KR100331278B1 - Method for fabricating DRAM device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a DRAM device manufacturing method having a gate line width of 0.1 탆 or less. In the DRAM device fabrication method of the present invention, when fabricating a memory cell transistor, an insulating film pattern corresponding to a source / drain region having a relatively wide line width is first manufactured, and then a gate electrode is formed by forming a conductive sidewall spacer on the sidewall of the insulating film pattern. Form. Subsequently, after removing the insulating layer pattern, impurities are implanted into semiconductor substrates on both sides of the gate electrode to form a source and a drain, thereby manufacturing a memory cell transistor. Subsequently, after the n-MOS transistor and the p-MOS transistor in the peripheral circuit region are manufactured by a conventionally known method, bit lines and capacitors are formed in the memory cell transistor region to complete the DRAM device fabrication. According to the present invention, since a memory cell transistor is manufactured using a photoresist pattern corresponding to a source drain region that is relatively wider than the gate line width, the photolithography process is large and the manufacturing process of the transistor is easy. In addition, since the gate electrode is formed by the method of forming the conductive sidewall spacer, the uniformity of the gate electrode line width is improved.

Description

DRAM device manufacturing method {Method for fabricating DRAM device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a DRAM (DRAM).

Referring to FIGS. 1A to 1C, a conventional DRAM manufacturing method will be described below. The DRAM may be divided into an array unit of memory cells including one transistor and one capacitor, and a peripheral circuit unit including an input / output circuit and the like. The transistor of the memory cell array portion is generally an n-channel MOS transistor formed in a p-type well and the peripheral circuit portion is composed of a CMOS (Complementary Metal Oxide Semiconductor) circuit. 1A to 1C, the left side is a memory cell array region and the right side is a peripheral circuit region, respectively, with a dashed line as the center.

First, as shown in FIG. 1A, a plurality of device isolation regions 102 are formed in the semiconductor substrate 100. The device isolation region 102 may be formed by local oxidation of silicon (LOCOS) or by a trench method. Regions other than the device isolation region 102 are referred to as active regions.

Next, an impurity is implanted into the active region to form a p-type well 104a in the active region of the memory cell array region and an n-type well 104b and a p-type well 104c in the peripheral circuit region, respectively. Next, the gate oxide film 106, the polysilicon film 108, the tungsten silicide film or the tungsten film 110 are sequentially stacked on the entire surface of the semiconductor substrate 100. Next, a nitride film 112 is formed on the tungsten film 110 to form a gate cap. Next, a photosensitive film mask 114 for forming the nitride film 112 gate electrode is formed.

Next, as shown in FIG. 1B, the nitride film 112, the tungsten silicide film 110, the polysilicon film 108, and the gate oxide film 106 are etched away using the photoresist mask 114 to form a gate electrode pattern 116. ). Next, p-type impurity ions are implanted into the n-type well 104b to form a lightly doped diffusion (LDD) region 117a in the semiconductor substrate 100 on both sides of the gate electrode pattern 116. do. Next, n-type impurity ions are implanted into the p-type wells 104a and 104c to form n-LED areas 117b in the semiconductor substrate 100 on both sides of the gate electrode pattern 116.

Next, the oxide film 118 and the nitride film 120 are sequentially formed on the entire surface of the structure formed on the semiconductor substrate 100.

Next, the anisotropic etching of the oxide film 118 and the nitride film 120 is performed without a mask to form sidewall spacers 122 on sidewalls of the gate electrode pattern 116 as shown in FIG. 1C.

Next, a mask pattern 124 is formed on the semiconductor substrate 100 in the memory cell array region, and p-type impurities are formed in the n-well 104b of the peripheral circuit region, and n-type in the p-well 104c. Impurities are implanted at high concentrations, respectively, to form the source and drain regions 128 of the p-MOS transistor 126, and the source and drain 132 of the n-MOS transistor 130 are sequentially formed.

Next, a capacitor, a bit line, and the like are formed in the cell array region to complete the manufacture of the DRAM.

However, the conventional DRAM cell manufacturing method described with reference to FIGS. 1A to 1C has a problem that it is difficult to apply to fabricate a highly integrated semiconductor device having a gate length of 0.1 μm or less in the following points.

First, in order to form a pattern having a fine line width of 0.1 μm, very expensive equipment is required in a photolithography process.

Second, there is a problem that the uniformity of the critical dimension cannot be guaranteed because the line width is very small. As a result, since the line width of the gate line is not uniform for each line, the electrical characteristics of each transistor are not uniform, which lowers the reliability of the semiconductor device.

Third, since the gate length becomes very narrow, such as 0.1 μm, there is a problem that a bridge or disconnection with an adjacent photoresist pattern may occur or deformation may occur when the photoresist mask pattern for forming the gate electrode is formed.

Fourth, even when the photoresist mask pattern having a fine line width is formed, the line width is very thin, which causes gate lines to collapse during the subsequent dry etching process.

Fifth, since the transistors in the cell array region having a dense and regular pattern and the transistors in the peripheral circuit region having irregular and low density must be formed at the same time, there are difficulties in the process such as the exposure process.

An object of the present invention for solving the above problems is to provide a DRAM device manufacturing method that can improve the non-uniformity of the bridge, disconnection, line width of the photosensitive film pattern when forming a gate line of 0.1㎛ or less.

It is still another object of the present invention to provide a DRAM device manufacturing method which improves the problem that the gate line falls when the gate line is formed.

It is still another object of the present invention to form a transistor in a memory cell array region without first forming a transistor in a cell array region and a peripheral circuit region having different properties at the same time, and then forming a transistor in the peripheral circuit region. It is to provide an easy DRAM device manufacturing method.

1 is a cross-sectional view showing a DRAM manufacturing process sequence according to the prior art.

2a to 2n are cross-sectional views showing a DRAM device manufacturing process sequence according to an embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

100: semiconductor substrate 102: device isolation region

104a: p-type well 104b, 104c: n-type well

106: gate oxide film 108: polysilicon film

110: tungsten film, tungsten silicide film 112: nitride film

114: photosensitive film mask 116: gate electrode pattern

117a: p-LDD 117b: n-LDD

118: oxide film 120: nitride film

122: sidewall spacer 124: mask pattern

126 source of p-MOS transistor 128 drain of p-MOS transistor

130: source of n-MOS transistor 132: drain of n-MOS transistor

A1: memory cell region A2: p-MOS transistor region

A3: n-MOS transistor area A2, A3: CMOS circuit area

200: semiconductor substrate 200a: active region

200b: inactive region 201a, 201c: p-type well

201b: n-type well 202: first oxide film

204: first photosensitive film pattern 206: gate oxide film

208: polysilicon film 210: metal film

212: second photosensitive film pattern

214: Gate electrode and sidewall spacer of memory cell transistor

216a: drain of the memory cell transistor

216b: source of memory cell transistor 218: second oxide film

220: first nitride film 222: first insulator spacer

224a: Bitline contact plug 224b: Storage node contact plug

226: third photosensitive film pattern

228: gate electrode of a p-MOS transistor

229: gate electrode of the n-MOS transistor

230: p-LDD 231: n-LDD

232: third oxide film 234: second nitride film

236: fourth photosensitive film pattern 238: second insulator spacer

239 source of p-MOS transistor 240 drain of p-MOS transistor

241 source of n-MOS transistor 242 drain of n-MOS transistor

244: fourth oxide film 246, 248: bit line contact hole

250: Ti film 251: TiN film

252: tungsten film 253: nitride film

254 bit line

256: third insulator spacer 258: fifth oxide film

260: storage node contact hole 262: conductive plug

264 capacitor electrode 266 dielectric film

268: capacitor plate electrode 270: capacitor

A DRAM device manufacturing method of the present invention for achieving the object of the present invention comprises the steps of preparing a semiconductor substrate having a memory cell region and a peripheral circuit region; Dividing the semiconductor substrate into an active region and an inactive region; Forming a p-type well in said memory cell region and in said n-MOS transistor region among said peripheral circuit regions; Forming an n-type well in an n-MOS transistor region of the peripheral circuit region; Forming an oxide film pattern on a predetermined portion of an active region of the memory cell region; Forming a gate oxide film over the entire structure on the semiconductor substrate; Forming a conductive film on the gate oxide film; Forming a first photoresist pattern on the conductive layer of the peripheral circuit region and performing a front anisotropic etching of the conductive layer of the memory cell region without a mask to form a conductive sidewall spacer type gate electrode on the sidewall of the oxide pattern; ; Removing the oxide film pattern; Implanting impurity ions into the active region of the region where the oxide film pattern is removed to form a source and a drain of the memory cell transistor; Forming first insulator spacers on opposite sides of gate electrodes of the memory cell transistors; Forming a storage node contact plug and a bit line contact plug on the source region and the drain region of the memory cell transistor, respectively; Forming a second photoresist layer pattern on the entire region of the memory cell region and the peripheral circuit region where the gate electrodes of the n-MOS transistor and the p-MOS transistor are to be formed; Forming a gate electrode of an n-MOS transistor and a p-MOS transistor by patterning a conductive film in the peripheral circuit area using the second photoresist pattern as a mask; Forming p-LDD by injecting p-type impurities into semiconductor substrates on both sides of the gate electrode of the p-MOS transistor; Forming n-LDD by injecting n-type impurities into the semiconductor substrate on both sides of the gate electrode of the n-MOS transistor; Forming a second insulator spacer on both sidewalls of the gate electrode of the n-MOS transistor and the gate electrode of the p-MOS transistor; Forming a source and a drain in the semiconductor substrate next to the second insulator spacer on both sidewalls of the gate electrode of the p-MOS transistor; Forming a source and a drain in the semiconductor substrate next to the second insulator spacer on both sidewalls of the gate electrode of the n-MOS transistor; Exposing an upper surface of the bit line contact plug after forming an oxide film over the entire structure on the semiconductor substrate; Forming a bit line to be connected to the bit line contact plug; Forming an oxide film on the entire structure obtained in the bit line forming step and then exposing an upper surface of the storage node contact plug; Forming a storage node electrode to be connected to the storage node contact plug; And forming a dielectric film and a plate electrode on an upper surface of the storage node electrode to manufacture a capacitor.

In the method of manufacturing a DRAM cell device of the present invention for achieving the object of the present invention, it is preferable that the process of forming the bit line contact plug and the storage node contact plug is a selective epitaxial growth method.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention. In addition, this embodiment does not limit the scope of the present invention, but is presented by way of example only.

2A to 2N show a manufacturing process sequence of the DRAM device according to the present invention. In the DRAM device manufacturing process of the present invention, the transistors of the peripheral circuits are sequentially manufactured after the memory cell transistors are manufactured without forming the memory cell transistors and the transistors of the peripheral circuits at the same time.

First, a process of manufacturing a memory cell transistor will be described with reference to FIGS. 2A through 2F, and then a peripheral circuit transistor is manufactured through the process of FIGS. 2G through 2M to complete the manufacture of the DRAM of the present invention.

First, as shown in FIG. 2A, the active region 200a and the inactive region 200b are formed in the semiconductor substrate 200. The inactive region 200b may be formed by forming a trench in the semiconductor substrate 200 and then filling the trench with an oxide, or other well-known local oxidation of silicon (LOCOS) or another method. Can be formed. 2A to 2R, A1 is a memory cell area among the areas A1, A2, and A3 divided around the broken line. A2 and A3 are peripheral circuit regions, in which A2 is a p-channel transistor region and A3 is an n-channel transistor region.

Next, p-type impurity ions are implanted into the memory cell region A1 and the n-channel transistor region A3 in the semiconductor substrate 200 to form a p-type well. n-type impurity ions are implanted into the p-channel transistor region A2 to form an n-type well.

Next, after forming a thick first oxide film on the entire surface of the semiconductor substrate 200, a first photosensitive film pattern 204 is formed on the first oxide film. Since the first photoresist layer pattern 204 is a storage node contact portion, the first photoresist pattern 204 is formed at a corresponding position, and the width w corresponds to a diameter of a storage node contact hole to be formed later or a distance between each gate electrode and a gate electrode. . When manufacturing a memory cell having a gate electrode length of 0.1 μm, the photoresist pattern 204 is formed to have a width of 0.15 μm to 0.16 μm. Therefore, the conventional method reduces the stringency of the process and the burden of the photolithography process as compared with the need to form a photosensitive film pattern of 0.1㎛.

FIG. 2B is a longitudinal sectional view taken along line IIb-IIb in FIG. 2A. In FIG. 2A, the same reference numerals as used in FIG. 2B denote the same components, and thus descriptions thereof will be omitted. However, the first oxide film 202, which is not shown in the plan view of FIG. 2A, is shown, and the p-type wells 201a and 201c and the n-type well 201b are shown.

Next, the first oxide film 202 is etched using the first photosensitive film pattern 204 of FIG. 2B as a mask to form an oxide film pattern 202a as shown in FIG. 2C. Next, a gate oxide film 206, a polysilicon film 208 doped with n-type impurities, and a metal film 210 are sequentially stacked on the oxide pattern 202a and the entire surface of the semiconductor substrate 200. The metal film is preferably formed of tungsten or tungsten silicide.

Next, as shown in FIG. 2D, a second photoresist layer pattern 212 is formed on the metal layer 210 in the peripheral circuit regions A2 and A3.

Next, as shown in FIG. 2E, anisotropic etching is performed on the metal film 210 and the polysilicon film 208 of the memory cell region A1 using the second photoresist film pattern 212 as a mask to form the oxide film pattern ( On the sidewall of 202a, sidewall spacers 214 made of the polysilicon film 208 and the metal film 210 are formed.

Next, when the second photoresist layer pattern 212 is removed, the polysilicon layer 208 and the metal layer 210 remain on the semiconductor substrate 200 in the peripheral circuit regions A2 and A3.

The sidewall spacers 214 made of the polysilicon film 208 and the metal film 210 operate as gate electrodes of memory cell transistors. The width (channel length) of the gate electrode line is equal to the width L of the bottom surface of the sidewall spacer 214. Therefore, the width of the sidewall spacer, that is, the line of the gate electrode 214 is determined by the deposition process of the polysilicon film 208 and the metal film 210. That is, as the metal film 210 and the polysilicon film 208 are formed thicker, the width of the sidewall spacer, that is, the width of the gate electrode line becomes wider. Therefore, in order to obtain a desired length of the gate electrode, the deposition thickness of the polysilicon film 208 and the metal film 210 should be adjusted in advance. In the semiconductor device manufacturing process, the thickness uniformity is sufficiently secured when the thin film such as the polysilicon film 208 or the metal film 210 is deposited, and thus the thickness error is only about 1%. The error of the electrode line width can also be suppressed to about 1% to obtain high uniformity.

Next, as shown in FIG. 2F, the oxide pattern 202a is selectively etched away, and then n-type impurities are implanted into the p-type well 201a of the memory cell region A1 using the gate electrode 214 as a self-alignment mask. Thus, the drain 216a and the source region 216b are formed. That is, the manufacturing of the memory cell transistor is completed through the process of FIGS. 2A to 2F.

Next, the second oxide film 218 and the first nitride film 220 are sequentially deposited on the structure obtained in the source 216a and drain 216b region forming steps.

Next, as shown in FIG. 2g, the first nitride film 220 and the second oxide film 218 are anisotropically etched without a mask to form first insulator spacers 222 on both sides of the gate electrode 214. . Next, n-type impurities are formed only on the drain 216a and the source 216b between the gate electrode 214 and the adjacent gate electrode 214 by using selective epitaxial growth (SEG). Doped n-doped silicon layers 224a, 224b are formed. The n-doped silicon layer 224a formed on the upper surface of the drain 216a is a bit line contact plug connected to the bit line, and the n-doped silicon layer 224b formed on the upper surface of the source 216b is a storage node electrode of the capacitor. The storage node contact plug to be connected to.

The heights of the plugs 224a and 224b are formed only to a height slightly lower than the upper end of the gate electrode 214. This is because adjacent plugs 224a and 224b are shorted when the heights of the plugs 224a and 224b become higher than the vertex of the gate electrode 214.

Since the width of the gate electrode 214 decreases upward as shown in FIG. 2G, the areas of the conductive plugs 224a and 224b become wider toward the upper side than the areas in contact with the semiconductor substrate 200. As a result, the alignment margin is increased when forming the bit line contact hole in a subsequent process.

Next, a photoresist film is formed over the entire structure of FIG. 2G and then patterned to form a third photoresist pattern 226 as shown in FIG. 2H. The third photoresist pattern 226 covers the entire structure of the memory cell region A1, and covers the positions where the gate electrodes of the n-MOS transistor and the p-MOS transistor are formed in the peripheral circuit regions A2 and A3. It is formed to. Next, the metal film 210 and the polysilicon film 208 of the peripheral circuit regions A2 and A3 are etched using the third photoresist pattern 226 as a mask, and as shown in FIG. Gate electrodes 228 and 229 are formed in regions A2 and A3, respectively. The gate electrode 228 formed in the p-MOS transistor region A2 is the gate electrode of the p-MOS transistor, and the gate electrode 229 formed on the n-MOS transistor region A3 is the gate electrode of the n-MOS transistor.

Next, a mask pattern is formed in the memory cell region A1 and the n-MOS transistor region A3. Then, as shown in FIG. 2I, the n-type wells 201b at both sides of the gate electrode 228 of the p-MOS transistor are formed. P-type impurity ions are implanted into the p-LDD 230. Next, a mask pattern is formed in the memory cell region A1 and the p-MOS transistor region A2. The n-LDD 231 is formed by ion implanting n-type impurity ions into the p-type well 201c at both sides of the gate electrode 229 of the n-MOS transistor.

Next, a third oxide film 232 and a second nitride film 234 are deposited on the entire structure obtained after the p-LDD 230 and n-LDD 231 forming steps.

Next, after forming the fourth photoresist layer pattern 236 on the memory cell region A1 as shown in FIG. 2J, the second nitride layer 234 and the third oxide layer of the peripheral circuit regions A2 and A3 are formed. An anisotropic etching of the entire surface 232 is performed without a mask to form a second insulator spacer 238 on sidewalls of the gate electrode 228 of the p-MOS transistor and the gate electrode 229 of the n-MOS transistor.

Next, a photoresist pattern is formed on the memory cell region A1 and the n-MOS transistor region A3, and the gate electrode 228 and the second insulator spacer 238 are formed as a mask using a self-aligning mask. P-type impurities are implanted into the n-type well 201b to form the source 239 and the drain 240 of the p-MOS transistor.

Next, a photoresist pattern is formed on the memory cell region A1 and the p-MOS transistor region A2, and the gate electrode 229 and the sidewall spacer 238 are used as a self-aligning mask to form a mask. N-type impurities are implanted into the p-type well 201c to form the source 241 and the drain 242 of the n-MOS transistor.

Next, as shown in FIG. 2K, a thick fourth oxide film 244 is formed over the entire structure of FIG. 2J, and then patterned to form bit line contact holes 246 and 248. The bit line contact hole 246 of the memory cell region is formed on the bit line contact plug 224a on the upper surface of the drain 216a region of the memory cell transistor, and the contact hole 248 of the peripheral circuit region is a p-MOS transistor. Is formed over the gate electrode 228. When the contact hole 246 is formed, the second nitride film 234 and the third oxide film 232 under the fourth oxide film 244 are also etched to expose the top surface of the conductive plug 224a. To form. In this case, the second nitride film 234 and the third oxide film 232 are gate hard masks for preventing the top surface of the gate electrode 214 from being etched by misalignment when the contact hole 246 is formed. Is used.

Next, the Ti250 / TiN film 251, the tungsten film 252, and the nitride film 253 are sequentially deposited on the entire structure of FIG. 2K, and then patterned to form the bit line contact plug 224a and the peripheral circuit. A bit line 254 is formed to be connected to the gate electrode 228 of the p-MOS transistor of FIG. Next, in forming a subsequent storage node contact hole, a third insulator spacer 256 is formed on both sidewalls of the bit line 254 for use as a mask.

Next, as shown in FIG. 2M, a thick fifth oxide film 258 is formed over the entire structure of FIG. 2L, and then a photoresist pattern mask (not shown) for forming a storage node contact on the oxide film 258 is shown. After forming the photoresist layer, the fifth oxide layer 258 is etched using the photoresist pattern as a mask to form a storage node contact hole 260 to expose an upper surface of the storage node contact plug 224b.

Next, as illustrated in FIG. 2N, a new conductive plug 262 is formed by growing polysilicon on the upper surface of the storage node contact plug 224b exposed through the contact hole 260 by a selective epitaxial growth method. Form.

Next, a polysilicon film is deposited on the top surface of the conductive plug 262 and the top surface of the fifth oxide film 258 and then patterned to form a storage node electrode 264 on the conductive plug 262, and the node electrode. The dielectric film 266 and the plate electrode 268 of the capacitor are sequentially deposited on 264 to form the capacitor 270 constituting the memory cell, thereby completing the manufacture of the DRAM device of the present invention.

As described above, according to the present invention, since the memory cell transistor is first manufactured and then the transistor of the peripheral circuit is manufactured, the manufacturing process is easy.

Further, according to the present invention, since the gate electrode is formed in the form of sidewall spacers, the uniformity of line widths of the gate electrode lines can be improved, and as a result, the uniformity of electrical characteristics of the memory cell transistors can be improved.

In addition, according to the present invention, when the photoresist pattern is formed to form a gate electrode line having a thickness of 0.1 μm, bridge, disconnection, and non-uniformity of the photoresist pattern are improved, and the gate electrode collapses in a dry etching process for forming the gate electrode. In this regard, there is an effect of facilitating a manufacturing process of a DRAM cell having a gate line width of 0.1 μm or less.

Claims (9)

Claim 1 has been deleted. Claim 2 has been deleted. Claim 3 has been deleted. Claim 4 has been deleted. Claim 5 has been deleted. Preparing a semiconductor substrate having a memory cell region and a peripheral circuit region; Dividing the semiconductor substrate into an active region and an inactive region; Forming a p-type well in said memory cell region and in an n-MOS transistor region of said peripheral circuit region; Forming an n-type well in an n-MOS transistor region of the peripheral circuit region; Forming an oxide film pattern on a predetermined portion of an active region of the memory cell region; Forming a gate oxide film over the entire structure on the semiconductor substrate; Forming a conductive film on the gate oxide film; Forming a first photoresist pattern on the conductive layer of the peripheral circuit element region and performing a front anisotropic etching of the conductive layer of the memory cell region without a mask to form a conductive sidewall spacer type gate electrode on the sidewall of the oxide pattern; ; Removing the oxide film pattern; Implanting impurity ions into the active region of the portion from which the oxide film pattern is removed to form a source and a drain of the memory cell transistor; Forming first insulator spacers on both sides of gate electrodes of the memory cell transistors; Forming a storage node contact plug and a bit line contact plug on the source region and the drain region of the memory cell transistor, respectively; Forming a second photoresist pattern on a portion of the memory cell region and a peripheral circuit region where a gate electrode of an n-MOS transistor and a p-MOS transistor is to be formed; Forming a gate electrode of an n-MOS transistor and a p-MOS transistor by patterning a conductive film in the peripheral circuit area using the second photoresist pattern as a mask; Forming p-LDD by injecting p-type impurities into semiconductor substrates on both sides of the gate electrode of the p-MOS transistor; Forming n-LDD by injecting n-type impurities into the semiconductor substrate on both sides of the gate electrode of the n-MOS transistor; Forming a second insulator spacer on both sidewalls of the gate electrode of the n-MOS transistor and the gate electrode of the p-MOS transistor; Forming a source and a drain in the semiconductor substrate next to the second insulator spacer on both sidewalls of the gate electrode of the p-MOS transistor; Forming a source and a drain in the semiconductor substrate next to the second insulator spacer on both sidewalls of the gate electrode of the n-MOS transistor; Exposing an upper surface of the bit line contact plug after forming an oxide film over the entire structure on the semiconductor substrate; Forming a bit line to be connected to the bit line contact plug; Exposing an upper surface of the storage node contact plug after forming an oxide film on the entire structure obtained in the bit line forming process; Forming a storage node electrode to be connected to the storage node contact plug; And And forming a dielectric film and a plate electrode on an upper surface of the storage node electrode to manufacture a capacitor. The method of claim 6, wherein the forming of the bit line contact plug and the storage node contact plug is performed by a selective epitaxial growth method. The method of claim 6, wherein the conductive film has a laminated structure of a polysilicon film and a metal film. The method of claim 8, wherein the metal film is tungsten or tungsten silicide.