KR100333360B1 - A method of fabricating a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a bit line is formed in a trench on a substrate, and then a transistor and a capacitor are formed thereon to secure a margin between the bit line and the storage node, so that they may be shorted to each other. The present invention relates to a method of manufacturing a memory device of a semiconductor device, in which the process is simplified by removing the and forming the storage electrode node in one process. In the method of manufacturing a semiconductor device according to the present invention, a field insulating film of a semiconductor substrate having a field region formed of a field insulating film isolating a plurality of active regions is removed to a predetermined thickness, and is formed long in a first direction along a field region between the active regions. Forming a trench, filling a trench with a conductive layer to form a bit line, forming a first insulating film on a surface of the semiconductor substrate including the bit line, and removing a predetermined portion of the first insulating film Simultaneously forming a first opening exposing a portion of the bit line and the bit line contact portion of the active region and a pair of second openings positioned at both sides of the first opening and exposing a predetermined portion of the active region of the gate forming portion. Forming a pair of second plugs and a conductive first plug filling the first to second openings; And a gate insulating film, a gate, and gate sidewall spacers having an impurity diffusion region formed at a predetermined portion of the active region, wherein at least one pair includes a plurality of gate patterns passing through the pair of second plugs of the active region. Forming a second insulating film as an interlayer insulating film on the first insulating film including the gate pattern, and then removing predetermined portions of the second insulating film and the first insulating film to form a gate pattern in which the first opening is not formed. And forming a contact hole exposing the surface of the active region located therebetween, and forming a conductive third plug filling the contact hole and a capacitor in contact with the third plug.

Description

A method of fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a bit line is formed in a trench on a substrate, and then a transistor and a capacitor are formed thereon to secure a margin between the bit line and the storage node, so that they may be shorted to each other. The present invention relates to a method of manufacturing a memory device of a semiconductor device, in which the process is simplified by removing the and forming the storage electrode node in one process.

1A to 1D illustrate cross-sectional views of a semiconductor device manufacturing process.

Referring to FIG. 1A, a field oxide film 12 is formed on a P-type semiconductor substrate 11 by a method such as LOCOS (Local Oxidation of Silicon) to define an active region and a field region in which an element is to be formed. A gate insulating film 13, a gate 14, a cap nitride film 15, a nitride film side wall 16 and a source / drain (not shown) are formed in the active region by patterning a photolithography process to form a transistor for a DRAM cell. Manufacture. In this case, the cap nitride layer 15 serves as a mask when the gate 14 is formed, and the nitride layer side wall 16 serves as an insulating layer sidewall for forming a self-aligned contact when forming the first storage node in a subsequent process.

Referring to FIG. 1B, a first HDL layer 17 is deposited on the entire surface of the substrate 11 including the gate 14. Then, the first BPS layer (boronphospho silicate glass, 18) for planarization is formed thereon. The first BPS layer 18 is planarized, and then photolithography is used to pattern the portion where the first storage node between the transistors is to be formed to expose the surface of the active region of the substrate.

Then, a polysilicon layer doped with a conductive material is deposited on the entire surface, and then etched back to form a first storage node 19 while exposing the surface of the first BPS layer 18.

Referring to FIG. 1C, a second HDL layer 20 is formed by depositing a second HDL layer 20 on a front surface of a substrate including an upper surface of the first storage node 19, and then adjacent to the first storage node 19. The photolithography process of exposing the active region between the two transistors is performed to form a bit line contact forming mask 20 formed of the remaining second HDL layer 20. Dry etching using the mask 20 is performed to expose the active region of the bit line contact region. Then, the doped polysilicon is deposited on the entire surface to completely fill the bit line contact portion, and then pattern the bit line 21.

At this time, the bit line 21 is not shown because the drawing is a cross-sectional view along the cutting line, but is formed in a shape that runs long orthogonal to the length direction of the gate 14 on the field oxide film 12 between the active regions.

Referring to FIG. 1D, a third HDL layer 22 is deposited on the entire surface of the substrate including the exposed bit line 21 surface, and then a nitride film 23 is formed by depositing a stopper layer thereon. . In order to planarize, a second BPS layer 24 is formed and planarized on the nitride film 23.

Next, a via hole exposing the top surface of the first storage node 19 to form a portion where the second storage node is to be formed is formed by the second BPS layer 24, the nitride layer 23, and the third H. The predetermined portions of the LED layer 22 and the second HDL layer 20 are removed by a photolithography process.

After forming a polysilicon layer doped with a conductive material on the exposed surface of the via hole and the surface of the second BPS layer 24, a mask pattern (not shown) is defined thereon, and the polysilicon layer is patterned using the polysilicon layer. The second storage node 25 is formed.

Therefore, the second storage node 25 has a high risk of shorting with the bit line 21 formed to run long in the width direction of the gate 14, and thus has a very poor process margin.

Then, the doped polysilicon layer is deposited on the entire surface of the substrate including the mask pattern and etched back to form a sidewall 26 made of polysilicon remaining on the side of the mask pattern. Form a third storage node 26 or electrode.

Subsequently, the mask pattern is removed by wet etching, and then a dielectric layer (not shown) made of silicon oxide or silicon oxide / silicon nitride is formed on the exposed surfaces of the third and second storage nodes 26 and 25, and then plated thereon. The electrode is formed to complete the DRAM cell.

However, the above-described conventional semiconductor device improves the resistance problem by forming a storage node in this step when the capacitor has a structure on a bit line in the highly integrated DRAM cell, but improves the resistance problem. 2 Because the process margin between storage node and bitline is very small, self-aligned photolithography and etching process should be used. This process is complicated and the process margin is also small, which reduces device reproducibility and is efficient for high integration of cells. There is a problem.

Accordingly, an object of the present invention is to manufacture a semiconductor device in which a bit line is first formed on a substrate, and then a device such as a transistor and a capacitor is completely manufactured, thereby completely eliminating a short circuit between the capacitor storage electrode node and the bit line and simplifying a DRAM cell manufacturing process. To provide a method.

A semiconductor device manufacturing method according to the present invention for achieving the above object is removed along the field region between the active region by removing a field insulating film of the semiconductor substrate having a field region consisting of a field insulating film isolating a plurality of active regions to a predetermined thickness Forming a trench elongated in a first direction, forming a bit line by filling an inside of the trench with a conductive layer, forming a first insulating film on a surface of the semiconductor substrate including the bit line, A pair of first and second openings disposed at both sides of the first opening and the first opening to expose a portion of the bit line and the bit line contact portion of the active region by removing a predetermined portion of the insulating layer; Simultaneously forming two openings, and a conductive first plug for filling the first to second openings. Forming a pair of second plugs, and having an impurity diffusion region formed at a predetermined portion of the active region, the gate plug including a gate insulating film, a gate, and a gate sidewall spacer, and at least one pair of the second plugs of the active region Forming a plurality of gate patterns extending in a second direction, forming a second insulating film as an interlayer insulating film on the first insulating film including the gate pattern, and then removing predetermined portions of the second insulating film and the first insulating film (1) forming a contact hole exposing a surface of an active region located between the gate patterns in which the opening is not formed, and forming a conductive third plug filling the contact hole and a capacitor in contact with the third plug It is made to include.

1A to 1D are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A to 5B are a manufacturing process layout and cross-sectional view of a semiconductor device according to the present invention.

In general, in a capacitor on bit line structure when forming a highly integrated DRAM cell, the possibility of shorting between the storage node contact and the bit line should be considered when forming the storage node. In order to solve this problem, in the related art, as the contact size of the second storage node is made small to secure a margin for an electrical short with the bit line, the second storage node contact separate from the first storage node contact due to the small contact size Must be formed and connected again, and a separate cylindrical storage node must be formed to secure the capacity of the capacitor.

In the present invention, a trench-type bit line is first formed on a substrate, and then gate lines and capacitors are formed to completely eliminate the possibility of a short circuit between the storage electrode node and the bit line, thereby sufficiently securing the subsequent process margin.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2A to 5B are a manufacturing process layout and a cross-sectional view of a semiconductor device according to the present invention. 2A, 3A, 4A, and 5A are layouts according to the manufacturing process, and FIGS. 2B, 3B, 4B and 5B are sectional views of each manufacturing process along the cutting lines X-X 'to Y-Y' of the layout.

2A and 2B, a predetermined region of the silicon substrate 40, which is a semiconductor substrate, is removed by photolithography to form a trench, thereby forming a field region, which is an isolation region.

The trench portion is filled with an oxide film as an insulating film to form a field oxide film 41. Therefore, the field oxide film 41 has a form connected to each other in the substrate 40, the upper portion of the substrate on which the field oxide film 41 is not formed becomes a plurality of active regions 42, the active regions 42 The islands are separated from each other by the field oxide film 41.

Then, a plurality of line-shaped bit line forming trenches are removed by removing a predetermined portion of the field oxide film 41 between the active regions 42 in a direction orthogonal to the cutting line X-X 'to a predetermined thickness. It is formed by photolithography.

Then, an insulating film 43 which covers the bit inner surface of the bit line forming trench is thinly formed by depositing a nitride film by chemical vapor deposition or the like. In this case, the nitride film 43 formed on the inner surface of the trench is formed at the interface between the bit line and the substrate to be insulated from each other.

Next, a tungsten layer is formed on the entire surface of the substrate by a sputtering method with a conductive layer having a thickness of completely filling the trench in which the insulating film 43 is formed, and then the tungsten layer is etched back so that the surface of the substrate or the surface oxide film 41 is exposed. As a result, a bit line 44 made of a tungsten layer remaining in the trench is formed.

Referring to FIGS. 3A and 3B, an oxide film 45 is formed by chemical vapor deposition on an entire surface of a substrate using an insulating film having a predetermined thickness.

A predetermined portion of the oxide film 45 is removed by photolithography to form an opening for exposing a contact hole for forming a bit line contact portion of the active region 42 and an active region portion through which a gate to be formed later passes. In this case, the contact hole for forming the bit line contact portion is formed to simultaneously expose the active region and a predetermined portion of the bit line 44 adjacent thereto. That is, a contact hole extending in the direction of the bit line 44 is formed in the common impurity diffusion regions of the gates to be formed to pass through the active region 42 in the Y-Y 'direction.

Then, the contact hole and the opening are completely filled with a conductive layer such as doped polysilicon or metal to form the bit line contact plug 46 and the gate connection plug 47. At this time, the plugs 46 and 47 are formed by depositing a conductive layer on the oxide film 45 and then performing etch back or chemical mechanical polishing on the conductive layer.

In a typical MOS transistor manufacturing method, a plurality of gate patterns 48 formed of a gate insulating film, a gate, a gate sidewall spacer, and the like are formed on the substrate so as to be perpendicular to the formation direction of the bit line 44 on the oxide film 45.

Next, although not shown, an impurity diffusion region is formed on the substrate of the active region 42 using the gate pattern 48 as an ion implantation mask. At this time, in the case of forming a lightly doped drain (LDD) structure, a low concentration impurity diffusion region is formed in a predetermined portion of the active region of the substrate before the gate sidewall spacer is formed, and then a high concentration impurity diffusion region using the gate pattern 48 is formed. Form a drain.

4A and 4B, an interlayer insulating layer 49 is formed on the entire surface of the oxide film 45 including the gate pattern 48 with an oxide film, and then the interlayer insulating layer 49 / oxide film is formed by photolithography. A predetermined portion of 45 is removed by photolithography to form a contact hole exposing the storage node contact portion of the active region 42. In this case, the contact hole may be formed as a self-aligned contact hole by etching by forming a sidewall again on the sidewall spacer surface after the impurity diffusion region is formed.

Then, a conductive layer such as polysilicon doped with impurities is formed on the interlayer insulating layer 49 to fill the contact hole, and then etched back to form a storage electrode node plug having a conductive layer remaining in the contact hole. 50).

5A and 5B, the storage electrode 51 is formed using polysilicon doped with impurities so as to contact each of the storage electrode node plugs 50. In the figure, a cylindrical storage electrode was formed.

Subsequently, although not shown, a capacitor is formed by forming a dielectric film and a plate electrode on the storage electrode, thereby completing a DRAM cell including a capacitor and a transistor.

Therefore, the present invention forms a bit line in the form of a trench on the substrate, and then forms a transistor and a capacitor thereon to secure a margin between the bit line and the storage node, eliminating the possibility that they are short-circuited with each other, and the storage electrode node once. By forming the process has the advantage of simplifying the process.

Claims (5)

Forming a trench formed in the longitudinal direction of the active region along the field region between the active regions by removing the field insulating layer of a semiconductor substrate having a field region formed of a field insulating layer to isolate a plurality of active regions to a predetermined thickness; Steps, Filling the inside of the trench with a conductive layer to form a bit line; Forming a first insulating film on a surface of the semiconductor substrate including the bit line; A first opening exposing a portion of the bit line and a bit line contact portion of the active region by removing a predetermined portion of the first insulating layer, and located at both sides of the first opening, the predetermined portion of the active region of the gate forming portion; Simultaneously forming a pair of second openings exposing the site, Forming a pair of second plugs and a conductive first plug to fill the first to second openings; And a gate insulating film, a gate, and a gate sidewall spacer formed on a predetermined portion of the active region, wherein at least one pair includes a plurality of gate patterns passing through the pair of second plugs of the active region. The mold is elongated in a direction orthogonal to the trench formation direction on the first insulating layer. Your sexual steps, A second insulating film is formed as an interlayer insulating film on the first insulating film including the gate pattern, and then, a portion of the second insulating film and the first insulating film is removed to be positioned between the gate pattern where the first opening is not formed. Forming a contact hole exposing a surface of the active region; Forming a conductive third plug filling the contact hole and a capacitor in contact with the third plug. The method of claim 1, wherein the bit line is formed by interposing an insulating film at an interface with the trench surface. Claim 3 has been deleted. The method of claim 1, wherein the impurity diffusion region comprises a low concentration impurity diffusion region and a high concentration impurity diffusion region. The method of claim 1, wherein after forming the impurity diffusion region, the contact hole is formed as a self-aligned contact hole by etching a sidewall on the sidewall spacer surface.