KR20040086704A - Method for manufacturing capacitor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to enhance capacitance by forming a lower electrode with a spacer shape in a contact hole and to simplify the process by patterning simultaneously the lower electrode and an upper electrode. CONSTITUTION: An insulating layer(30) is formed on a semiconductor substrate(21) with a transistor. A contact hole is formed to expose a junction region of the transistor by selectively etching the insulating layer. A lower electrode(34a) with a spacer shape is formed at inner walls of the contact hole. A dielectric film(35) is formed on the lower electrode. Then, an upper electrode(36a) is formed by filling a conductive layer in the contact hole.

Description

Method for manufacturing capacitor in a semiconductor device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor having a laminated structure to maximize the capacitance by increasing the effective surface area of the lower electrode.

In general, a memory cell of a memory device such as a DRAM includes a capacitor and a transistor for storing or reading information in the capacitor. The capacitor is configured such that the lower electrode is connected to the junction region of the transistor formed on the semiconductor substrate, and the connection between the junction region and the lower electrode is made through a contact hole formed in the insulating film.

1A to 1G are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device having a stacked structure as described above.

Referring to FIG. 1A, a well 3 is formed in a semiconductor substrate 1 on which a device isolation film 2 having a shallow trench form is formed, and a gate oxide film (1) is formed on the semiconductor substrate 1 of the well 3. 4) and the gate electrode 5 are laminated. Low concentration impurity ions are implanted into the exposed semiconductor substrate 1 on both sides of the gate electrode 5 to form the LDD region 6, and then spacers 7 are formed on both sides of the gate electrode 5 with an insulating film. High concentration impurity ions are implanted into the semiconductor substrate 1 to complete the junction region 8 of the LDD structure. A cobalt silicide layer 9 is formed on the surfaces of the gate electrode 5 and the junction region 8 by a self-aligned silicide process.

Referring to FIG. 1B, after fabricating a transistor in a general CMOS process as described above, the surface is planarized by coating a BPSG (Boro Phosphorus Silica Glass) film 10 having a thickness of 5000 에 on the entire upper surface thereof, and flattening the surface thereof. A buffer layer 11 having a thickness of 200 μs is formed.

Referring to FIG. 1C, after the photoresist layer 12 is formed on the buffer layer 11, the photoresist layer 12 is patterned by using a contact hole forming mask, and the buffer layer of the portion exposed by the dry etching process using the patterned photoresist 12 as a mask. (11) and the BPSG film 10 are sequentially etched to form the contact holes 13 to expose the junction region 8 between the gate electrodes 5.

Referring to FIG. 1D, after removing the photoresist film 12, polysilicon 14 having about 4000 μs is deposited on the entire upper surface such that the contact hole 13 is completely filled.

Referring to FIG. 1E, after the photoresist film 15 is formed on the polysilicon layer 14, the polysilicon layer is formed by a dry etching process using a mask for forming a lower electrode and using the patterned photoresist 15 as a mask. (14) is patterned to form the lower electrode 14a of the capacitor.

Referring to FIG. 1F, after removing the photosensitive film 15, a dielectric film 16 of a capacitor including a nitride film 16a having a thickness of 60 μs and an oxide film 16b having a thickness of 80 μs is formed on an entire upper surface thereof, and polysilicon is formed on the entire upper surface thereof. Form layer 17. After the photoresist film 18 is formed on the polysilicon layer 17, the photoresist film is patterned using a mask for forming an upper electrode.

Referring to FIG. 1G, the polysilicon layer 17 is patterned by an etching process using the patterned photosensitive film 18 as a mask to form the upper electrode 17a of the capacitor, and then the photosensitive film 18 is removed.

As described above, after forming a transistor in a CMOS process, a contact hole is formed in an insulating layer to expose a junction region, and a lower electrode is formed to be connected to the junction region through the contact hole. Therefore, as the semiconductor memory device increases in speed, capacity, and high integration, the area occupied by the unit memory cell is greatly reduced, and thus the effective surface area of the lower electrode is greatly reduced, thus making it difficult to secure the capacitance required for the operation of the device. .

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of solving the above-mentioned disadvantages by maximizing an effective surface area by forming a spacer-type lower electrode on a sidewall of a contact hole.

According to an aspect of the present invention, a transistor is formed on a semiconductor substrate through a predetermined process to form and planarize an insulating film on the entire upper surface thereof, and pattern the contact to expose the junction region of the transistor. Forming a hole, depositing a conductive material having a predetermined thickness on surfaces of the contact hole and the insulating layer to form a spacer-type lower electrode on the sidewall of the contact hole, and forming a dielectric layer on the lower electrode And depositing a conductive material to fill the contact hole to form an upper electrode.

And forming a buffer layer on the insulating film, wherein the conductive material is polysilicon, and the dielectric film is formed of a nitride film and an oxide film.

1A to 1G are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

2A to 2G are cross-sectional views illustrating a method for manufacturing a capacitor of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 21: semiconductor substrate 2, 22: device isolation film

3, 23: well 4, 24: gate oxide film

5, 25: gate electrode 6, 26: LDD region

7, 27: spacer 8, 28: junction region

9, 29: silicide layer 10, 30: BPSG film

11, 31: buffer layer 12, 15, 18, 32, 37: photosensitive film

13, 33: contact holes 14, 17, 34, 36: polysilicon layer

14a and 34a: lower electrode 16 and 35: dielectric film

16a, 35a: nitride film 16b, 35b: oxide film

17a, 36a: upper electrode

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Referring to FIG. 2A, a well 23 is formed in a semiconductor substrate 21 on which a shallow trench type isolation layer 22 is formed, and a gate oxide film 24 and a gate are formed on the semiconductor substrate 21 of the well 23. A structure in which the electrodes 25 are stacked is formed. Low concentration impurity ions are implanted into the exposed semiconductor substrate 21 on both sides of the gate electrode 25 to form the LDD region 26, and then spacers 27 are formed on both sides of the gate electrode 25 with an insulating film. High concentration impurity ions are implanted into the semiconductor substrate 21 to complete the junction region 28 of the LDD structure. Cobalt (Co) silicide layer 29 is formed on the surfaces of the gate electrode 25 and the junction region 28 by a self-aligned silicide process.

Referring to FIG. 2B, after the transistor is manufactured in the CMOS process as described above, the BPSG film 30 having a thickness of 6000 to 10000 μs is applied to the entire upper surface to planarize the surface, and the thickness of the 200 to 400 μm thickness is applied to the BPSG film 30. The buffer layer 31 is formed. The buffer layer 31 is formed of a nitride film to prevent the exposure of the BPSG film 30 during the subsequent etching process.

Referring to FIG. 2C, after the photoresist layer 32 is formed on the buffer layer 31, the photoresist layer is patterned using a contact hole forming mask, and the buffer layer of the portion exposed by the dry etching process using the patterned photoresist layer 32 as a mask. (31) and the BPSG film 30 are sequentially etched to form the contact holes 33 so that the junction region 28 between the gate electrodes 25 is exposed.

Referring to FIG. 2D, after removing the photoresist film 32, a polysilicon layer 34 having a predetermined thickness is formed on the surfaces of the contact hole 33 and the buffer layer 31, and the nitride film () is formed on the surface of the polysilicon layer 34. A dielectric film 35 of a capacitor composed of 35a) and an oxide film 35b is formed. After that, the polysilicon layer 36 having a thickness of 1500 to 2500 Å is formed on the entire upper surface of the contact hole 33 to be filled. In this case, the polysilicon layer 34 is formed to have a thickness of 800 to 1200Å so that a spacer shape made of polysilicon is formed on the sidewall of the contact hole 33, and the nitride film 35a is 40 to 60 에서 at a temperature of 600 ° C. The thickness of the oxide film 35b is formed to a thickness of 50 to 80 kPa at a temperature of 700 ℃ so that the contact hole 33 is not completely embedded. In addition, the polysilicon layer 34, the dielectric film 35, and the polysilicon layer 36 are continuously formed without time delay to improve the characteristics of the dielectric film 35.

Referring to FIG. 2E, a rapid heat treatment (RTP) method is performed for 20 to 40 seconds at a temperature of 700 to 900 ° C. and a nitrogen (N ₂ ) gas atmosphere to activate the polysilicon layer 36 to increase its conductivity.

Referring to FIG. 2F, the photosensitive film 37 is formed on the polysilicon layer 36 and then patterned using a mask for forming an upper electrode. The polysilicon layer 36, the dielectric layer 35, and the polysilicon layer 34 are sequentially patterned by a dry etching process using the patterned photosensitive film 37 as a mask.

Referring to FIG. 2G, the photosensitive film 37 is removed to complete a capacitor in which the lower electrode 34a, the dielectric film 35, and the upper electrode 36a are stacked.

As described above, the present invention increases the effective surface area of the lower electrode by forming a contact hole in the insulating film so that the junction region is exposed after forming the transistor through a CMOS process and forming a spacer-type lower electrode in the contact hole. By forming the dielectric film without time delay after forming the dielectric property is improved, the capacitance of the capacitor is effectively increased. In addition, by lowering the upper electrode and the upper electrode by a single photo and etching process, the process can be simplified to achieve cost reduction, and process conditions and process margins can be secured to improve yield. Therefore, by using the present invention, it is possible to manufacture highly integrated high performance semiconductor memory devices having increased capacitance.

Claims (6)

Forming a transistor on the semiconductor substrate through a predetermined process and then forming and planarizing an insulating film on the entire upper surface thereof; Patterning the insulating layer to expose a junction region of the transistor to form a contact hole; Depositing a conductive material having a predetermined thickness on surfaces of the contact hole and the insulating layer to form a spacer-shaped lower electrode on the sidewall of the contact hole; And forming an upper electrode by forming a dielectric film on the lower electrode and depositing a conductive material to fill the contact hole. The method of claim 1, further comprising forming a buffer layer on the insulating film. The method of claim 1, wherein the conductive material is polysilicon. The method of claim 1, wherein the dielectric film is formed of a nitride film and an oxide film. The method of claim 1, further comprising heat treatment to form the upper electrode and then activate the upper electrode. The method of claim 5, wherein the heat treatment is performed by a rapid heat treatment (RTP) method at a temperature of 700 to 900 ° C. and a nitrogen (N ₂ ) gas for 20 to 40 seconds.