KR900017148A - Manufacturing method of highly integrated trench type DRAM cell - Google Patents

Manufacturing method of highly integrated trench type DRAM cell Download PDF

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Publication number
KR900017148A
KR900017148A KR1019890005573A KR890005573A KR900017148A KR 900017148 A KR900017148 A KR 900017148A KR 1019890005573 A KR1019890005573 A KR 1019890005573A KR 890005573 A KR890005573 A KR 890005573A KR 900017148 A KR900017148 A KR 900017148A
Authority
KR
South Korea
Prior art keywords
insulating film
ion implantation
manufacturing
dram cell
trench type
Prior art date
Application number
KR1019890005573A
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Korean (ko)
Other versions
KR0139802B1 (en
Inventor
김달수
Original Assignee
이만용
금성반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이만용, 금성반도체 주식회사 filed Critical 이만용
Priority to KR1019890005573A priority Critical patent/KR0139802B1/en
Publication of KR900017148A publication Critical patent/KR900017148A/en
Application granted granted Critical
Publication of KR0139802B1 publication Critical patent/KR0139802B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

고집적 트렌치형 디램 셀의 제조방법Manufacturing method of highly integrated trench type DRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도의 (가)-(마)는 본 발명 트렌치형 디램 셀의 제조공정도.Figure 3 (a)-(e) is a manufacturing process diagram of the trench type DRAM cell of the present invention.

Claims (1)

필드산화막(1) 및 게이트(2)가 형성된 기판에 n-이온주입을 한 후 절연막(3)을 입히고, 자기정합 및 측벽공법을 이용해 비트라인 콘택트를 형성하여서는 그 비트라인 콘택트를 통해 소오스, 드레인용 n+이온주입을 함과 아울러 비트라인(4)을 적층하며, 그 위에 절연막(5)을 입힌 후 저장노드와 상기 n-이온주입된 곳을 연결할 접합부(6)를 형성하고, 그 접합부(6)를 통해 소오스-드레인용 n+이온주입을 한 다음 측벽공법을 이용해 상기 접합부(6) 내측에 절연막벽(7)을 형성하고, 트렌치에칭하여 다결정실리콘층(8)으로 저장노드를 형성해 n+가 자기도핑되게 한 다음 커패시터용 절연막(9), 플레이트용 다결정 실리콘층(10)을 적층형성함을 특징으로 하는 고집적 트렌치형 디램 셀의 제조방법.After n - ion implantation is performed on the substrate on which the field oxide film 1 and the gate 2 are formed, an insulating film 3 is applied, and a bit line contact is formed using self-alignment and sidewall method, and then a source and a drain are formed through the bit line contact. N + ion implantation and the bit line 4 are stacked, and an insulating film 5 is coated thereon, and then a junction 6 to connect the storage node and the n − ion implantation is formed, and the junction ( 6) n + ion implantation for the source-drain through the sidewall method, and then forming an insulating film wall 7 inside the junction 6 and trench etch to form a storage node with a polysilicon layer 8 n. A method for manufacturing a highly dense trench type DRAM cell, wherein + is self-doped, and then an insulating film (9) for a capacitor and a polycrystalline silicon layer (10) for a plate are formed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890005573A 1989-04-27 1989-04-27 Fabrication method of high integrated trench type dram cell KR0139802B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890005573A KR0139802B1 (en) 1989-04-27 1989-04-27 Fabrication method of high integrated trench type dram cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890005573A KR0139802B1 (en) 1989-04-27 1989-04-27 Fabrication method of high integrated trench type dram cell

Publications (2)

Publication Number Publication Date
KR900017148A true KR900017148A (en) 1990-11-15
KR0139802B1 KR0139802B1 (en) 1998-06-01

Family

ID=19285678

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890005573A KR0139802B1 (en) 1989-04-27 1989-04-27 Fabrication method of high integrated trench type dram cell

Country Status (1)

Country Link
KR (1) KR0139802B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333360B1 (en) * 1999-07-29 2002-04-18 박종섭 A method of fabricating a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333360B1 (en) * 1999-07-29 2002-04-18 박종섭 A method of fabricating a semiconductor device

Also Published As

Publication number Publication date
KR0139802B1 (en) 1998-06-01

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