KR970077741A - Thin film transistor and manufacturing method thereof - Google Patents

Thin film transistor and manufacturing method thereof Download PDF

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Publication number
KR970077741A
KR970077741A KR1019960015075A KR19960015075A KR970077741A KR 970077741 A KR970077741 A KR 970077741A KR 1019960015075 A KR1019960015075 A KR 1019960015075A KR 19960015075 A KR19960015075 A KR 19960015075A KR 970077741 A KR970077741 A KR 970077741A
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KR
South Korea
Prior art keywords
conductive layer
layer
insulating
thin film
film transistor
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KR1019960015075A
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Korean (ko)
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KR100192322B1 (en
Inventor
박진원
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문정환
Lg 반도체주식회사
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Priority to KR1019960015075A priority Critical patent/KR100192322B1/en
Publication of KR970077741A publication Critical patent/KR970077741A/en
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Publication of KR100192322B1 publication Critical patent/KR100192322B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 박막트랜지스터 및 그 제조방법에 관한 것으로, 특히 SRAM(Static Random Access Memory)에 적당하도록 한 박막트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor suitable for an SRAM (Static Random Access Memory) and a manufacturing method thereof.

이를 위한 본 발명의 박막트랜지스터 및 그 제조방법은 기판, 상기 기판상에 형성되는 제1절연막, 상기 제1절연막위에 차례로 형성되는 제1도전층, 반도체층, 제2도전층 및 제2절연막, 상기 제2절연막, 제2도전층, 반도체층 및 제1도전층에 형성되는 홀, 상기 홀 측벽 및 제2절연막상에 형성되는 제3절연막 및, 상기 홀 내부 및 제3절연막 소정영역에 형성되는 게이트 전극으로 구성된다.A thin film transistor and a method of manufacturing the same according to the present invention includes a substrate, a first insulating layer formed on the substrate, a first conductive layer sequentially formed on the first insulating layer, a semiconductor layer, a second conductive layer, A third insulating film formed on the second insulating film, the second conductive layer, the semiconductor layer, and the first conductive layer, the hole sidewall and the second insulating film, and a gate formed in the predetermined region of the hole and the third insulating film. Electrode.

Description

박막트랜지스터 및 그 제조방법Thin film transistor and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 박막트랜지스터의 단면구조도.FIG. 2 is a cross-sectional structural view of a thin film transistor according to the present invention. FIG.

Claims (7)

기판, 상기 기판상에 형성되는 제1절연막, 상기 제1절연막위에 차례로 형성되는 제1도전층, 반도체층, 제2도전층 및 제2절연막, 상기 제2절연막, 제2도전층, 반도체층 및 제1도전층에 형성되는 홀, 상기 홀 측벽 및 제2절연막상에 형성되는 제3절연막 및, 상기 홀 내부 및 제3절연막 소정영역에 형성되는 게이트 전극으로 구성됨을 특징으로 하는 박막트랜지스터.A semiconductor device comprising: a substrate; a first insulating layer formed on the substrate; a first conductive layer sequentially formed on the first insulating layer; a semiconductor layer; a second conductive layer; a second insulating layer; A third insulating layer formed on the first insulating layer, a hole formed in the first insulating layer, a third insulating layer formed on the hole sidewall and the second insulating layer, and a gate electrode formed in the hole and a predetermined region of the third insulating layer. 제1항에 있어서, 제1도전층은 불순물을 함유한 폴리실리콘으로 형성됨을 특징으로 하는 박막트랜지스터.The thin film transistor according to claim 1, wherein the first conductive layer is formed of polysilicon containing an impurity. 제1항에 있어서, 제1도전층과 제2도전층은 동일 불순물을 함유함을 특징으로 하는 박막트랜지스터.The thin film transistor according to claim 1, wherein the first conductive layer and the second conductive layer contain the same impurity. 기판상에 제1절연막, 제1도전층, 반도체층, 제2절연막을 차례로 형성하는 공정과, 상기 반도체층상의 상측부위에 불순물 이온을 주입하여 제2도전층을 형성하는 공정과, 상기 제2절연막, 제2도전층, 반도체층 및 제1도전층을 식각하여 홀을 형성하는 공정과, 상기 홀 내부 및 제2절연막상에 제3절연막을 형성하는 공정과, 상기 홀내에 게이트 전극을 형성하는 공정을 포함하는 것을 특징으로 하는 박막트랜지스터의 제조방법.A step of forming a first insulating film, a first conductive layer, a semiconductor layer and a second insulating film on a substrate in this order; a step of forming a second conductive layer by implanting impurity ions into an upper portion of the semiconductor layer; A step of forming a hole by etching the insulating film, the second conductive layer, the semiconductor layer, and the first conductive layer; a step of forming a third insulating film on the inside of the hole and on the second insulating film; Wherein the thin film transistor is formed on the substrate. 제4항에 있어서, 제1도전층은 불순물을 함유한 폴리실리콘으로 형성함을 특징으로 하는 박막트랜지스터의 제조방법.5. The method of claim 4, wherein the first conductive layer is formed of polysilicon containing impurities. 제4항에 있어서, 제1도전층과 제2도전층은 동일 불순물을 함유함을 특징으로 하는 박막트랜지스터의 제조방법.The method according to claim 4, wherein the first conductive layer and the second conductive layer contain the same impurity. 제4항에 있어서, 제2도전층을 이온주입에 의해 형성하는 대신에 제1도전층과 동일 불순물을 함유한 폴리실리콘을 증착하여 형성함을 특징으로 하는 박막트랜지스터의 제조방법.The method according to claim 4, wherein the second conductive layer is formed by depositing polysilicon containing the same impurity as the first conductive layer, instead of forming the second conductive layer by ion implantation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960015075A 1996-05-08 1996-05-08 Fabrication method of thin film transistor KR100192322B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960015075A KR100192322B1 (en) 1996-05-08 1996-05-08 Fabrication method of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960015075A KR100192322B1 (en) 1996-05-08 1996-05-08 Fabrication method of thin film transistor

Publications (2)

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KR970077741A true KR970077741A (en) 1997-12-12
KR100192322B1 KR100192322B1 (en) 1999-07-01

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