KR950004548A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR950004548A
KR950004548A KR1019930013809A KR930013809A KR950004548A KR 950004548 A KR950004548 A KR 950004548A KR 1019930013809 A KR1019930013809 A KR 1019930013809A KR 930013809 A KR930013809 A KR 930013809A KR 950004548 A KR950004548 A KR 950004548A
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KR
South Korea
Prior art keywords
silicon layer
polycrystalline silicon
oxide film
semiconductor device
forming
Prior art date
Application number
KR1019930013809A
Other languages
Korean (ko)
Other versions
KR100268776B1 (en
Inventor
이희승
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930013809A priority Critical patent/KR100268776B1/en
Publication of KR950004548A publication Critical patent/KR950004548A/en
Application granted granted Critical
Publication of KR100268776B1 publication Critical patent/KR100268776B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로 특히, 폴리사이드 구조를 MOS트랜지스터의 게이트전극과 아날로그 회로용 캐패시터 전극에 적용하되, 캐패시터 유전체막의 특성을 향상시키기 위한 반도체소자 제조방법에 관한 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for applying a polyside structure to a gate electrode and an analog circuit capacitor electrode of a MOS transistor, thereby improving characteristics of a capacitor dielectric film.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도 내지 제 4 도는 본 발명에 의한 MOS트랜지스터의 게이트전극과 아날로그 회로용 캐패시터를 제조한 단면도.2 to 4 are cross-sectional views of manufacturing a gate electrode and an analog circuit capacitor of the MOS transistor according to the present invention.

Claims (2)

반도체소자 제조방법에 있어서, 반도체기판의 예정된 부분에 필드산화막을 형성한 다음, 노출된 기판 표면에 게이트산화막을 형성하는 공정과, 게이트산화막과 필드산화막 상부에 도프된 제 1 다결정 실리콘층, 금속 실리사이드층, 도프된 제 2 다결정 실리콘층, 유전체막, 도프된 제 3 다결정 실리콘층을 순차적으로 적층하는 공장과, 아날로그 회로용 캐패시터 마스크를 이용한 식각공정으로 상기 제 3 다결정 실리콘층, 유전체막 제 2 다결정 실리콘층을 순차적으로 식각하여 캐패시터 패턴을 형성하는 공정과, 게이트 마스크를 이용한 식각공정으로 금속 실리사이드층, 제 1 다결정 실리콘층을 식각하여 MOS트랜지스터 지역에 제 1 다결정 실리콘층과 금속 실리사이드로된 폴리사이드 구조의 게이트전극을 형성하는 동시에 캐패시터 지역에 제1다결정 실리콘층과, 금속 실리사이드층으로 이루어진 폴리사이드 패턴을 형성하는 공정을 포함하는 반도체소자 제조방법.A method of manufacturing a semiconductor device, comprising: forming a field oxide film on a predetermined portion of a semiconductor substrate, and then forming a gate oxide film on an exposed substrate surface, a first polycrystalline silicon layer and a metal silicide doped on the gate oxide film and the field oxide film A layer, a doped second polycrystalline silicon layer, a dielectric film, and a doped third polycrystalline silicon layer sequentially stacked, and the third polycrystalline silicon layer and the dielectric film second polycrystalline by an etching process using a capacitor mask for an analog circuit. The silicon layer is sequentially etched to form a capacitor pattern, and the metal silicide layer and the first polycrystalline silicon layer are etched by an etching process using a gate mask to form a polyside comprising a first polycrystalline silicon layer and a metal silicide in the MOS transistor region. A first polycrystal in the capacitor region while forming a gate electrode of the structure Method of manufacturing a semiconductor device including a step of forming a polycide pattern consisting of a silicon layer, a metal silicide layer. 제 1 항에 있어서, 상기 유전체막은 화학증착법으로 형성한 산화막인 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the dielectric film is an oxide film formed by chemical vapor deposition. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930013809A 1993-07-21 1993-07-21 A manufacturing method of semiconductor device KR100268776B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930013809A KR100268776B1 (en) 1993-07-21 1993-07-21 A manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930013809A KR100268776B1 (en) 1993-07-21 1993-07-21 A manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950004548A true KR950004548A (en) 1995-02-18
KR100268776B1 KR100268776B1 (en) 2000-10-16

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Application Number Title Priority Date Filing Date
KR1019930013809A KR100268776B1 (en) 1993-07-21 1993-07-21 A manufacturing method of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328451B1 (en) * 1995-10-13 2002-08-08 주식회사 하이닉스반도체 Method for manufacturing capacitor in semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102152256B1 (en) 2014-02-11 2020-09-04 에스케이하이닉스 주식회사 Dc-dc converter and method of manufacturing dc-dc converter

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156563A (en) * 1988-12-08 1990-06-15 Fuji Electric Co Ltd Semiconductor integrated circuit
JP2616519B2 (en) * 1991-08-28 1997-06-04 富士通株式会社 Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328451B1 (en) * 1995-10-13 2002-08-08 주식회사 하이닉스반도체 Method for manufacturing capacitor in semiconductor device

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Publication number Publication date
KR100268776B1 (en) 2000-10-16

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