KR940004823A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940004823A
KR940004823A KR1019920015187A KR920015187A KR940004823A KR 940004823 A KR940004823 A KR 940004823A KR 1019920015187 A KR1019920015187 A KR 1019920015187A KR 920015187 A KR920015187 A KR 920015187A KR 940004823 A KR940004823 A KR 940004823A
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KR
South Korea
Prior art keywords
insulating layer
contact hole
etching
film
polysilicon film
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KR1019920015187A
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Korean (ko)
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KR960003772B1 (en
Inventor
김대영
김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019920015187A priority Critical patent/KR960003772B1/en
Publication of KR940004823A publication Critical patent/KR940004823A/en
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Publication of KR960003772B1 publication Critical patent/KR960003772B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 소자의 캐패시터 제조방법에 관한 것으로, 반도체 기판(1)에 소자 분리 절연막(2)을 형성하고 게이트 산화막(4)과 게이트 전극(5)을 소정의 크기로 형성한 다음에 소오스(3) 및 드레인(3')을 형성하고 제1절연층(6)을 증착하는 제1단계, 상기 제1단계 후에 제1폴리실리콘막(7)과 제2절연층(8)을 차례로 증착하여 전하보존전극용 콘택홀(13)을 마스크 패턴하여 상기 제2절연층(8)을 상기 콘택홀(13)크기로 식각하는 제2단계, 상기 제2단계후에 상기 제1폴리실리콘막(7)을 상기 콘택홀(13)의 크기 보다 넓은 폭으로 식각하고 상기 제1절연층(6)을 상기 콘택홀(13)의 크기와 같은 폭으로 식각하는 제3단계, 상기 제3단계 후에 제2폴리실리콘막(9)을 증착하여 전하보전전극(10)형성을 위해 소정의 크기로 상기 제2폴리실리콘막(9)을 선택 식각하고 상기 제2절연층(8)과 상기 잔류된 제1폴리실리콘막(9)을 모두 식각하는 제4단계, 및 상기 제4단계 후에 유전막(11)과 플레이트전극(12)을 차례로 상기 전하보전전극(10)에 증착하는 제5단계로 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법에 관한 것이다.A method for manufacturing a capacitor of a semiconductor device, comprising: forming a device isolation insulating film (2) on a semiconductor substrate (1), forming a gate oxide film (4) and a gate electrode (5) to a predetermined size, and then source (3) and A first step of forming a drain 3 ′ and depositing the first insulating layer 6, and after the first step, the first polysilicon film 7 and the second insulating layer 8 are sequentially deposited to form a charge storage electrode. A second pattern of etching the second insulating layer 8 to the size of the contact hole 13 by masking the contact hole 13 for the contact hole 13, and after the second step, the first polysilicon film 7 is contacted with the contact hole 13. A third step of etching the first insulating layer 6 to the same width as the size of the contact hole 13 and the second polysilicon layer after the third step 9) the second polysilicon film 9 is selectively etched to a predetermined size to form the charge preserving electrode 10 by depositing the same with the second insulating layer 8. A fourth step of etching all of the remaining first polysilicon film 9 and a fifth step of depositing the dielectric film 11 and the plate electrode 12 on the charge preserving electrode 10 after the fourth step. The present invention relates to a method for manufacturing a capacitor of a semiconductor device.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 일실시예의 제조 공정도.1 is a manufacturing process diagram of an embodiment according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 소자 분리 절연막1 semiconductor substrate 2 device isolation insulating film

3 : 소오스 3' : 드레인3: source 3 ': drain

4 : 게이트 실리콘 5 : 게이트 전극4 gate silicon 5 gate electrode

6,8 : 절연층 7,9 : 폴리실리콘막6,8 insulation layer 7,9 polysilicon film

10 : 전하보존전극 11 : 유전막10 charge storage electrode 11 dielectric film

12 : 플레이크 전극 13 : 콘택홀12 flake electrode 13 contact hole

Claims (2)

반도체 소자의 캐패시터 제조방법에 있어서, 반도체 기판(1)에 소자 분리 절연막(2)을 형성하고 게이트 산화막(4)과 게이트 전극(5)을 소정의 크기로 형성한 다음에 소오스(3) 및 드레인(3')을 형성하고 제 1 절연층(6)을 증착하는 제 1 단계, 상기 제 1 단계후에 제 1 폴리실리콘막(7)과 제 2 절연층(8)을 차례로 증착하여 전하보존전극용 콘택홀(13)을 마스크 패턴하여 상기 제 2 절연층(8)을 상기 콘택홀(13) 크기로 식각하는 제 2 단계, 상기 제 2 단계후에 상기 제 1 폴리실리콘막(7)을 상기 콘택홀(13)의 크기 보다 넓은 폭으로 식각하고 상기 제 1 절연층(6)을 상기 콘택홀(13)의 크기와 같은 폭으로 식각하는 제 3 단계, 상기 제 3 단계후에 제 2 폴리실리콘막(9)을 증착하여 전하보존전극(10) 형성을 위해 소정의 크기로 상기 제 2 폴리실리콘막(9)을 선택 식각하고 상기 제 2 절연층(8)과 상기 잔류된 제 1 폴리실리콘막(9)을 모두 식각하는 제 4 단게, 및 상기 제 4 단계후에 유전막(11)과 플레이트전극(12)을 차례로 상기 전하보존적극(10)에 증착하는 제 5 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.In the method of manufacturing a capacitor of a semiconductor device, an element isolation insulating film 2 is formed on a semiconductor substrate 1, the gate oxide film 4 and the gate electrode 5 are formed to a predetermined size, and then the source 3 and the drain are formed. A first polysilicon film 7 and a second insulating layer 8 are sequentially deposited after the first step of forming a 3 'and depositing the first insulating layer 6; A second step of etching the second insulating layer 8 to the size of the contact hole 13 by masking the contact hole 13, and after the second step, the first polysilicon layer 7 is formed into the contact hole. A third step of etching the first insulating layer 6 to the same width as that of the contact hole 13 and the second polysilicon film 9 after the third step. Evaporate the second polysilicon layer 9 to a predetermined size to form the charge preservation electrode 10 by A fourth step of etching both the insulating layer 8 and the remaining first polysilicon film 9, and after the fourth step, the dielectric film 11 and the plate electrode 12 are sequentially in the charge storage active 10 And a fifth step of depositing the same). 제 1 항에 있어서, 상기 제 2 단계의 제 2 절연층(8)과 상기 제 3 단계의 제 1 절연층(6)의 비등방성 식각을 하고 상기 제 3 단계의 제 1 폴리실리콘막(7) 식각은 SF6가스를 이용한 등방성 식각으로 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein anisotropic etching of the second insulating layer (8) of the second step and the first insulating layer (6) of the third step is performed, and the first polysilicon film (7) of the third step is performed. Etching is an isotropic etching method using a SF 6 gas capacitor manufacturing method of a semiconductor device, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920015187A 1992-08-24 1992-08-24 Capacitor manufacture of semiconductor device KR960003772B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015187A KR960003772B1 (en) 1992-08-24 1992-08-24 Capacitor manufacture of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019920015187A KR960003772B1 (en) 1992-08-24 1992-08-24 Capacitor manufacture of semiconductor device

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KR940004823A true KR940004823A (en) 1994-03-16
KR960003772B1 KR960003772B1 (en) 1996-03-22

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100277875B1 (en) * 1997-12-30 2001-02-01 김영환 Capacitor Manufacturing Method
KR20210082235A (en) * 2018-10-31 2021-07-02 제이엑스금속주식회사 Raw material supply device, electronic/electric device component scrap processing device, and electronic/electric device component scrap treatment method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100277875B1 (en) * 1997-12-30 2001-02-01 김영환 Capacitor Manufacturing Method
KR20210082235A (en) * 2018-10-31 2021-07-02 제이엑스금속주식회사 Raw material supply device, electronic/electric device component scrap processing device, and electronic/electric device component scrap treatment method

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Publication number Publication date
KR960003772B1 (en) 1996-03-22

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