KR100328451B1 - Method for manufacturing capacitor in semiconductor device - Google Patents
Method for manufacturing capacitor in semiconductor device Download PDFInfo
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- KR100328451B1 KR100328451B1 KR1019950035266A KR19950035266A KR100328451B1 KR 100328451 B1 KR100328451 B1 KR 100328451B1 KR 1019950035266 A KR1019950035266 A KR 1019950035266A KR 19950035266 A KR19950035266 A KR 19950035266A KR 100328451 B1 KR100328451 B1 KR 100328451B1
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- polysilicon layer
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- semiconductor device
- capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 67
- 239000011229 interlayer Substances 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 하부 전극을 폴리실리콘 및 텅스텐 실리사이드(WSix)층의 적층 구조로 형성하고, 상부 전극을 금속층으로 형성하는 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device, wherein the lower electrode is formed of a laminated structure of polysilicon and tungsten silicide (WSix) layers and the upper electrode is formed of a metal layer.
일반적으로 반도체 소자는 논리 회로를 구성하기 위한 디지탈 소자와 주변회로를 구성하기 위한 아날로그 소자로 이루어진다. 디지탈 소자로는 트랜지스터를 사용하며, 아날로그 소자로는 캐패시터, 저항, 다이오드등이 사용된다. 이중 아날로그 회로를 구성하는 소자중의 하나인 캐패시터는 일반적으로 다음과 같은 3가지 형태로 구성된다.In general, a semiconductor device is composed of a digital device for configuring a logic circuit and an analog device for configuring a peripheral circuit. Transistors are used as digital devices, and capacitors, resistors, and diodes are used as analog devices. One of the components constituting the dual analog circuit, the capacitor is generally composed of the following three types.
첫 번째 형태의 캐패시터는 상부 및 하부 전극이 폴리실리콘층 및 실리콘층으로 이루어진 형태의 캐패시터이다. 이러한 형태의 캐패시터는 게이트 산화막을 유전체막으로 사용하므로 산화막의 질이 우수하여 누설 전류는 작으나 실리콘층에서 공핍 현상이 발생하여 전압 계수(Voltage Coefficient)가 커지는 단점이 있다.The first type of capacitor is a type of capacitor in which the upper and lower electrodes are made of a polysilicon layer and a silicon layer. Since this type of capacitor uses a gate oxide film as a dielectric film, the oxide film is excellent in quality and thus has a small leakage current, but a depletion phenomenon occurs in the silicon layer, resulting in a large voltage coefficient.
두 번째 형태의 캐패시터는 상부 및 하부 전극이 제 1 폴리실리콘층 및 제 2 폴리실리콘층으로 이루어진 형태의 캐패시터이다. 이러한 형태의 캐패시터는 상기 첫 번째 형태의 캐패시터에 비해 낮은 전압 계수를 가지나 폴리실리콘과 산화막계면의 거칠음에 의해 누설 전류가 크다는 단점이 있다.The second type of capacitor is a type of capacitor in which the upper and lower electrodes are composed of a first polysilicon layer and a second polysilicon layer. This type of capacitor has a lower voltage coefficient than the capacitor of the first type, but has a disadvantage in that the leakage current is large due to roughness of the polysilicon and the oxide film interface.
세 번째 형태의 캐패시터는 상부 및 하부 전극이 제 1 금속층 및 제 2 금속층으로 이루어진 형태의 캐패시터이다. 이러한 형태의 캐패시터는 전압 계수도 우수하고 누설 전류도 작지만, 하부 금속을 알루미늄으로 사용하기 때문에 이후의 공정에서 고온 처리가 불가능하다는 단점이 있다.The third type of capacitor is a capacitor in which the upper and lower electrodes are composed of a first metal layer and a second metal layer. This type of capacitor has a good voltage coefficient and a small leakage current. However, since the lower metal is used as aluminum, there is a disadvantage that high temperature processing is not possible in a subsequent process.
따라서, 본 발명은 하부 및 상부 전극을 텅스텐 실리사이드(Wsix)층 및 금속층으로 형성함으로써 상기한 단점을 해소 할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of solving the above-mentioned disadvantages by forming the lower and upper electrodes as a tungsten silicide (Wsix) layer and a metal layer.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판 상부의 소정 영역에 제 1 폴리실리콘층을 형성하는 단계와, 상기 제 1 폴리실리콘층 상부에 제 2 폴리실리콘층 및 텅스텐 실리사이드층을 형성하는 단계와, 상기 텅스텐 실리사이드층 및 제 2 폴리실리콘층을 패터닝하여 하부 전극을 형성하는 단계와, 상기 텅스텐 실리사이드층 상부에 유전체막 및 금속층을 형성하여 상부 전극을 형성하는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a first polysilicon layer on a predetermined region on the silicon substrate, forming a second polysilicon layer and tungsten silicide layer on the first polysilicon layer; And forming a lower electrode by patterning the tungsten silicide layer and the second polysilicon layer, and forming an upper electrode by forming a dielectric layer and a metal layer on the tungsten silicide layer.
본 발명에 의하면 금속-실리사이드 캐패시터의 계면 우수성과 전압에 따른 캐패시턴스의 선형성에 의하여 낮은 누설 전류와 낮은 전압 계수를 얻을 수 있다.According to the present invention, a low leakage current and a low voltage coefficient can be obtained by the interfacial excellence of the metal-silicide capacitor and the linearity of the capacitance according to the voltage.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1A 내지 제 1E 도는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이고, 제 2 도는 본 발명에 따른 캐패시터의 평면도이다. 참고로 도면에서 동일 부호는 동일한 영역을 나타낸다.1A to 1E are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention, and FIG. 2 is a plan view of a capacitor according to the present invention. For reference, the same reference numerals in the drawings represent the same area.
제 1A 도와 관련하여, 필드 산화막(2)이 형성되어 액티브 영역 및 필드 영역이 확정된 실리콘 기판(1) 상부에 제 1 폴리실리콘층(3)을 4000Å 이상의 두께로 형성한다. 캐패시터의 하부 전극용 마스크를 이용한 사진 및 식각 공정에 의해 제 1 폴리실리콘층(3)을 패터닝하여 필드 산화막(2) 상부의 소정 영역에 제 1 폴리실리콘층(3)이 잔류되도록 한다.In relation to the first A diagram, a field oxide film 2 is formed to form a first polysilicon layer 3 with a thickness of 4000 kPa or more on top of the silicon substrate 1 where the active region and the field region are defined. The first polysilicon layer 3 is patterned by a photolithography and an etching process using a mask for a lower electrode of the capacitor so that the first polysilicon layer 3 remains in a predetermined region above the field oxide film 2.
제 1B 도와 관련하여, 전체 구조 상부에 게이트 산화막(4)을 증착하고, 제 1 폴리실리콘층(3)을 패터닝하기 위한 마스크와 반대의 형상을 갖는 마스크를 이용한 사진 및 식각 공정내 의해 제 1 폴리실리콘층(3) 상부에 증착된 게이트 산화막(4)을 제거한다. 상기 식각 공정시 필드 산화막(2) 상부에 형성된 제 1 폴리실리콘층(3)을 보호하기 위해 HF를 이용한 습식 식각을 실시한다. 게이트 산화막(4) 및 제 1 폴리실리콘층(3)이 잔류하는 실리콘 기판(1) 상부에 제 2 폴리실리콘층(5) 및 텅스텐 실리사이드(WSix)층(6)을 순차적으로 형성한다. 그리고, 소정의 마스크를 이용한 사진 및 식각 공정을 실시하여 텅스텐 실리사이드층(6), 제 2 폴리실리콘층(5) 및 게이트 산화막(4)을 패터닝한다. 이에 의해 실리콘 기판(1)의 액티브 영역상에는 게이트 전극(12)이 형성되고, 필드 영역상에는 캐패시터의 하부전극(13)이 형성된다. 상기 제 1 폴리실리콘층(3)의 패턴 폭은 하부전극(13)의 패턴 폭보다 넓게 형성된다.Regarding the 1B diagram, the first poly is deposited by photo gate and etching process using a mask having a shape opposite to that for depositing a gate oxide film 4 over the entire structure and patterning the first polysilicon layer 3. The gate oxide film 4 deposited on the silicon layer 3 is removed. In the etching process, wet etching using HF is performed to protect the first polysilicon layer 3 formed on the field oxide layer 2. A second polysilicon layer 5 and a tungsten silicide (WSix) layer 6 are sequentially formed on the silicon substrate 1 on which the gate oxide film 4 and the first polysilicon layer 3 remain. The tungsten silicide layer 6, the second polysilicon layer 5, and the gate oxide film 4 are patterned by performing a photolithography and an etching process using a predetermined mask. As a result, the gate electrode 12 is formed on the active region of the silicon substrate 1, and the lower electrode 13 of the capacitor is formed on the field region. The pattern width of the first polysilicon layer 3 is wider than the pattern width of the lower electrode 13.
제 1C 도와 관련하여, 전체 구조 상부에 산화막을 증착한 후 전면 식각 공정을 실시한다. 이에 의해 게이트 전극(12) 측벽과 하부 전극(13) 측벽에 산화막스페이서(7)가 형성된다. 아울러, 제 1 폴리실리콘층(3) 측벽에도 산화막 스페이서(3)가 형성된다.In connection with the first C diagram, an oxide film is deposited on the entire structure, followed by a front surface etching process. As a result, an oxide film spacer 7 is formed on the sidewall of the gate electrode 12 and the sidewall of the lower electrode 13. In addition, the oxide film spacers 3 are formed on the sidewalls of the first polysilicon layer 3.
제 1D 도와 관련하여, 전체 구조 상부에 상부에 TEOS막(8) 및 BPSG막(9)을 형성하여 층간 절연막을 형성한다. 그후 CMP(Chemical Mechnical Polishing) 공정을 실시하여 층간 절연막을 연마한다. 이때, 필드 산화막(2) 상부에 형성된 제 1 폴리실리콘층(3)의 두께와 필드 산화막(2)의 두께에 의하여 필드 영역은 액티브 영역 보다 약 6000Å 이상 높기 때문에 CMP 공정을 잘 조절하여 하부 전극(13)의 텅스텐 실리사이드층(6) 상부가 노출되도록 CMP 공정을 실시하는 것이 바람직하다.In relation to the 1D diagram, a TEOS film 8 and a BPSG film 9 are formed on the entire structure, thereby forming an interlayer insulating film. Thereafter, a chemical mechanical polishing (CMP) process is performed to polish the interlayer insulating film. At this time, since the field region is about 6000 GHz or more higher than the active region by the thickness of the first polysilicon layer 3 formed on the field oxide film 2 and the thickness of the field oxide film 2, the lower electrode ( It is preferable to perform the CMP process so that the upper portion of the tungsten silicide layer 6 in 13) is exposed.
제 1E 도와 관련하여, 전체 구조 상부에 캐패시터의 유전체막(10)을 형성한 후 유전체막(10) 상부에 금속층을 형성한 후 패터닝하여 금속으로 이루어진 캐패시터의 상부 전극(11)을 형성한다. 이후, 제 2 도에 도시된 바와 같이 콘택(15)을 이용하여 메탈라인(14)을 형성한다.In relation to the first E diagram, the dielectric film 10 of the capacitor is formed over the entire structure, and then a metal layer is formed over the dielectric film 10 to be patterned to form the upper electrode 11 of the capacitor made of metal. Thereafter, as shown in FIG. 2, the metal line 14 is formed using the contact 15.
상술한 바와 같이 본 발명에 의하면 제 1 폴리실리콘층, 제 2 폴리실리콘층 및 텅스텐 실리사이드층으로 형성된 하부 전극과 금속층으로 형성된 상부 전극으로 이루어진 캐패시터를 제조함으로써 소자의 누설 전류를 줄일 수 있고, 전압계수를 줄일 수 있어 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, by manufacturing a capacitor including a lower electrode formed of a first polysilicon layer, a second polysilicon layer, and a tungsten silicide layer and an upper electrode formed of a metal layer, the leakage current of the device can be reduced, and the voltage coefficient Can be reduced, thereby improving the reliability of the device.
제 1A 내지 제 1E 도는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1A to 1E are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
제 2 도는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 캐패시터의 평면도.2 is a plan view of a capacitor for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 제 1 폴리실리콘층 4 : 게이트 산화막3: first polysilicon layer 4: gate oxide film
5 : 제 2 폴리실리콘층 6 : 텅스텐 실리사이드층5: second polysilicon layer 6: tungsten silicide layer
7 : 스페이서 8 : TEOS막7 spacer 8 TEOS film
9 : BPSG막 10 : 유전체막9: BPSG film 10: dielectric film
11 : 상부 전극 12 : 게이트 전극11 upper electrode 12 gate electrode
13 : 하부 전극 14 : 메탈 라인13: lower electrode 14: metal line
15 : 콘택15: Contact
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950035266A KR100328451B1 (en) | 1995-10-13 | 1995-10-13 | Method for manufacturing capacitor in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950035266A KR100328451B1 (en) | 1995-10-13 | 1995-10-13 | Method for manufacturing capacitor in semiconductor device |
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| KR970024141A KR970024141A (en) | 1997-05-30 |
| KR100328451B1 true KR100328451B1 (en) | 2002-08-08 |
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| KR20020030420A (en) * | 2000-10-17 | 2002-04-25 | 박종섭 | Semiconductor Device and Method for Fabricating the Same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920018939A (en) * | 1991-03-06 | 1992-10-22 | 가나이 쓰토무 | Manufacturing Method of Semiconductor Device |
| JPH0621379A (en) * | 1992-07-06 | 1994-01-28 | Matsushita Electron Corp | Semiconductor memory and manufacture thereof |
| KR940016804A (en) * | 1992-12-31 | 1994-07-25 | 김주용 | Capacitor Formation Method of Semiconductor Device |
| KR950004548A (en) * | 1993-07-21 | 1995-02-18 | 김주용 | Semiconductor device manufacturing method |
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1995
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920018939A (en) * | 1991-03-06 | 1992-10-22 | 가나이 쓰토무 | Manufacturing Method of Semiconductor Device |
| JPH0621379A (en) * | 1992-07-06 | 1994-01-28 | Matsushita Electron Corp | Semiconductor memory and manufacture thereof |
| KR940016804A (en) * | 1992-12-31 | 1994-07-25 | 김주용 | Capacitor Formation Method of Semiconductor Device |
| KR950004548A (en) * | 1993-07-21 | 1995-02-18 | 김주용 | Semiconductor device manufacturing method |
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| KR970024141A (en) | 1997-05-30 |
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