KR100304948B1 - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PURPOSE: A fabrication method of DRAM(Dynamic Random Access Memory) is provided to improve a capacitance by forming dual storage nodes. CONSTITUTION: A planarized layer, an etch stopper(5) and a first conductive layer(13) are sequentially formed on a semiconductor substrate having transistors. A storage node contact is formed by selectively etching the first conductive layer(13), the etch stopper and the planarized layer. After forming a second conductive layer(14) on the resultant structure, a storage node pattern is formed by selectively etching the second and first conductive layers(14,13), wherein the edge portions of the storage node pattern is sloped. Dual storage nodes having an inner pillar(A) and an outer pillar(B) are formed. Then, a dielectric film(16) and a plate electrode(17) are sequentially formed on the dual storage nodes.

Description

Manufacturing Method of Semiconductor Memory Device

1 is a process flowchart showing a conventional method of manufacturing a semiconductor memory device.

2 is a process flowchart showing a method of manufacturing a semiconductor memory device of the present invention.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate 2: gate insulating film

3: gate electrode S / D: source and drain regions

4: planarization layer 5: etch stop layer

6: Storage node contact 9: Isolation area between storage nodes

13: first conductive layer 14: second conductive layer

15 CVD oxide film 16 capacitor dielectric film

17: capacitor plate electrode

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device having a dual capacitor storage node.

Referring to FIG. 1, a conventional method of manufacturing a dynamic random access memory (DRAM) is as follows.

First, as shown in FIG. 1A, a cell transistor including a gate insulating film 2, a gate electrode 3, a source and a drain region S / D is formed on a semiconductor substrate 1, and then As a result, a CVD (Chemical Vapor Deposition) oxide film is formed as the planarization layer 4 on the entire surface, and the nitride film 5 is formed thereon.

Subsequently, as shown in FIG. 1 (b), the nitride film 5 and the planarization layer 4 are selectively etched to form a storage node contact 6 exposing the source or drain region of the cell transistor. As the first conductive layer 7 for forming a storage node on the nitride film 5 and in the storage node contact, a polysilicon layer is formed.

Next, as shown in FIG. 1 (c), an oxide film 8 is formed on the entire surface of the resultant and then patterned into a storage node pattern by a photolithography process to form the storage node forming region and the storage node isolation region 9. Next, the polysilicon layer 7 is etched using the oxide film 8 as a mask.

Subsequently, as shown in FIG. 1 (d), as a second conductive layer for forming a storage node on the entire surface of the resultant, a polysilicon layer is formed, and then etched back to form a conductive layer sidewall on the sidewall of the oxide film 8. 10) and then the oxide film is removed by wet etching to form a capacitor storage node including the first conductive layer 7 and the second conductive layer side wall 10. Subsequently, the capacitor dielectric layer 11 is formed on the entire surface of the storage node, and the capacitor plate electrode 12 is formed on the entire surface of the capacitor dielectric layer 11 to complete the capacitor.

The prior art is limited in increasing capacitor capacity. In other words, as the size of the DRAM cell decreases, the area occupied by the cell capacitors also decreases in proportion to the size of the DRAM cell. Thus, in order for a memory cell operation to be performed, sufficient capacitor capacity must be obtained even in a small area. There is a limit to increasing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a method of manufacturing a semiconductor memory device that is suitable for obtaining sufficient capacitor capacity even in a small area.

A semiconductor memory device manufacturing method of the present invention for achieving the above object comprises the steps of forming a transistor comprising a gate insulating film (2), a gate electrode (3), a source and a drain region (S / D) on a semiconductor substrate; A process of forming a puncturing layer (4), an etch stop layer (5), and a first conductive layer (13) in order on the entire surface of the resultant formed transistor, the first conductive layer (13) and the etch stop layer (5) and planarization Selectively etching the layer 4 to form a storage node contact 6 having an inclined portion 13A thereon, forming a second conductive layer 14 on the entire surface of the resultant, the second conductive layer Selectively etching the 14 and first conductive layers 13 to form a storage node pattern having an inclined edge region, and defining an isolation region 9 between storage nodes, between the storage node contacts and the storage nodes. Embedding the isolation region with an insulating film; Selectively etching the second conductive layer 14 and the first conductive layer 13 so that the first conductive layer remains a predetermined thickness to form a capacitor storage node having an inner pillar A and an outer pillar B; Removing the insulating film 15, forming a capacitor dielectric film 16 on the entire surface of the capacitor storage node, and forming a capacitor plate electrode 17 over the capacitor dielectric film 16. It features.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 shows a method of manufacturing a semiconductor memory device according to the present invention according to the process sequence.

First, as illustrated in FIG. 2A, a cell transistor including a gate insulating film 2, a gate electrode 3, a source, and a drain region S / D is formed on the semiconductor substrate 1. As a result, a CVD (Chemical Vapor Deposition) oxide film is formed as the planarization layer 4 on the entire surface, and the nitride film 5 is formed as an etch stop layer thereon. Subsequently, as the first conductive layer 13 for forming a capacitor storage node on the nitride film 5, a polysilicon layer is formed to a thickness of 5000 kPa.

Next, as shown in FIG. 2 (b), the first conductive layer 1 (4), the nitride film 5, and the planarization layer 4 are selectively etched to expose the source or drain region of the cell transistor. The node contact 6 is formed. First, the inclined portion 13A is formed on the first conductive layer 13 by wet etching, and then the remaining portion of the first conductive layer 13 through dry etching. And forming the storage node contact 6 by etching the nitride film 5 and the planarization layer 4. Subsequently, a polysilicon layer is formed as a second conductive layer 14 for forming a storage node on the entire surface of the resultant.

Next, as shown in FIG. 2 (c), the second conductive layer 14 and the first conductive layer 13 are selectively etched by a photolithography process to form a capacitor storage node pattern and at the same time a storage node. Liver isolation area 9 is defined. At this time, the second conductive layer 14 and the upper portion of the first conductive layer 13 are first etched by wet etching to form the inclined region 9A on the edge portion of the storage node pattern, and then the first by dry etching. By etching the rest of the conductive layer, an isolation region 9 between storage nodes is formed. Subsequently, after the CVD oxide film 15 is formed on the entire surface of the resultant material, the CVD oxide film 15 is etched back to bury the storage node contact region 6 and the isolation region 9 between the storage nodes with the oxide film 15.

Subsequently, as illustrated in FIG. 2D, the second conductive layer 14 and the first conductive layer 13 are selectively etched by dry etching. In this case, the first conductive layer of the storage node forming region ( The etching is carried out so that the thickness of 13) remains by X. Subsequently, the remaining CVD oxide film 15 is removed by wet etching, thereby completing a storage node including an internal storage node pillar A and an external storage node pillar B. Here, the thickness of the internal storage node pillar A is equal to the width of the inclined portion 13A on the upper portion of the storage node contact, and the thickness of the external storage node pillar B is the inclined region 9A of the edge portion of the storage node pattern. Is equal to the width of. Subsequently, the capacitor dielectric layer 16 is formed on the entire surface of the storage node, and the capacitor plate electrode 17 is formed on the entire surface of the capacitor dielectric layer 16 to complete the capacitor.

As described above, the structure of the storage node of the present invention is increased by the area of the inner storage node pillar since the structure of the storage node of the present invention is composed of the double pillar of the inner pillar and the outer pillar, whereas the conventional capacitor storage node structure is formed of only the outer storage node pillar. As a result, the cell capacitor capacity value is increased. Therefore, when the capacitor structure of the present invention is applied to a semiconductor memory device, high integration can be achieved.

Claims (4)

Forming a transistor comprising a gate insulating film (2), a gate electrode (3), a source and a drain region (S / D) on a semiconductor substrate, and a planarization layer (4) and an etch stop layer on the entire surface of the resultant transistor. (5), a step of sequentially forming the first conductive layer 13, and selectively etching the first conductive layer 13, the etch stop layer 5, and the planarization layer 4 to incline the upper portion 13A. Forming a storage node contact 6 having a structure; forming a second conductive layer 14 on the entire surface of the resultant; selectively etching the second conductive layer 14 and the first conductive layer 13 Forming a storage node pattern having an inclined edge region and defining an isolation region 9 between storage nodes; and buried the isolation region between the storage node contact and the storage node with an insulating film 15; The second conductive layer 14 and the first conductive layer 13 are formed so that the layer 13 remains constant. Selectively etching to form a capacitor storage node having an inner pillar A and an outer pillar B, removing the insulating layer 15, and forming a capacitor dielectric layer 16 on the entire surface of the capacitor storage node. And forming a capacitor plate electrode (17) over the capacitor dielectric film (16). The method of manufacturing a semiconductor memory device according to claim 1, wherein the first conductive layer is formed to a thickness of about 5000 GPa. The method of claim 1, wherein an inner pillar A of the storage node has a thickness equal to a width of an inclined portion of an upper portion of the storage node contact. The method of claim 1, wherein the outer pillar B of the storage node has a thickness equal to a width of an inclined region of an edge portion of the storage node pattern.