JPH0629463A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To reduce an irregularity in capacitance of a capacitor and to simplify manufacturing steps in a method for manufacturing a semiconductor element and hence capacitor cells of a DRAM, etc. CONSTITUTION:A method for manufacturing a capacitor cell comprises the steps of forming a polysilicon film 210 for constituting a storage node 218, then forming an insulating film (nitride film) 209 of a lower layer of the film 210 and an insulating film (SiO2) 211 having largely different etching selection ratio, patterning the film 210 and the film 211, and forming polysilicon 214 on its sidewall in a sidewall manner. Then, the method comprises the steps of removing the film 211 and forming the films 210, 214 as storage nodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing mainly a capacitive element portion of a semiconductor device, and more particularly to a DRAM (Dynam).
The present invention relates to a method for manufacturing a stacked capacitor cell structure of ic Random Access Memory).

[0002]

2. Description of the Related Art FIG. 3 shows a conventional method for manufacturing a DRAM memory cell having a stacked capacitor structure, which will be described below.

First, the LOC is formed on the silicon single crystal substrate 101.
A field oxide film 102 is selectively formed using an OS (selective oxidation) method to separate an active region 103 and a field region 104. Next, on the active area 103,
A gate electrode 105 using a polycrystalline silicon film (hereinafter, referred to as polysilicon) to which impurities such as arsenic and phosphorus are added or a silicide film is formed, and a MOS transistor using an impurity diffusion layer by ion implantation as a source / drain electrode 106 is formed. To do. After that, a SiO ₂ film 107 is formed by a CVD (Chemical Vapor Deposition) method, and a contact hole (hereinafter referred to as a cell contact) for connecting the impurity diffusion layer 106 and a lower electrode (hereinafter referred to as a storage node) of the capacitor. Note).

Next, a nitride film 108 having a large selection ratio with the SiO ₂ film 110 formed by the CVD method of FIG. 3C, which is formed in a later step, is formed by the CVD method, and the cell contact is opened again ( FIG. 3A). Next, a polysilicon film is formed and patterned to form the bottom electrode 109 of the storage node (FIG. 3B).

[0005] Next, the SiO ₂ film 110 was produced on the entire surface by the CVD method, an SiO ₂ film on the bottom electrode 109 to form a contact hole by etching. Next, a polysilicon film 111 is formed thereon (FIG. 3).
(C)).

[0006] Then, a polysilicon film 111 is etched, machined As the SiO ₂ film 110 sidewall polysilicon sidewall is formed, when removing the SiO ₂ film 110 by wet etching in HF, etc. FIG 3 ( d)
As described above, the polysilicon has a shape having a portion remaining in the column 112. Then, impurities such as As are added to the polysilicon films 109 and 112 by ion implantation to form storage nodes. Next, a dielectric film such as a nitride film is formed on the storage node, and a polysilicon film is formed on the dielectric film to form an upper electrode (hereinafter referred to as a cell plate) 1
13 is formed (FIG. 3E).

[0007]

However, in the above capacitor structure, it is expected that the polysilicon film of the bottom electrode is also etched during the etching for forming the sidewall-shaped polysilicon film. Therefore, there is a problem that the polysilicon film thickness in the bottom electrode after etching has a large variation, resulting in a large variation in the capacitor capacitance and the contact resistance of the cell contact. In addition, since the photolithography (photolithography) step needs to be performed at least three times after forming the cell contact and before forming the storage node, the capacitor capacitance varies due to misalignment of patterns and variations in resist dimensions. There was a problem.

According to the present invention, in order to eliminate the above-mentioned problem that the variation of the capacitance value of the capacitor becomes large, the steps of removing the polysilicon etching to the bottom electrode and forming the storage node after the cell contact opening. In order to provide a method of manufacturing a stacked capacitor structure capable of reducing the variation in capacitance by performing the photolithography process once and simplifying the process.

[0009]

To achieve the above object, the present invention is a method of manufacturing a stacked capacitor structure for a DRAM, in which after a polysilicon film 210 forming a storage node is formed as shown in FIGS. An insulating film having a large etching selection ratio to the insulating film 209 below the polysilicon film (for example, the SiO ₂ film 21 formed by the CVD method).
1) to generate the polysilicon film 210 and the insulating film 21.
1 is patterned, and then an insulating film 211 and a polysilicon film (polysilicon sidewalls 214 on the sidewalls of 210) are formed.
18 is formed.

[0010]

Since the present invention has the above-described forming method,
The polysilicon film for forming the bottom electrode of the storage node and the SiO ₂ film for forming the sidewall-shaped polysilicon layer can be formed by a single photolithography / etching process, which reduces variations in capacitor capacitance. And the process can be simplified.

[0011]

1 is a process sectional view showing an embodiment of the present invention, which will be described below.

First, an active region 203 and a field region 204 are separated on the substrate 201 by selectively forming a field oxide film 202 on a silicon single crystal substrate (hereinafter simply referred to as a substrate) 201 using a LOCOS method. To do. Next, an insulating film (gate insulating film) 206 of the MOS transistor is formed on the active region 203 by a thermal oxidation method. Next, a polysilicon film or a silicide film to which impurities such as arsenic and phosphorus are added is formed and patterned to form a gate electrode 2 of the MOS transistor.
07 is formed. After that, arsenic, phosphorus, etc. are ion-implanted using the gate electrode 207 as a mask to
An impurity diffusion layer 205 to be a drain region is formed. After that, a SiO ₂ film 208 is deposited by the CVD method, and subsequently, is formed on the SiO ₂ film 208 in a later step.
An insulating film (for example, a nitride film) 209 that can have a large etching selection ratio with the insulating film 211 of (b) is formed (FIG. 1).
(A)).

Next, a cell contact 217 is opened to connect the impurity diffusion layer 205 and the storage node.
Then, a polysilicon film 210 is formed, and then CVD is performed.
An insulating film 211 such as a SiO ₂ film is formed by the method (FIG. 1B).

Next, the polysilicon film 210 and the insulating film 211 are simultaneously etched by using the patterned resist material 212 as a mask (FIG. 1).
(C)).

Next, after removing the resist 212, a polysilicon film 213 is formed as shown in FIG. 2D, and the polysilicon film 213 is etched by a known etching technique to insulate it from the polysilicon film 210. The sidewall of the film 211 is processed to form a sidewall-shaped polysilicon film 214 as shown in FIG. Then, the insulating film 211 is removed by using an etching technique having a large selection ratio with respect to the insulating film (nitride film) 209, and impurities such as arsenic are added to the polysilicon films 210 and 214, thereby forming the storage node 218. Form. Then, on the storage node 218, a cell plate 21 made of a dielectric film 215 such as a silicon nitride film and a polysilicon film is formed.
6 is formed (FIG. 2 (f)).

[0016]

As described above, according to the forming method of the present invention, the polysilicon film for forming the bottom electrode of the storage node and the SiO ₂ film for forming the sidewall-shaped polysilicon film are formed. Since it can be formed by one-time photolithography / etching process, it is expected to reduce variations in capacitor capacitance and simplify the process.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 Conventional example

[Explanation of symbols]

 209 Insulating film (nitride film) 210, 213 Polysilicon film 211 Insulating film 214 Sidewall 215 Dielectric film 216 Cell plate 218 Storage node

Claims (1)

[Claims] 1. A method comprising: (a) forming a first insulating film on a semiconductor substrate, and forming a second insulating film on the first insulating film; Forming step, (b) forming a contact hole at a predetermined position of the first and second insulating films, (c) forming a first conductive film on the structure up to the above step, and forming And (d) patterning the first conductive film and the third insulating film so as to remain at a predetermined position in a portion including the contact hole, (e) Forming a sidewall-shaped second conductive film on the sidewalls of the patterned first conductive film and the third insulating film; (f) removing the third insulating film to form the first and second insulating films; The impurity is introduced into the conductive film of the capacitor to form a storage node in the capacitor cell section. A method of manufacturing a semiconductor device characterized by comprising the above steps.