KR100235983B1 - Method for manufacturing stacked type capacitor - Google Patents
Method for manufacturing stacked type capacitor Download PDFInfo
- Publication number
- KR100235983B1 KR100235983B1 KR1019910015860A KR910015860A KR100235983B1 KR 100235983 B1 KR100235983 B1 KR 100235983B1 KR 1019910015860 A KR1019910015860 A KR 1019910015860A KR 910015860 A KR910015860 A KR 910015860A KR 100235983 B1 KR100235983 B1 KR 100235983B1
- Authority
- KR
- South Korea
- Prior art keywords
- polycrystalline silicon
- film
- silicon film
- oxide film
- depositing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
본 발명은 소자의 신뢰성 개선 및 커패시터 용량을 늘리고 집적도를 향상시키기 위한 적층형 커패시터 제조방법에 관한 것으로, 통상적인 방법으로 워드라인을 형성하는 공정과, 워드라인과 커패시터간의 절연용 제1산화막(4)과 SOG(5)를 증착하여 평탄화하고 질화막(6)과 스토리지 노드용 제1다결정 규소막(7) 및 제2산화막(8)을 증착하여 커패시터 베리드 콘택을 형성하는 공정과, 콘택부위와 제2산화막(8)위에 스토리지 노드용 제2다결정 규소막(10)과 제3산화막(11) 및 스토리지 노드용 제3다결정 규소막(12)을 차례로 증착하여 콘택의 상측부위만 남기고 제3산화막(11)과 제3다결정 규소막(12)을 식각제거하는 공정과, 계속하여 스토리지 노드용 제4다결정 규소막(14)을 증착하고 제4, 제3, 제2다결정 규소막(14,12,10)을 에치백하여 제1다결정 규소막 측벽을 형성하는 공정과, 제4산화막(15)을 증착하고, 제4, 제2산화막(15,8)을 에치백하여 산화막 측벽을 형성하는 공정과, 제5다결정 규소막(16)을 증착하고, 제5, 제1다결정 규소막(16,7)을 에치백하여 제2다결정 규소막 측벽을 형성하는 공정과, 상기의 제1, 제2다결정 규소막 측벽사이의 산화막을 식각제거하고 유전체막(17)과 플레이트용 다결정 규소막(18)을 증착하는 공정으로 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a stacked capacitor for improving device reliability, increasing capacitor capacity, and improving integration. The method includes forming a word line by a conventional method, and insulating first oxide film 4 between the word line and the capacitor. And SOG (5) to planarize and to form a capacitor buried contact by depositing and planarizing the nitride film (6), the first polycrystalline silicon film (7) and the second oxide film (8) for the storage node; The second polycrystalline silicon film 10 for the storage node, the third oxide film 11, and the third polycrystalline silicon film 12 for the storage node are sequentially deposited on the second oxide film 8, leaving only the upper portion of the contact. 11) and etching the third polycrystalline silicon film 12, and subsequently, depositing the fourth polycrystalline silicon film 14 for the storage node and depositing the fourth, third and second polycrystalline silicon films 14, 12, 10) is etched back to form the first polycrystalline silicon film sidewalls. A process of depositing the fourth oxide film 15, etching back the fourth and second oxide films 15, 8 to form sidewalls of the oxide film, and depositing the fifth polycrystalline silicon film 16; And etching the first polycrystalline silicon films 16 and 7 to form sidewalls of the second polycrystalline silicon film, and removing the oxide film between the first and second polycrystalline silicon film sidewalls by etching the dielectric film 17. And a polycrystalline silicon film 18 for plates.
Description
제1도는 본 발명의 적층형 커패시터 공정단면도.1 is a cross-sectional view of a multilayer capacitor process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 3 : 게이트1: silicon substrate 3: gate
4, 8, 11, 15 : 산화막 5 : SOG4, 8, 11, 15: oxide film 5: SOG
6 : 질화막 7, 10, 12, 14, 16 : 다결정 규소막6: nitride film 7, 10, 12, 14, 16: polycrystalline silicon film
9, 13 : 포토 레지스트 17 : 유전체막9, 13 photoresist 17 dielectric film
18 : 플레이트 다결정 규소막18: plate polycrystalline silicon film
본 발명은 고집적 반도체 메모리 소자에 관한 것으로 특히 적층형 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to highly integrated semiconductor memory devices, and more particularly to a method of manufacturing a multilayer capacitor.
종래의 적층형 커패시터는 다음과 같은 방법으로 제조된다.Conventional multilayer capacitors are manufactured in the following manner.
즉, 실리콘 기판에 LOCOS(Local Oxidation of Silicon)방법으로 필드영역과 엑티브영역을 구분하고 트랜지스터 형성을 위한 게이트 산화막으로써 고열 확산로에서 산화막을 성장시키고 그위에 도핑(Doping)된 다결정 규소막이나 폴리사이드막(다결정 규소막+실리사이드)을 성장시킨다. 이후, 게이트 트랜지스터형성을 위하여 감광제를 도포하여 노광을 거쳐 성형하고 건식 식각으로 다결정막이나 폴리사이드막을 수직으로 식각하여 워드 라인(word line)을 형성한다. 이때, 게이트 트랜지스터의 다결정 규소막위에 증착산화막을 형성하여 소오스/드레인 불순물 이온주입시 다결정 규소막을 뚫고 들어가는 채널링(channeling)을 방지하기 위해 첨가시킬 수 있다.In other words, the silicon substrate is divided into a field region and an active region by LOCOS (Local Oxidation of Silicon) method, and as a gate oxide film for forming a transistor, an oxide film is grown in a high temperature diffusion furnace and doped thereon. The film (polycrystalline silicon film + silicide) is grown. Subsequently, a photoresist is applied to form a gate transistor, which is formed through exposure, and a polyline or polyside layer is vertically etched by dry etching to form a word line. In this case, a deposition oxide film may be formed on the polysilicon film of the gate transistor to be added to prevent channeling through the polycrystalline silicon film during source / drain impurity ion implantation.
그 뒤, 쇼트채널(short channel)방지를 위한 측벽을 형성하여 이온주입으로 LDD(Lightly Doped Drain)구조의 소오스/드레인을 형성한다. 이어서 게이트 트랜지스터의 다결정 규소막과 커패시터 노드용 다결정 규소막을 절연시키기 위해 규소막간 산화막을 증착하고 기판과 커패시터 노드가 연결될 수 있도록 포토 에치 공정으로 베리드 콘텍(Burried Contact)을 형성한다.Thereafter, sidewalls for short channel prevention are formed to form a source / drain of a lightly doped drain (LDD) structure by ion implantation. Subsequently, in order to insulate the polycrystalline silicon film of the gate transistor from the polycrystalline silicon film for the capacitor node, an oxide film is deposited between the silicon film and a buried contact is formed by a photo etch process so that the substrate and the capacitor node can be connected.
그리고 스토리지 노드용 다결정 규소막을 산화막위와 콘텍부위에 증착하고 마스크공정으로 노드를 정의하여 불필요한 부분을 식각제거하고 마스크도 제거한 다음 유전체막과 플레이트 노드용 다결정 규소막을 증착시켜 불필요한 부분을 제거하여 적층형 커패시터를 제조한다.Then, a polycrystalline silicon film for the storage node is deposited on the oxide layer and the contact portion, and a node is defined by a mask process to remove the unnecessary portions, and the mask is also removed. Manufacture.
그러나 종래의 적층형 커패시터는 정전용량이 작아 디램(DRAM)의 재충전(Refresh)특성과 소자 신뢰도가 저하되고 집적도가 낮아 칩(Chip)면적이 크다.However, the conventional multilayer capacitor has a small capacitance, which lowers the refresh characteristics of the DRAM, device reliability, and has a low chip density.
본 발명은 이와 같은 문제점을 해결하기 위해 안출한 것으로, 소자의 신뢰성 개선 및 커패시턴스 용량을 늘리고, 집적도를 향상시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to improve reliability of a device, increase capacitance capacity, and improve integration.
이와 같은 목적을 달성하기 위한 본 발명은 통상적인 방법으로 워드라인을 형성하고 SOG를 도포하여 평탄화한 뒤, 다결정 규소막과 산화막을 증착하여 커패시터 베리드 콘택을 형성한 다음 그위에 다결정 규소막과 산화막, 다결정 규소막을 증착하여 포토 예치하고 다결정 규소막과 산화막을 증착하면서 에치백하여 1,2차 측벽 다결정 규소막을 형성한다. 이렇게 형성된 다결정 규소막을 스토리지 노드로 하고, 유전체막과 플레이트용 다결정 규소막을 증착하여 커패시터를 제조하는 것이다. 상기와 같은 본 발명의 실시예를 첨부된 제1도를 참조하여 보다 상세히 설명하면 다음과 같다.In order to achieve the above object, the present invention forms a word line in a conventional manner, applies SOG to planarize, and then deposits a polycrystalline silicon film and an oxide film to form a capacitor buried contact, and then a polycrystalline silicon film and an oxide film thereon. Then, the polycrystalline silicon film is deposited to be photo-deposited and etched back while the polycrystalline silicon film and the oxide film are deposited to form the first and second sidewall polycrystalline silicon films. The polycrystalline silicon film thus formed is used as a storage node, and a capacitor is manufactured by depositing a dielectric film and a polycrystalline silicon film for plate. Referring to the attached embodiment of the present invention as described above in more detail as follows.
즉, 제1a도와 같이 실리콘기판(1)에 국부산화막 증착법(LOCOS)으로 필드영역과 엑터브영역을 정의한 후 고열확산로에서 산화막을 성장시켜 그위에 도핑된 다결정 규소막이나 폴리사이드막과, 캡게이트 산화막을 증착하고 포토에치공정으로 게이트(3)형성으로 워드라인을 형성한 후 소오스/드레인 이온주입하고 쇼트 채널 방지를 위한 게이트에 측벽산화막을 형성하여 불순물 이온주입으로 LDD구조의 소오스/드레인을 형성한다.In other words, as shown in FIG. 1A, a field region and an extrude region are defined on the silicon substrate 1 by LOCOS, and an oxide film is grown in a high-temperature diffusion furnace, and a doped polycrystalline silicon film or polyside film and cap After depositing the gate oxide film and forming the word line by forming the gate (3) by the photoetch process, source / drain ion implantation and sidewall oxide film are formed on the gate to prevent short channel, and impurity ion implantation results in source / drain of LDD structure To form.
제1b도와 같이 트랜지스터와 커패시터의 절연을 위해 제1산화막(4)을 증착하고 SOG(5)를 증착하여 평탄화한 뒤 제1c도와 같이 질화막(6)과 스토리지 노드용 제1다결정 규소막(7)을 증착하고 제2산화막(8)를 증착한다.As shown in FIG. 1B, the first oxide film 4 is deposited to insulate the transistor and the capacitor, and the SOG 5 is deposited and planarized. Then, as shown in FIG. 1C, the nitride film 6 and the first polycrystalline silicon film 7 for the storage node. Is deposited and the second oxide film 8 is deposited.
그리고, 제1d도와 같이 포토 레지스트(9)를 이용, 식각하여 노드 베리드 콘택을 형성하고 포토 레지스트(9)를 제거한 뒤, 스토리지 노드용 제2다결정 규소막(10)과 두꺼운 제3산화막(11)과 제2다결정 규소막과 똑같은 두께로 제3다결정 규소막(12)을 차례로 증착하고, 포토 레지스트(13)을 증착하여 제1e도와 같이 콘택 상측부위만 남겨두고, 제3산화막(11)과 제3다결정 규소막(12)을 식각 제거한다.As shown in FIG. 1D, the node resist contact is formed by etching using the photoresist 9 to remove the photoresist 9, and then the second polycrystalline silicon film 10 for the storage node and the thick third oxide film 11 are formed. ) And the third polycrystalline silicon film 12 are sequentially deposited to the same thickness as the second polycrystalline silicon film, and the photoresist 13 is deposited to leave only the upper portion of the contact as shown in FIG. The third polycrystalline silicon film 12 is etched away.
계속해서 제1f도와 같이 포토 레지스트(13)를 제거하고 제4다결정 규소막(14)을 증착한 뒤, 제1g도와 같이 제4다결정 규소막(14)과 제3다결정 규소막(12) 및 제2다결정 규소막(10)을 에치백하여 제1다결정 규소막 측벽을 형성하고 제4산화막(15)을 증착한 다음 제1h도와 같이 제4산화막(15)과 제2산화막(8)을 에치백하여 산화막 측벽을 형성하고 제5다결정 규소막(16)을 증착한다.Subsequently, after removing the photoresist 13 and depositing the fourth polycrystalline silicon film 14 as shown in FIG. 1f, the fourth polycrystalline silicon film 14 and the third polycrystalline silicon film 12 and the first film as shown in FIG. The second polycrystalline silicon film 10 is etched back to form sidewalls of the first polycrystalline silicon film, the fourth oxide film 15 is deposited, and the fourth oxide film 15 and the second oxide film 8 are etched back as shown in FIG. Thereby forming an oxide film sidewall and depositing a fifth polycrystalline silicon film 16.
그리고, 제1i도와 같이 제5다결정 규소막(16)과 제1다결정 규소막(7)을 에치백하여 제2다결정 규소막 측벽을 형성한 후 산화막을 식각 제거하여 커패시터 스토리지 노드(9)를 형성한 다음 제1j도와 같이 유전체막(17)과 플레이트 다결정 규소막(18)을 증착하여 커패시터를 제조한다.Then, as shown in FIG. 1i, the fifth polycrystalline silicon film 16 and the first polycrystalline silicon film 7 are etched back to form sidewalls of the second polycrystalline silicon film, and the oxide layer is etched away to form the capacitor storage node 9. Next, as shown in FIG. 1j, a dielectric film 17 and a plate polycrystalline silicon film 18 are deposited to fabricate a capacitor.
이상에서 설명한 바와 같이 본 발명은 마스크 공정없이 에치백 공정으로 커패시터의 용량을 확장시키고 디램의 재충전 특성과 소자의 신뢰도를 개선시키며 집적도를 향상시키는 효과가 있다.As described above, the present invention has the effect of extending the capacitance of the capacitor by the etch back process without the mask process, improving the recharging characteristics of the DRAM and the reliability of the device, and improving the degree of integration.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015860A KR100235983B1 (en) | 1991-09-11 | 1991-09-11 | Method for manufacturing stacked type capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015860A KR100235983B1 (en) | 1991-09-11 | 1991-09-11 | Method for manufacturing stacked type capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930006909A KR930006909A (en) | 1993-04-22 |
| KR100235983B1 true KR100235983B1 (en) | 1999-12-15 |
Family
ID=19319823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910015860A KR100235983B1 (en) | 1991-09-11 | 1991-09-11 | Method for manufacturing stacked type capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100235983B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248062A (en) * | 1985-08-28 | 1987-03-02 | Sony Corp | Memory cell |
| KR870005471A (en) * | 1985-11-29 | 1987-06-09 | 가부시끼가이샤 히다찌세이사꾸쇼 | Semiconductor memory with stacked capacity and manufacturing method thereof |
-
1991
- 1991-09-11 KR KR1019910015860A patent/KR100235983B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248062A (en) * | 1985-08-28 | 1987-03-02 | Sony Corp | Memory cell |
| KR870005471A (en) * | 1985-11-29 | 1987-06-09 | 가부시끼가이샤 히다찌세이사꾸쇼 | Semiconductor memory with stacked capacity and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930006909A (en) | 1993-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5686337A (en) | Method for fabricating stacked capacitors in a DRAM cell | |
| JPH10321814A (en) | Planarization technique for dram cell capacitor electrode | |
| US6335248B1 (en) | Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technology | |
| KR970063744A (en) | Method for manufacturing cylindrical storage nodes of stacked capacitors in memory cells | |
| KR0151197B1 (en) | Semconductor device & its manufacturing method | |
| US6872629B2 (en) | Method of forming a memory cell with a single sided buried strap | |
| KR0151385B1 (en) | Semiconductor memory device and its manufacturing method | |
| US5913129A (en) | Method of fabricating a capacitor structure for a dynamic random access memory | |
| US6548348B1 (en) | Method of forming a storage node contact hole in a porous insulator layer | |
| US5723374A (en) | Method for forming dielectric spacer to prevent poly stringer in stacked capacitor DRAM technology | |
| KR0141950B1 (en) | Manufacturing method of semiconductor device | |
| US7122855B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| US5534457A (en) | Method of forming a stacked capacitor with an "I" shaped storage node | |
| KR100235983B1 (en) | Method for manufacturing stacked type capacitor | |
| KR940009631B1 (en) | Manufacturing method of dram with trench capacitor | |
| US5989954A (en) | Method for forming a cylinder capacitor in the dram process | |
| US6251725B1 (en) | Method of fabricating a DRAM storage node on a semiconductor wafer | |
| US7700435B2 (en) | Method for fabricating deep trench DRAM array | |
| KR20000013402A (en) | Fabrication method of memory capacitor | |
| US20040132245A1 (en) | Method of fabricating a dram cell | |
| US6218240B1 (en) | Method of fabricating low voltage coefficient capacitor | |
| JP3214615B2 (en) | Semiconductor storage device | |
| KR930012121B1 (en) | Method of fabricating a stacked capacitor | |
| KR930009580B1 (en) | Method for manufacturing a lsi mos memory device with capacitor | |
| KR960006716B1 (en) | Semiconductor integrated circuit device fabrication process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050822 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |