KR930009580B1 - Method for manufacturing a lsi mos memory device with capacitor - Google Patents

Method for manufacturing a lsi mos memory device with capacitor Download PDF

Info

Publication number
KR930009580B1
KR930009580B1 KR1019900016281A KR900016281A KR930009580B1 KR 930009580 B1 KR930009580 B1 KR 930009580B1 KR 1019900016281 A KR1019900016281 A KR 1019900016281A KR 900016281 A KR900016281 A KR 900016281A KR 930009580 B1 KR930009580 B1 KR 930009580B1
Authority
KR
South Korea
Prior art keywords
forming
oxide film
film
gate
polycrystalline silicon
Prior art date
Application number
KR1019900016281A
Other languages
Korean (ko)
Other versions
KR920008972A (en
Inventor
김상균
김준식
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019900016281A priority Critical patent/KR930009580B1/en
Publication of KR920008972A publication Critical patent/KR920008972A/en
Application granted granted Critical
Publication of KR930009580B1 publication Critical patent/KR930009580B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The fabricates a capacitor for increasing capacitance. The method includes the steps of forming a gate on the substrate, forming a lightly doped source and drain region by ion implanting n-type impurity using the gate as a mask, forming a sidewall oxide on the side of the gate, forming a highly doped source and drain region by ion implanting n-type impurity using the gate and the sidewall oxide layer as a mask, forming oxide, nitride and oxide layers successively, selective etching the oxide layer to remain only on the gate, forming a storage node buried contact by removing the oxide layer and the nitride layer selectively, forming a polysilicon layer on the resultant, forming a storage node by etching the polysilicon layer selectively, forming an ONO and plate electrode on the storage node.

Description

고집적 모스 기억소자의 캐패시터 제조방법Capacitor Manufacturing Method of High Density Morse Memory

제 1 도는 종래의 공정 단면도.1 is a cross-sectional view of a conventional process.

제 2 도는 본 발명의 공정 단면도.2 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 게이트산화막 4,13,15 : 다결정규소막3: gate oxide film 4,13,15 polysilicon film

5,7,8,10 : 증착산화막 6,11,12 : 감광체5,7,8,10 Deposition oxide film 6,11,12 Photosensitive member

9 : 질화막 14 : ONO막9: nitride film 14: ONO film

본 발명은 고집적 모스 기억소자의 커패시터 제조방법에 관한 것으로, 특히 커패시터의 노드로 사용되는 다결정 규소막 아래에 커패시터 면적 확장용 막을 형성하여 커패시턴스를 향상시키기에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a highly integrated MOS memory device, and in particular, to form a capacitor area-expanding film under a polycrystalline silicon film used as a node of a capacitor so as to be suitable for improving capacitance.

그리고 게이트 트랜지스터 형성을 위한 마스크 공정을 감광제(6) 도포, 노광, 현상을 거쳐 성형하고 건식식각을 통하여 (b)와 같이 다결정규소막(4)을 수직으로 식각하여 워드라인을 형성한다.The mask process for forming the gate transistor is formed by coating, exposing, and developing the photosensitive agent 6, and through the dry etching, the polysilicon film 4 is vertically etched as shown in (b) to form a word line.

이하 (c)와 같이 증착산화막(7)을 형성하여 소오스 및 드레인 형성을 위한 이온주입시 이온이 다결정 규소막(4)을 뚫고 들어가는 채널링(Channeling) 현상을 방지하도록 한다.As shown in (c), the deposition oxide film 7 is formed to prevent channeling ions penetrating the polysilicon film 4 during ion implantation for source and drain formation.

다음에 (d)와 같은 쇼트채널 방지를 위한 측벽(7a)을 형성하고 LDD 이온주입을 실시한다.Next, the side wall 7a for short channel prevention as shown in (d) is formed and LDD ion implantation is performed.

이어서 (e)와 같이 게이트 트랜지스터의 다결정 규소막과 커패시터 노드용 다결정 규소막을 절연시키기 위해 규소막간 산화막(8)을 증착시키고 산화막 사이 접합부위를 커패시터의 노드와 연결될 수 있도록 감광제(9)를 사용한 마스크 공정을 거쳐 건식(또는 습식) 식각으로 매몰콘택트를 형성한다.Subsequently, as shown in (e), a mask using a photosensitive agent 9 is deposited so as to deposit an inter-silicon oxide film 8 to insulate the polycrystalline silicon film of the gate transistor from the polycrystalline silicon film for the capacitor node and connect the junction between the oxide films with the node of the capacitor. Through the process, a buried contact is formed by dry (or wet) etching.

그리고 (f)와 같이 노드용 다결정 규모막(10)을 규소막간 산화막위와 접합부 표면위로 증착시키고 사진식각 방법에 의해 노드를 정의한다.As shown in (f), the polycrystalline scale film 10 for the node is deposited on the inter-silicon oxide film and the junction surface, and the node is defined by a photolithography method.

이후 (g)와 같이 ONO막(11), 플레이트용 다결정 규소막(12)을 차례로 형성하여 패터닝하므로 적층형커패서터를 제조할 수 있었다.Thereafter, as shown in (g), the ONO film 11 and the plate polycrystalline silicon film 12 were sequentially formed and patterned, thereby manufacturing a multilayer capacitor.

그러나, 상기와 같은 종래 기술에 있어서는 커패시터의 적층높이가 낮아 커패시턴스가 작으므로 소자의 신뢰도가 저하되었고 집적도가 낮아 칩면적이 커지는 결점이 있었다.However, in the conventional technology as described above, since the capacitance of the capacitor is low due to the low stacking height of the capacitor, the reliability of the device is lowered and the chip area is increased due to the low integration.

본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로, 커패시터의 적층높이를 높게 하여 커패시턴스를 향상시키고 집적도를 높일 수 있는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a method of improving capacitance and increasing integration by increasing a stack height of capacitors.

이하에서 본 발명을 첨부된 도면 제 2 도를 참고로 하여 상술하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to FIG. 2.

먼저(a)-(c)와 같이 기판(1) 위에 필드산화막(2)과 게이트 산화막(3)을 형성하여 필드영역과 액티브영역을 구분하고 그 위에 도핑된 다결정 규소막(4), 증착산화막(5)을 차례로 형성한 후 감광제(6)를 사용하여 상기 다결정 규소막(4) 및 증착산화막(5)을 수직으로 식각하여 워드라인(게이트)를 형성하고, 게이트를 마스크로 하여 저농도 n형 소오스 및 드레인영역을 형성한 다음(도면에는 도시되지 않음) 감광제(6)를 제거한다.First, as in (a)-(c), the field oxide film 2 and the gate oxide film 3 are formed on the substrate 1 to distinguish the field region from the active region, and the polycrystalline silicon film 4 and the doped oxide film doped thereon. After forming (5) in sequence, the polysilicon film 4 and the deposited oxide film 5 were etched vertically using a photosensitive agent 6 to form a word line (gate), and the gate was used as a mask to form a low concentration n-type. After forming the source and drain regions (not shown), the photosensitive agent 6 is removed.

그리고 전면에 증착산화막(7)을 형성하고 에치백하여 게이트에 측벽을 형성한 후 고농도 n형 이온주입으로 LDD 구조의 소오스 및 드레인 영역을 형성한다(도면에는 도시되지 않음).Then, the deposition oxide film 7 is formed on the entire surface and etched back to form sidewalls on the gate, and then source and drain regions of the LDD structure are formed by high concentration n-type ion implantation (not shown).

(d)와 같이 전면에 증착산화막(8), 질화막(9), 증착산화막(10)을 차례로 형성한다.As shown in (d), the deposition oxide film 8, the nitride film 9, and the deposition oxide film 10 are sequentially formed.

이때의 질화막(9)의 두께는 1000Å-3000Å 정도이고 증착산화막(10)의 두께는 4000Å-8000Å 정도로 한다. 이어서, (e)와 같이 워드라인(게이트)들과 정합을 이룰 수 있도록 감광제를 이용하여 (11) 마스크를 정의하고 상기 증착산화막(10)을 건식식각한다.At this time, the thickness of the nitride film 9 is about 1000 kPa-3000 kPa and the thickness of the deposited oxide film 10 is about 4000 kPa-8000 kPa. Subsequently, as shown in (e), a mask (11) is defined using a photosensitive agent so as to be matched with the word lines (gates), and the deposition oxide film 10 is dry-etched.

여기서 건식식각시 수직식각과 등방성 식각을 통해 식각하고 감광제(11)를 제어하여 T자형의 산화막(10)이 형성되게 한다.Here, during the dry etching, the etching is performed through vertical etching and isotropic etching, and the photosensitive agent 11 is controlled to form the T-shaped oxide film 10.

이때, 등방성 식각이 되는 부위의 두께는 3000Å-7000Å으로 한다.At this time, the thickness of the portion to be isotropic etching is 3000 kPa-7000 kPa.

이후에 (f)와 같이 접합부위를 커패시터의 노드와 연결될 수 있도록 감광제(12)를 사용한 마스크 공정을 거쳐 증착산화막(8)과 질화막(9)을 선택적으로 건식(또는 습식) 식각에 의해 스토리지노드용 매몰콘택트를 형성한다.Thereafter, as shown in (f), the storage node is selectively dry (or wet) etched through the deposition oxide film 8 and the nitride film 9 through a mask process using a photosensitive agent 12 so that the junction portion can be connected to the node of the capacitor. A buried contact is formed.

또한, (g)와 같이 노드용 다결정 규소막(13)을 규소막간 절연용 산화막 위와 개공된 접합부위에 T자형 상이 도포되도록 증착시킨다.Further, as shown in (g), the node polycrystalline silicon film 13 is deposited so that a T-shaped phase is applied onto the inter-silicon insulating oxide film and the junction where the hole is opened.

여기서, 노드용 다결정 규소막(13)의 두께는 1000Å-3000Å으로 하고 T자형 아랫부분은 1000Å 정도의 두께가 남도록 진행한다.Here, the thickness of the node polycrystalline silicon film 13 is set to 1000 mW-3000 mW, and the lower portion of the T-shaped portion proceeds to have a thickness of about 1000 mW.

이어서, (h)와 같이 상기 노드용 다결정 규소막(13)에 도핑을 한 후 마스크 공정을 통해 노드를 정의하고 건식식각을 한 후 감광제를 제거한다.Subsequently, after doping the polycrystalline silicon film 13 for the node as shown in (h), a node is defined through a mask process, and the photoresist is removed after dry etching.

마지막 공정으로 (i)와 같이 유전체인 ONO막(14)과 플레이트용 다결정 규소막(15)을 증착한 후 패터닝하므로 적층형 커패시터를 제조할 수 있다.As a final process, a multilayer capacitor may be manufactured by depositing and patterning the ONO film 14, which is a dielectric, and the polycrystalline silicon film 15 for plates, as shown in (i).

이상과 같은 본 발명에 의하면 T자형상 높이만큼 커패시터의 용량을 증대시킬 수 있어 커패시턴스가 향상됨은 물론 집적도를 높일 수 있는 장점이 있다.According to the present invention as described above can increase the capacitance of the capacitor by the height of the T-shape, there is an advantage that the capacitance is improved as well as the degree of integration.

Claims (5)

기판(1)위에 필드영역과 액티브영역을 구분하여 필드영역에 필드산화막(2)을 형성하고 그 위에 다결정 규소막(4), 증착산화막(5)을 형성한 후 다결정 규소막(4)과 증착산화막(5)을 선택적으로 수직으로 식각하여 게이트를 형성하는 공정과, 상기 게이트를 마스크로 하여 저농도 n형 이온주입으로 저농도 소오스 및 드레인 영역을 형성하고 게이트에 증착산화막(8)으로 측벽을 형성하는 공정과, 상기 게이트 및 측벽을 마스크로 이용하여 고농도 소오스 및 드레인 영역을 형성하는 공정과, 전면에 증착산화막(8), 질화막(9), 증착산화막(10)을 차례로 형성하고 마스크를 사용하여 상기 게이트 위에만 남도록 증착산화막(10)을 건식식각하는 공정과, 상기 소오스 영역의 증착산화막(8)과 질화막(9)을 선택적으로 제거하여 스토리지노드 매몰콘택트를 형성한 후 전면에 노드용 다결정 규소막(13)을 증착시키는 공정과, 상기 노드용 다결정 규소막(13)의 불필요한 부분을 제거하고, 그 위에 ONO막(14), 플레이트용 다결정 규소막(15)을 패터닝하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 고집적 모스 기억소자의 커패시터 제조방법.After forming the field oxide film 2 in the field region by separating the field region and the active region on the substrate 1, forming the polycrystalline silicon film 4 and the deposition oxide film 5 thereon, and then depositing the polycrystalline silicon film 4 and the deposition process. Forming a gate by selectively etching the oxide film 5 vertically, and forming a low concentration source and drain region by using a low concentration n-type ion implantation using the gate as a mask, and forming a sidewall with a deposition oxide film 8 in the gate. Forming a high concentration source and drain region using the gate and sidewalls as a mask; and forming a deposition oxide film 8, a nitride film 9, and a deposition oxide film 10 on the entire surface, and using a mask. Dry etching the deposited oxide film 10 so as to remain only on the gate, and selectively removing the deposited oxide film 8 and the nitride film 9 in the source region to form a storage node investment contact. A process of depositing the polycrystalline silicon film 13 for a node, the process of removing the unnecessary part of the said polycrystalline silicon film 13 for a node, and patterning the ONO film 14 and the polycrystalline silicon film 15 for plates on it. Capacitor manufacturing method of a highly integrated MOS memory device, characterized in that is carried out in sequence. 제 1 항에 있어서, 질화막(9)의 두께는 1000Å-3000Å으로 함을 특징으로 하는 고집적 모스 기억소자의 커패시터 제조방법.The method of claim 1, wherein the nitride film has a thickness of 1000 mW-3000 mW. 제 1 항에 있어서, 증착산화막(10)의 두께는 4000Å-8000Å으로 함을 특징으로 하는 고집적 모스 기억 소자의 커패시터 제조방법.The method of claim 1, wherein the deposited oxide film (10) has a thickness of 4000 kPa to 8000 kPa. 제 1 항에 있어서, 증착산화막(10)의 건식식각시 수직식각과 등방성 식각을 통해 식각하여 T자형상으로 형성함을 특징으로 하는 고집적 모스 기억소자의 커패시터 제조방법.The method of claim 1, wherein the dry oxide film is etched through vertical etching and isotropic etching during dry etching to form a T-shape. 제 4 항에 있어서, 증착산화막(10)의 등방성 식각이 되는 부위의 두께는 3000Å-7000Å으로 함을 특징으로 하는 고집적 모스 기억소자의 커패시터 제조방법.5. The method of claim 4, wherein the thickness of the portion of the deposited oxide film 10 to be isotropically etched is 3000 kPa-7000 kPa.
KR1019900016281A 1990-10-13 1990-10-13 Method for manufacturing a lsi mos memory device with capacitor KR930009580B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900016281A KR930009580B1 (en) 1990-10-13 1990-10-13 Method for manufacturing a lsi mos memory device with capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900016281A KR930009580B1 (en) 1990-10-13 1990-10-13 Method for manufacturing a lsi mos memory device with capacitor

Publications (2)

Publication Number Publication Date
KR920008972A KR920008972A (en) 1992-05-28
KR930009580B1 true KR930009580B1 (en) 1993-10-07

Family

ID=19304626

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016281A KR930009580B1 (en) 1990-10-13 1990-10-13 Method for manufacturing a lsi mos memory device with capacitor

Country Status (1)

Country Link
KR (1) KR930009580B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394222B1 (en) 1999-07-13 2003-08-06 윤희선 Treatment apparatus in high and low temperature

Also Published As

Publication number Publication date
KR920008972A (en) 1992-05-28

Similar Documents

Publication Publication Date Title
US5492850A (en) Method for fabricating a stacked capacitor cell in semiconductor memory device
US5290726A (en) DRAM cells having stacked capacitors of fin structures and method of making thereof
KR0151197B1 (en) Semconductor device & its manufacturing method
US5114873A (en) Method for manufacturing a stacked capacitor DRAM cell
KR0119961B1 (en) Fabrication method for capacitor of semiconductor device
KR0151385B1 (en) Semiconductor memory device and its manufacturing method
KR960011664B1 (en) Capacitor manufacturing method of semiconductor device
US4373250A (en) Process for fabricating a high capacity memory cell
KR0141950B1 (en) Manufacturing method of semiconductor device
US6833293B2 (en) Semiconductor device and method for manufacturing the same
KR930009580B1 (en) Method for manufacturing a lsi mos memory device with capacitor
KR940010346A (en) DRAM manufacturing method of semiconductor integrated device
KR930009578B1 (en) Method for manufacturing a lsi mos device with capacitor
KR930009588B1 (en) Method for manufacturing a semiconductor memory device
Rideout et al. MOSFET's with polysilicon gates self-aligned to the field isolation and to the source and drain regions
KR930009589B1 (en) Method for manufacturing a capacitor of lsi mos device
US5691221A (en) Method for manufacturing semiconductor memory device having a stacked capacitor
KR930009586B1 (en) Method for manufacturing a semiconductor memory device
KR930009126B1 (en) Method of fabricating capacitor for a high integrated mos device
KR930009587B1 (en) Method for manufacturing a semiconductor device
JP3036117B2 (en) Method for manufacturing semiconductor device
KR930012121B1 (en) Method of fabricating a stacked capacitor
KR930009590B1 (en) Method for manufacturing a lsi mos device with capacitor
KR100235983B1 (en) Method for manufacturing stacked type capacitor
KR0151070B1 (en) Capacitor for soi and its manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050922

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee