JP3036117B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a dynamic RAM having a stacked capacitor in a memory cell.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is becoming highly integrated year by year, and a capacitor portion of a memory cell of a dynamic RAM has a three-dimensional structure in order to secure a sufficiently large storage capacity.
A typical example is a memory cell having a stacked capacitor, which is changed to a three-dimensional structure. In addition, a self-aligned (self-aligned) contact is used to reduce a contact margin.

[0005] A conventional method of manufacturing this type of semiconductor device will be described with reference to FIG. First, a P-type silicon substrate 1
An element isolation region consisting of a field oxide film 2 is formed, a gate oxide film 3 is formed in a transistor region, a first polycrystalline silicon is formed on the entire surface, and a first silicon oxide film 5 is further formed. These are simultaneously patterned to form gate electrodes 4a and 4b which become adjacent word lines.
To form Next, the gate electrode 4 serving as the word line
By implanting an N-type impurity with a low dose using the masks a and 4b as a mask, the low-concentration N ⁻ -type diffusion layer 6 is formed.
Is formed, a third silicon oxide film is formed on the entire surface, and the spacer 7 is formed by anisotropic etching.
Using the spacer 7, the gate electrode and the first silicon oxide film as a mask, an N-type impurity is ion-implanted at a high dose. Thus, N ⁺ -type source and drain diffusion layers 8a and 8b are formed. Thus, an LDD transistor is formed. Subsequently, a second silicon oxide film 9 is formed on the entire surface, and a contact hole is provided on the drain diffusion layer 8b so as to cover the first silicon oxide film 5 of the gate electrodes 4a, 4b, thereby forming a self-aligned contact. Furthermore, a lower electrode 12 of a capacitor for charge storage is formed,
A capacitor insulating film 13 is deposited on the lower electrode 12 to form an upper electrode 14 of the capacitor.

Finally, an interlayer insulating film 15 is deposited on the entire surface, an opening is formed on the source diffusion layer 8a, and an aluminum wiring 16 serving as a bit line is patterned to obtain a one-transistor dynamic RAM. .

[0005]

The above-described conventional method of manufacturing a semiconductor device has a step of forming a self-aligned contact structure in which a contact on a drain diffusion layer is opened in a self-aligned manner with respect to a gate electrode. ing. Since a thick insulating film (oxide film) is present on the gate electrode and a step formed by the gate step is large, an etching residue tends to remain along the side wall of the gate step during etching for forming a capacitor electrode in a later step. There is a drawback in that it is difficult to form a bit line and a bit line contact on the upper layer of the capacitor electrode, and the step coverage deteriorates.

[0006]

A method of manufacturing a semiconductor device according to the present invention comprises a gate electrode provided on a first conductive semiconductor substrate via a gate insulating film, a first insulating film covering the gate electrode, Forming a MIS transistor by providing a source diffusion layer and a drain diffusion layer that are self-aligned with the gate electrode; depositing a second insulating film; and forming a second insulating film on the first insulating film of the MIS transistor. Forming a first resist film having an opening from a region to a region on the drain (or source) diffusion layer; and using the first resist film as a mask until the drain (or source) diffusion layer is exposed. A step of providing a contact hole by performing etching; and, after removing the first resist film, applying a second resist film over the entire surface and then performing an etch back. A step of reducing the thickness of the second insulating film on at least the gate electrode to reduce a step, and a step of forming a conductive film on the contact hole and the periphery thereof after removing the second resist film. It is to have.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 (a) and 1 (b) and FIGS.
FIG. 2B is a sectional view illustrating a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, a thickness of 600 to 70 mm is formed on a P-type silicon substrate 1 in the same manner as in the conventional example.
A field oxide film 2 having a thickness of 0 nm is selectively formed, a gate oxide film 3 is formed on the divided element region, a polycrystalline silicon film having a thickness of 300 to 400 nm is formed on the entire surface, and a thickness of 300 nm is further formed on the entire surface. After forming, for example, a first silicon oxide film 5 as a first insulating film having a thickness of about 400 nm, these are simultaneously patterned to form a gate electrode 4a serving as a word line.
4b is formed. Next, using the gate electrode 4 as a mask, N
The N ^- type diffusion layer 6 is formed by ion-implanting a type impurity at a low dose, a third insulating film (third silicon oxide film) having a thickness of 200 nm is formed on the entire surface, and this is anisotropically etched. By doing so, the spacers 7 are formed on the side walls of the gate electrode and the first silicon oxide film. Using the spacer 7, the gate electrode and the first silicon oxide film as a mask,
Type impurities are ion-implanted at a high dose to form an N ⁺ -type source diffusion layer 8a and a drain diffusion layer 8b. Subsequently, a second insulating film (second silicon oxide film) having a thickness of 200 nm is formed on the entire surface. At this time, the source diffusion layer 8
a, a 200 nm second silicon oxide film 9 is also formed on the drain diffusion layer 8b. Subsequently, a resist is applied to form a first resist film which is applied to both ends of the gate electrodes 4a and 4b and is patterned so as to open a hole on the drain diffusion layer 8b.

Next, as shown in FIG. 1B, when the insulating film is etched by about 250 nm by anisotropic dry etching, the drain diffusion layer 8b is exposed and the gate electrodes 4a, 4b
, A self-aligned contact is formed. Further, after removing the first resist film 10, the second resist film 11a is uniformly applied.

Then, as shown in FIG. 2A, under the condition that the second resist film 11a and the first, second and third silicon oxide films 5, 7, 9 have the same etching rate, respectively. The thickness of the insulating film on the gate electrode 4b is 200 to 30
The entire surface is etched so as to have a thickness of 0 nm.

Subsequently, as shown in FIG. 2B, the second resist film is removed, the lower electrode 12 of the capacitor for charge storage is formed in the same manner as in the prior art, and the capacitor insulating film 13 is formed on the lower electrode 12. And an upper electrode 14 is formed. Finally,
After an interlayer insulating film 15 is deposited on the entire surface and an opening is formed on the source diffusion layer 8a, the aluminum wiring 1 serving as a bit line is formed.
6 to manufacture a one-transistor dynamic RAM.

As described above, since the step of forming the capacitor is performed after the step in the gate stage is reduced by the etch back, lithography and etching in these subsequent steps are facilitated, and the step coverage of the wiring is improved.

Next, a second embodiment of the present invention will be described.

First, as in the first embodiment, up to the self-aligned contact is formed on the drain diffusion layer.

Next, as shown in FIG. 3A, a second resist film 11b is applied. However, a highly viscous coating liquid is used and the shape reflects the underlying shape.

Subsequently, as shown in FIG. 3B, each of the second resist film 11b, the first silicon oxide film 5, the third silicon oxide film 7, and the second silicon oxide film 9 has the same etching rate. 4a, 4a
The entire surface is etched until the first silicon oxide film 7 on b is left by 200 to 300 nm to reduce the level difference and flatten.

Thereafter, the second resist film 11b is removed, and up to the aluminum wiring 16 is formed in the same manner as in the first embodiment to manufacture a one-transistor dynamic RAM.

In this embodiment, both insulating films on the gate electrodes 4a and 4b are etched to reduce the level difference and flatten. Therefore, the level difference is reduced as compared with the first embodiment, and the lower electrode 1 is formed.
2 can be performed more easily, and the interlayer thickness on the source diffusion layer 8a can be reduced (because there are few steps in the base).
The contact shape of the contact portion with the aluminum wiring 16 to be a bit line and the step coverage of the aluminum wiring 16 can be further improved.

[0020]

As described above, according to the present invention, the insulating film on the gate electrode provided for forming the self-aligned contact is formed after the self-aligned contact is formed, and a resist is applied to the insulating film on the gate electrode. Since the step is reduced and flattened by removing the portion by etching, lithography and etching in a later process can be easily performed, and there is an effect that the step coverage of the wiring can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view used for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view used for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 5 is a cross-sectional view used for explaining a conventional technique.

[Explanation of symbols]

1 P-type silicon substrate 2 field oxide film 3 gate oxide film 4a, 4b gate electrode 5 first silicon oxide film 6 N ^- -type diffusion layer 7 third silicon oxide film 8a N ⁺ -type source diffusion layer 8b N ⁺ -type drain Diffusion layer 9 Second silicon oxide film 10 First resist film 11a, 11b Second resist film 12 Lower electrode of capacitor 13 Capacitive insulating film 14 Upper electrode of capacitor 15 Interlayer insulating film 16 Aluminum wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/336 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 29/78

Claims (3)

(57) [Claims] 1. A gate electrode provided on a first conductivity type semiconductor substrate via a gate insulating film, a first insulating film covering the gate electrode, and a source diffusion layer and a drain self-aligned with the gate electrode. Diffusion layers are provided and M
A step of forming an IS transistor, a step of depositing a second insulating film, and a step of forming an opening from a region on the first insulating film of the MIS transistor to a region on the drain (or source) diffusion layer. Forming a resist film, etching using the first resist film as a mask until the drain (or source) diffusion layer is exposed to form a contact hole, and removing the first resist film. After applying a second resist film over the entire surface, performing an etch-back step to reduce the thickness of the second insulating film on at least the gate electrode to reduce the level difference, and removing the second resist film, A method for manufacturing a semiconductor device, comprising: a step of forming a conductive film in a contact hole portion and a periphery thereof. 2. The method according to claim 1, wherein the MIS transistor is an LDD transistor having a gate electrode and a spacer made of a third insulating film on a side surface of the first insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is a lower electrode of the stack capacitor, and a memory cell is formed by the MIS transistor and the stack capacitor.