JPH04361569A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve a wiring in step coverage by a method wherein an insulating film on a gate electrode is partially removed by etching after a self-aligned contact is formed. CONSTITUTION:When an insulating film is etched as far as 250nm through an anisotropical etching method, a drain diffusion layer 8b is exposed to form a contact self-aligned to gate electrodes 4a and 4b. Furthermore, a first resist film 10 is removed, and then a second resist film 11a is uniformly applied. In succession, all the surface is etched under such a condition that the second resist, film 11a, a first silicon oxide film 5, a second silicon oxide film 7, and a third silicon oxide film 9 are set equal in etching rate until an insulating film on the gate electrode 4b is rendered 200-300nm in thickness. Then, the second resist film is removed, and the lower electrode of a charge storage capacitor is formed. By this setup, the surface concerned is lessened in level difference, so that after processes such as a lithography process and an etching process can be easily carried out.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a dynamic RAM having a stacked capacitor in a memory cell.

0002

[Background Art] Semiconductor integrated circuits are becoming more highly integrated year by year, and in order to ensure a sufficiently large storage capacity, the capacitor portion of a dynamic RAM memory cell has changed from a planar structure to a three-dimensional structure, with a typical example being a stacked structure. There are memory cells that have type capacitors. Additionally, self-aligned contacts are used to reduce the contact margin.

A conventional method for manufacturing this type of semiconductor device will be explained with reference to FIG. First, P-type silicon substrate 1
After forming an element isolation region made of a field oxide film 2, forming a gate oxide film 3 in the transistor region, forming a first polycrystalline silicon on the entire surface, and further forming a first silicon oxide film 5, These are patterned simultaneously to form gate electrodes 4a and 4b which will become mutually adjacent word lines. Next, the gate electrode 4a, which becomes this word line,
Using 4b as a mask, N-type impurities are ion-implanted at a low dose to form a low-concentration N- type diffusion layer 6, and a third silicon oxide film is formed on the entire surface, followed by anisotropic etching. A spacer 7 is formed by this. Using the spacer 7, the gate electrode, and the first silicon oxide film as masks, N-type impurities are ion-implanted at a high dose. This forms N+ type source and drain diffusion layers 8a and 8b. Through the above steps, an LDD transistor is formed. Subsequently, a second silicon oxide film 9 is formed on the entire surface, and a contact hole is formed on the drain diffusion layer 8b so as to span the first silicon oxide film 5 of the gate electrodes 4a, 4b, thereby forming a self-aligned contact. Furthermore, a lower layer electrode 12 of a capacitor for charge storage is formed, a capacitive insulating film 13 is deposited on the lower layer electrode 12, and an upper layer electrode 14 of the capacitor is formed.

Finally, after depositing an interlayer insulating film 15 over the entire surface and forming an opening on the source diffusion layer 8a, a one-transistor dynamic RAM was obtained by patterning an aluminum wiring 16 that would become a bit line. .

[0005]

[Problems to be Solved by the Invention] The conventional semiconductor device manufacturing method described above includes a step of forming a self-aligned contact structure in which the contact on the drain diffusion layer is opened in a self-aligned manner with respect to the gate electrode. ing. There is a thick insulating film (oxide film) on this gate electrode, and there is a large step difference between the gate steps, so when etching is performed to form the capacitor electrode in the later process, etching remains are likely to be left along the side walls of the gate step. This has the drawback of making it difficult to form a bit line in the upper layer of the capacitor electrode and forming a bit line contact, resulting in poor step coverage.

[0006]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes: a gate electrode provided on a first conductive semiconductor substrate via a gate insulating film; a first insulating film covering the gate electrode; and a step of forming a MIS transistor by respectively providing a source diffusion layer and a drain diffusion layer self-aligned with the gate electrode, a step of depositing a second insulating film, and a step of depositing a second insulating film on the first insulating film of the MIS transistor. forming a first resist film having an opening from a region above the drain (or source) diffusion layer, and using the first resist film as a mask until the drain (or source) diffusion layer is exposed; forming a contact hole by etching, and after removing the first resist film, applying a second resist film to the entire surface and performing etch back to thin the second insulating film at least on the gate electrode. and a step of forming a conductive film in and around the contact hole after removing the second resist film.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

1(a), (b) and FIG. 2(a), (
b) is a step-by-step sectional view for explaining the first embodiment of the present invention.

First, as shown in FIG. 1(a), a layer of 600 to 70 mm thick is deposited on a P-type silicon substrate 1 in the same manner as in the conventional example.
A field oxide film 2 with a thickness of 0 nm is selectively formed, a gate oxide film 3 is formed on the divided device region, a polycrystalline silicon film with a thickness of 300 to 400 nm is formed on the entire surface, and a polycrystalline silicon film with a thickness of 300 nm is further formed on the entire surface. After forming, for example, a first silicon oxide film 5 as a first insulating film with a thickness of ~400 nm, these are simultaneously patterned to form gate electrodes 4a, which will become word lines.
Form 4b. Next, using the gate electrode 4 as a mask, N
A type impurity is ion-implanted at a low dose to form an N- type diffusion layer 6, a third insulating film (third silicon oxide film) with a thickness of 200 nm is formed on the entire surface, and this is anisotropically etched. By doing so, spacers 7 are formed on the gate electrode and the sidewalls of the first silicon oxide film. Using this spacer 7, the gate electrode and the first silicon oxide film as a mask, N
Type impurities are ion-implanted at a high dose to form an N+ type source diffusion layer 8a and drain diffusion layer 8b. Subsequently, a second insulating film (second silicon oxide film) with a thickness of 200 nm is formed over the entire surface. At this time, a second silicon oxide film 9 of 200 nm is also formed on the source diffusion layer 8a and drain diffusion layer 8b. Subsequently, a resist is applied to form a first resist film that covers both ends of the gate electrodes 4a, 4b and is patterned so as to have an opening above the drain diffusion layer 8b.

Next, as shown in FIG. 1(b), when the insulating film is etched by about 250 nm by anisotropic dry etching, the drain diffusion layer 8b is exposed and the gate electrodes 4a, 4b are etched.
A self-aligned contact is formed. Furthermore, after removing the first resist film 10, a second resist film 11a is uniformly applied.

Next, as shown in FIG. 2(a), under the conditions that the second resist film 11a and the first, second, and third silicon oxide films 5, 7, and 9 have the same etching rate, The thickness of the insulating film on the gate electrode 4b is 200 to 30 mm.
The entire surface is etched to a thickness of 0 nm.

Next, as shown in FIG. 2(b), the second resist film is removed, the lower electrode 12 of the charge storage capacitor is formed as in the conventional method, and the capacitive insulating film 13 is placed on the lower electrode 12. to form the upper layer electrode 14. lastly,
After depositing an interlayer insulating film 15 on the entire surface and forming an opening on the source diffusion layer 8a, an aluminum wiring 1 that will become a bit line is formed.
6, a one-transistor type dynamic RAM is manufactured.

[0013] In this way, since the capacitor is formed after reducing the step difference in the gate step by etching back, the lithography and etching in the subsequent steps are facilitated, and the step coverage of the wiring is improved.

Next, a second embodiment of the present invention will be described.

First, as in the first embodiment, a self-aligned contact is formed on the drain diffusion layer.

Next, as shown in FIG. 3(a), a second resist film 11b is applied. However, a highly viscous coating liquid should be used, and the shape should reflect the underlying shape.

Next, as shown in FIG. 3(b), the second resist film 11b, the first silicon oxide film 5, the third silicon oxide film 7, and the second silicon oxide film 9 are each etched at the same etching rate. 4a, 4 on the gate electrode under the condition that
The entire surface of the first silicon oxide film 7 on b is etched until only 200 to 300 nm remains, thereby reducing steps and flattening the surface.

Thereafter, the second resist film 11b is removed and a one-transistor type dynamic RAM is manufactured by forming up to the aluminum wiring 16 in the same manner as in the first embodiment.

In this embodiment, both the insulating films on the gate electrodes 4a and 4b are etched to reduce the level difference and flatten it, so the level difference is smaller than in the first embodiment, and the lower electrode 1
The etching step 2 can be performed more easily, and the interlayer film thickness on the source diffusion layer 8a can be made thinner (because there are fewer steps in the underlying layer).
The contact shape of the contact portion between the aluminum wire 16 and the aluminum wire 16 that becomes the bit line and the step coverage of the aluminum wire 16 can be made even better.

[0020]

Effects of the Invention As explained above, in the present invention, after forming a self-aligned contact, the insulating film on the gate electrode provided for forming a self-aligned contact is coated with a resist to form a part of the insulating film on the gate electrode. By removing the portion by etching, the difference in level is reduced and the surface is flattened, so that the subsequent lithography and etching can be easily performed, and the step coverage of the wiring can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view used to explain a first embodiment of the present invention.

FIG. 2 is a sectional view used to explain the first embodiment of the present invention.

FIG. 3 is a sectional view used to explain a second embodiment of the present invention.

FIG. 4 is a sectional view used to explain a second embodiment of the present invention.

FIG. 5 is a cross-sectional view used to explain the conventional technology.

[Explanation of symbols]

1 P type silicon substrate 2 Field oxide film 3 Gate oxide films 4a, 4b Gate electrode 5 First silicon oxide film 6 N- type diffusion layer 7 Third silicon oxide film 8a N+ type source diffusion layer 8b N+ type drain diffusion layer 9 Second silicon oxide film 10 First resist film 11a, 11b Second resist film 12
Capacitor lower electrode 13 Capacitive insulating film 14 Capacitor upper electrode 15 Interlayer insulating film 16 Aluminum wiring

Claims (3)

[Claims] 1. A gate electrode provided on a first conductivity type semiconductor substrate via a gate insulating film, a first insulating film covering the gate electrode, and a source diffusion layer and a drain self-aligned with the gate electrode. a step of forming a MIS transistor by respectively providing diffusion layers; a step of depositing a second insulating film; and a step of forming a MIS transistor from a region on the first insulating film to a region on the drain (or source) diffusion layer of the MIS transistor. a step of forming a first resist film having an opening throughout the process; a step of etching using the first resist film as a mask until the drain (or source) diffusion layer is exposed to form a contact hole; a step of removing the resist film, applying a second resist film to the entire surface, and performing etchback to thin the second insulating film at least on the gate electrode to reduce the step difference; A method for manufacturing a semiconductor device, comprising the step of forming a conductive film in and around the contact hole after removing the film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the MIS transistor is an LDD transistor having a gate electrode and a spacer made of a third insulating film on the side surface of the first insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is a lower electrode of a stacked capacitor, and the MIS transistor and the stacked capacitor constitute a memory cell.