KR0156099B1 - Semiconductor memory and manufacture thereof - Google Patents
Semiconductor memory and manufacture thereofInfo
- Publication number
- KR0156099B1 KR0156099B1 KR1019890005668A KR890005668A KR0156099B1 KR 0156099 B1 KR0156099 B1 KR 0156099B1 KR 1019890005668 A KR1019890005668 A KR 1019890005668A KR 890005668 A KR890005668 A KR 890005668A KR 0156099 B1 KR0156099 B1 KR 0156099B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- type impurity
- impurity region
- conductor layer
- contact hole
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Abstract
내용 없음.No content.
Description
제1도는 종래의 다이나믹 램 셀의 단면구조도.1 is a cross-sectional view of a conventional dynamic ram cell.
제2도는 본 발명의 다이나믹 램 셀의 단면구조.2 is a cross-sectional structure of the dynamic ram cell of the present invention.
제3도 (a)-(h)는 제2도에 도시된 본 발명의 다이나믹 램 셀의 제조공정도.3 (a)-(h) are manufacturing process diagrams of the dynamic ram cell of the present invention shown in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 게이트 산화막 24: 게이트 전극23: gate oxide film 24: gate electrode
25, 31 : 사이드웰 26 : N+형 불순물영역25, 31: Sidewell 26: N + type impurity region
27, 30, 36 : 절연막 37 : BPSG막27, 30, 36: insulating film 37: BPSG film
28, 32,39 : 콘택홀 29 : 전도체층28, 32, 39: contact hole 29: conductor layer
33 : 스토리지노드용 폴리실리콘막 34 : 유전체막33: polysilicon film for storage node 34: dielectric film
35 : 플레이트 노드용 폴리실리콘막 38 : 포토레지스트막35 polysilicon film for plate node 38 photoresist film
40 : 비트라인요 금속40: bitline metal
본 발명은 다이나믹 램 셀(Dynamic RAM cell)에 관한 것으로서, 4메가 비트(Mega bit) 이상이 초고집적 다이나믹 램에 요구되는 커다란 커패시턴스와 양호한 메탈 스텝 커버리지(Metal step coverage)를 얻는데 적당한 다이나믹 램 셀 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM cell, wherein more than 4 mega bits are suitable for obtaining large capacitance and good metal step coverage required for ultra-high density dynamic RAM. It relates to a manufacturing method thereof.
제1도는 종래의 다이나믹 램 셀의 단면구조를 도시한 것이다.1 shows a cross-sectional structure of a conventional dynamic ram cell.
제1도를 참조하면, 필드영역에 해당하는 반도체 기판(1)상에 필드산화막(2)이 형성되고, 액티브 영역에 해당하는 반도체 기판(1) 및 필드산화막(2) 상에 게이트 산화막(3)과 게이트 전극(4)이 형성되며, 게이트 전극(4)의 양측 면에는 사이드웰(side wail)(6)이 형성되고, 게이트 전극(4)의 양측 반도체 기판(1)내에는 소오스/드레인용 N+형 불순물영역(5)이 형성되어 종래의 다이나믹 램 셀의 트랜지스터를 형성한다.Referring to FIG. 1, a field oxide film 2 is formed on a semiconductor substrate 1 corresponding to a field region, and a gate oxide film 3 is formed on a semiconductor substrate 1 and a field oxide film 2 corresponding to an active region. ) And a gate electrode 4, sidewalls 6 are formed on both sides of the gate electrode 4, and source / drain is formed in both semiconductor substrates 1 of the gate electrode 4. A citation N + type impurity region 5 is formed to form a transistor of a conventional dynamic RAM cell.
N+형 불순물영역(5)을 제외한 기판전면에 유전체층으로 된 절연막(7)이 형성되고, 이웃하는 게이트 전극(4) 사이의 N+형 불순물영역(5)과 콘택홀(14)을 통해 접촉되도록 이웃하는 게이트 전극(4) 사이의 절연막(7)상에 스토리지노드용 폴리실리몬칵(8)이 형성되며, 노출된 스토리지노드용 플리실리콘막(8)상에 유전체막(9)이 형성되고, 그 위에 플레이트 노드용 폴리실리콘막(10)이 형성되어 종래의 다이나믹 램 셀의 캐패시터가 형성된다.N + type impurity region 5, an insulating film (7) with a dielectric layer over the entire surface of the substrate excluding is formed, and contact with the N + type impurity region 5 and the contact holes 14 between adjacent gate electrodes 4 to The polysilicon cock 8 for the storage node is formed on the insulating film 7 between neighboring gate electrodes 4, and the dielectric film 9 is formed on the exposed storage node polysilicon film 8. The polysilicon film 10 for the plate node is formed thereon to form a capacitor of a conventional dynamic RAM cell.
플레이트 노드용 폴리실리콘막(10)상에 유전체층으로 저온산화막(LTO, Low Temperature Oxide)(11)이 형성되고, N+형 불순물영역(5)을 제외한 기판 전면에 유전체층을 BPSG(Boron-Phosphorous Silica Glass)막(12)이 형성되며, 콘택홀(15)을 통해 N+형 불순물영역(5)과 접촉되도록 BPSG막(12)상에 비트라인용 메탈(13)이 형성된다.Low Temperature Oxide (LTO) 11 is formed as a dielectric layer on the polysilicon layer 10 for the plate node, and a BPSG (Boron-Phosphorous Silica) is formed on the entire surface of the substrate except for the N + type impurity region (5). A glass film 12 is formed, and a bit line metal 13 is formed on the BPSG film 12 so as to contact the N + type impurity region 5 through the contact hole 15.
이로써, 종래의 다이나믹 램 셀이 얻어진다.As a result, a conventional dynamic ram cell is obtained.
종래의 다이나믹 램 셀은 충분한 정전용량(Capacitance)을 확보하기 위하여 적층 캐패시터 셀 구조(Stacked Capacitor Cell Structure)를 채택하였는데, 이러한 다이나믹 램 셀은 정해진 작은 셀 면적 내에서 충분히 커다란 정전용량을 얻는데는 한계성이 발생되고, 또한 큰 단차에 의해서 비트라인용 메탈의 스텝 커버리지 값도 현저하게 작아지는 문제점이 있었다.Conventional dynamic ram cells employ a stacked capacitor cell structure to ensure sufficient capacitance. Such dynamic ram cells have limitations in obtaining sufficiently large capacitance within a given small cell area. There was a problem that the step coverage value of the bit line metal was also significantly reduced due to the large step.
본 발명은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 충분한 커다란 정전용량을 얻으며, 양호한 메탈 스탭커버리지를 얻을 수 있는 다이나믹 램 셀 및 그의 제조방법을 제공하는데 그 목적 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a dynamic ram cell and a method of manufacturing the same, which can obtain a sufficiently large capacitance and obtain good metal step coverage.
이하 본 발명의 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 실시예에 따른 다이나믹 램 셀의 단면구조를 도시한 것이다.2 shows a cross-sectional structure of a dynamic RAM cell according to an embodiment of the present invention.
제2도를 참조하면, 필드영역에 해당하는 반도체 기판(21)상에 필드산화막(22)이 형성되고, 필드산화막(22)과 액티브영역에 해당하는 반도체 기판(21)상에 게이트 산화막(23), 게이트 전극(24) 및 사이드웰(25)이 형성되며, 상기 N+형 불순물영역(26)을 제외한 기판전면에 절연막(27)이 형성되어 본 발명의 다이나믹 램 셀의 트랜지스터를 형성한다.Referring to FIG. 2, a field oxide film 22 is formed on a semiconductor substrate 21 corresponding to a field region, and a gate oxide film 23 is formed on a semiconductor substrate 21 corresponding to a field oxide film 22 and an active region. ), A gate electrode 24 and a side well 25 are formed, and an insulating film 27 is formed on the entire surface of the substrate except for the N + type impurity region 26 to form a transistor of the dynamic RAM cell of the present invention.
콘택홀(28)을 통해 N+형 불순물영역(26)과 접촉되도록 이웃하는 게이트 전극(24)상의 절연막(27) 사이에 전도체층(29)이 형성되고, 전도체층(29)의 양단부에 절연막(30)이 형성되고, 그의 측면에 사이드웰(31)이 형성되며, 콘택홀(32)이 통해 N+형 불순물영역(26)과 접촉되도록 이웃하는 게이트 전극(24)상의 절연막(27(30) 사이에 걸쳐 스토리지노드용 폴리실리콘막(33)이 형성되고, 스토리지노드용 폴리실리콘막(33)상에 유전체막(34)이 형성되며, 전도체층(29)의 상부를 제외한 기판전면에 플레이트 노드용 실리콘막(35), 절연막(36) 및 BPSG막(37)이 순차 형성되어 본 발명의 다이나믹 램 셀의 캐패시터가 형성된다.The conductor layer 29 is formed between the insulating film 27 on the neighboring gate electrode 24 so as to contact the N + type impurity region 26 through the contact hole 28, and the insulating film is formed at both ends of the conductive layer 29. 30 is formed, and side wells 31 are formed on the side surfaces thereof, and insulating films 27 (30) on neighboring gate electrodes 24 are brought into contact with the N + -type impurity regions 26 through the contact holes 32. The polysilicon film 33 for the storage node is formed between the layers, and the dielectric film 34 is formed on the polysilicon film 33 for the storage node, and the plate is formed on the entire surface of the substrate except for the upper portion of the conductor layer 29. The node silicon film 35, the insulating film 36, and the BPSG film 37 are sequentially formed to form a capacitor of the dynamic RAM cell of the present invention.
콘택홀(39)을 통해 전도체층(29)과 접촉되도록 비트라인용 금속(40)이 BPSG막(37)상에 형성되고 이로써 제2도에 도시된 바와 같은 본 발명의 다이나믹 램 셀이 얻어진다.A bit line metal 40 is formed on the BPSG film 37 so as to be in contact with the conductor layer 29 through the contact hole 39, thereby obtaining the dynamic RAM cell of the present invention as shown in FIG. .
제3도 (a)-(h)는 제2도에 도시된 본 발명의 다이나믹 램 셀의 제조공정도이다.3 (a)-(h) are manufacturing process diagrams of the dynamic ram cell of the present invention shown in FIG.
제3도 (a)를 참조하면, 필드영역에 해당하는 P형 반도체 기판(21)상에 필드산화고정을 수행하여 필드산화막(22)을 형성하고, 필드산화막(22)과 액티브영역에 해당하는 반도체 기판(21)상에 게이트 산화막(23), 게이트 전극(24) 및 게이트 전극(24)의 측면에 사이드웰(25)을 형성하여, 게이트 전극(24)을 마스크로 하여 n형 불순물을 이온주입하여 소오스/드레인용 N+형 불순물영역(26)을 형성한다.Referring to FIG. 3A, field oxide film 22 is formed on the P-type semiconductor substrate 21 corresponding to the field region to form the field oxide film 22, and the field oxide film 22 and the active region correspond to the field oxide film 22. Side wells 25 are formed on the semiconductor substrate 21 on the side surfaces of the gate oxide film 23, the gate electrode 24, and the gate electrode 24, and the n-type impurities are ionized using the gate electrode 24 as a mask. Implantation to form an N + type impurity region 26 for source / drain.
이로써 본 발명의 다이나믹 램 셀의 트랜지스터가 형성된다.As a result, the transistor of the dynamic RAM cell of the present invention is formed.
제3도 (b)를 참조하면, 기판전면에 유전체층으로 된 절연막(27)을 전면도포하고, 식각하여 콘택홀(28)을 형성하고 N+형 불순물영역(26)을 노출시킨다.Referring to FIG. 3B, an insulating film 27 made of a dielectric layer is coated on the entire surface of the substrate and etched to form a contact hole 28 to expose the N + type impurity region 26.
이어서, 기판전면에 플리사이드로 된 전도체층(29)과 유전체층으로 된 절연막(30)을 도포한다.Subsequently, a conductive layer 29 made of a pleside and an insulating film 30 made of a dielectric layer are applied to the entire surface of the substrate.
제3도(c)를 참조하면, 전도체층(29)과 절연막(30)을 식각하여 콘택홀(28)을 통해서 전도체층(29)이 N+형 불순물영역(26)과 접촉하도록 이웃하는 게이트 전극(24) 사이의 절연막(27) 상에만 남겨둔다.Referring to FIG. 3C, a gate adjacent to the conductor layer 29 and the N + type impurity region 26 is etched through the contact hole 28 by etching the conductor layer 29 and the insulating layer 30. Only the insulating film 27 between the electrodes 24 is left.
그리고, 전도체층(29)의 양측에 사이드웰(31)을 형성한다.The side wells 31 are formed on both sides of the conductor layer 29.
제3도(d)를 참조하면, 콘택홀(28)이 형성된 N+형 불순물영역(26)의 양쪽에 형성된 N+형 불순물영역(26)상의 절연막(27)을 제거하여 콘택홀(32)을 형성하고, N+형 불순물영역(26)을 노출시킨다.Third Degree (d) When the reference, the contact hole 28 is formed N + type by removing the insulating film 27, contact holes 32 on the N + type impurity region 26 formed on both sides of the impurity region 26 a Is formed and the N + -type impurity region 26 is exposed.
이어서, 기판전면에 스토리지노드용 폴리실리콘막(33)을 기판전면에 증착한다.Next, a polysilicon film 33 for a storage node is deposited on the entire surface of the substrate.
제3도(e)를 참조하면, 스토리지노드용 폴리실리콘막(33)을 식각하여 콘택홀(32)을 통해 N+형 불순물영역(26)과 접촉되도록 이웃하는 게이트 전극(24)상의 절연층(27(30) 사이에 걸쳐 남겨둔다.Referring to FIG. 3E, the insulating layer on the neighboring gate electrode 24 is etched to contact the N + type impurity region 26 through the contact hole 32 by etching the polysilicon layer 33 for the storage node. (Leave over 27 (30).
노출된 스토리지노드용 폴리실리콘막(33)상에 유전체막(34)을 형성하고, 기판전면에 플레이트 노드용 폴리실리콘막(35)과 유전체층으로 된 절연막(36)을 증착한다.The dielectric film 34 is formed on the exposed polysilicon film 33 for the storage node, and the polysilicon film 35 and the insulating film 36 made of the dielectric layer are deposited on the entire surface of the substrate.
제3도(f)를 참조하면, 플레이트 노드용 폴리실리콘막(35)과 절연막(36)을 식각하여 상기 전도체층(29)상의 절연막(30)을 노출시킨다.Referring to FIG. 3F, the polysilicon layer 35 and the insulating layer 36 for the plate node are etched to expose the insulating layer 30 on the conductor layer 29.
이로써 본 발명의 다이나믹 램 셀의 개패시터가 형성된다.This forms the capacitor of the dynamic ram cell of the present invention.
제3도(g)를 참조하면, 기판전면에 걸쳐 유전체층으로 BPSG막(37)을 전면도포하고, 그 위에 프토레지스트막(38)을 도포한다.Referring to FIG. 3 (g), the BPSG film 37 is coated over the entire surface of the substrate with a dielectric layer, and a ptoresist film 38 is applied thereon.
포토레지스트막(38)을 사진식각하여 전도체층(29)상의 BPSG막(37)을 노출시킨다.The photoresist film 38 is etched to expose the BPSG film 37 on the conductor layer 29.
제3도(h)를 참조하면, 상기 포토레지스트막(38)을 마스크로 전도체층(29)상의 노출된 BPSG막(37)과 절연막(36)을 식각하여 콘택홀(39)을 형성한다.Referring to FIG. 3 (h), the contact hole 39 is formed by etching the exposed BPSG film 37 and the insulating film 36 on the conductor layer 29 using the photoresist film 38 as a mask.
포토레지스트막(38)을 제거한 후 콘택홀(39)을 통해 전도층(29)과 접촉되도록 비트라인용 금속(40)을 BPSG막(37)상에 형성한다.After removing the photoresist film 38, the bit line metal 40 is formed on the BPSG film 37 to be in contact with the conductive layer 29 through the contact hole 39.
비트라인용 금속(40)은 전도체층(29)을 통해 N+형 불순물영역(26)과 전기적으로 접촉한다.The bit line metal 40 is in electrical contact with the N + type impurity region 26 through the conductor layer 29.
이로써, 최종적인 본 발명의 다이나믹 램 셀이 얻어진다.Thus, the final dynamic ram cell of the present invention is obtained.
상기한 바와 같은 본 발명에 의하면, 비트라인용 금속과 N+형 불순물영역 사이에 폴리사이드로 된 전도체층을 형성하여 줌으로서 캐패시터의 유전체막의 면적을 증가시켜 주고, 비트라인용 금속이 N+형 불순물영역과 직접 접촉될 때보다 접촉면적을 증가시켜 준다.According to the present invention as described above, the area of the dielectric film of the capacitor is increased by forming a conductor layer made of polyside between the bit line metal and the N + type impurity region, and the bit line metal is N + type. It increases the contact area than when directly in contact with the impurity region.
따라서 본 발명의 다이나믹 램 셀의 캐패시터의 정전용량을 증대시키고 전도체층에 이한 금속의 접촉면적 증가로 인하여 접촉저항을 감소시키며, 스탭커버리지를 향상시킬 수 있는 효과가 있다.Therefore, the capacitance of the capacitor of the dynamic ram cell of the present invention is increased, the contact resistance is reduced due to the increase in the contact area of the metal following the conductor layer, and the step coverage can be improved.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890005668A KR0156099B1 (en) | 1989-04-28 | 1989-04-28 | Semiconductor memory and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890005668A KR0156099B1 (en) | 1989-04-28 | 1989-04-28 | Semiconductor memory and manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900017089A KR900017089A (en) | 1990-11-15 |
KR0156099B1 true KR0156099B1 (en) | 1998-10-15 |
Family
ID=19285706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890005668A KR0156099B1 (en) | 1989-04-28 | 1989-04-28 | Semiconductor memory and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0156099B1 (en) |
-
1989
- 1989-04-28 KR KR1019890005668A patent/KR0156099B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR900017089A (en) | 1990-11-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR900000207B1 (en) | Semiconductor memory device with trench surrounding each memory cell | |
KR930002292B1 (en) | Semiconductor device and method for manufacturing thereof | |
KR0135067B1 (en) | Device & cell manufacturing of semiconductor device | |
KR970000977B1 (en) | Capacitor producing method of semiconductor device | |
JPS6156445A (en) | Semiconductor device | |
KR0156099B1 (en) | Semiconductor memory and manufacture thereof | |
US5773310A (en) | Method for fabricating a MOS transistor | |
JPH0319362A (en) | Semiconductor memory and manufacture thereof | |
KR100623321B1 (en) | Method for manufacturing a semiconductor device haved pattern for measuring contact resistor | |
KR100195837B1 (en) | Micro contact forming method of semiconductor device | |
KR0156107B1 (en) | Method of fabricating memory cell capacitors | |
KR970010681B1 (en) | Method of manufacturing a storage node | |
KR100541697B1 (en) | DRAM cell transistor manufacturing method | |
KR100244403B1 (en) | Sram and manufacturing method thereof | |
KR100218735B1 (en) | Forming method for contact hole of semiconductor device | |
KR100321146B1 (en) | SRAM device and method for manufacturing the same | |
KR0172812B1 (en) | Structure of memory device | |
KR100215862B1 (en) | Capacitor of semiconductor device and its fabrication method | |
KR0126114B1 (en) | The manufacturing method for semiconductor memory device | |
KR100223895B1 (en) | Dram cell and manufacturing method thereof | |
KR940011806B1 (en) | Dram cell and fabricating method thereof | |
KR0144175B1 (en) | Semiconductor Memory Device Manufacturing Method | |
KR100454631B1 (en) | Manufacturing method of storage electrode of semiconductor device | |
KR100232205B1 (en) | Semiconductor memory and its fabrication method | |
KR0156097B1 (en) | Semiconductor memory and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20070622 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |