KR0156097B1 - Semiconductor memory and manufacture thereof - Google Patents

Semiconductor memory and manufacture thereof

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Publication number
KR0156097B1
KR0156097B1 KR1019890009033A KR890009033A KR0156097B1 KR 0156097 B1 KR0156097 B1 KR 0156097B1 KR 1019890009033 A KR1019890009033 A KR 1019890009033A KR 890009033 A KR890009033 A KR 890009033A KR 0156097 B1 KR0156097 B1 KR 0156097B1
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South Korea
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forming
plate
region
insulating film
storage node
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KR1019890009033A
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Korean (ko)
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KR910001764A (en
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김준기
금은섭
김동원
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

본 발명은 메모리소자에 관한 것으로, 특히 4 메카 비트(4 Mega bit)급 이상의 초고집적 디램셀(Dynamic RAM Cell)에 요구되는 커패시터용량을 얻는데 적당하도록한 디램셀의 제조방법 및 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a manufacturing method and a structure of a DRAM cell suitable for obtaining a capacitor capacity required for an ultra high-density DRAM cell of 4 mega bits or more.

이와같은 본 발명의 디램셀 제조방법은 필드영역과 액팁브영역기 정의된 반도체 기판에 게이트절연막과 게이트전극을 형성하는 공정과, 상기 게이트전극 양측 기판에 소오스 및 드레인 영역을 형성하고 게이트전극 측면에 절연막을 측벽을 형성하는 공정과, 전면에 절연막을 증착하고 커패시터 형성영역의 절연막 상에 선택적으로 제1플레이트와 제1유전체막을 형성하는 공정과, 상기 소오스 영역에 스토리지노드콘택을 형성하고 스토리지노드를 형성하는 공정과, 상기 스토리지노드 표면에 제2유전체막을 형성하고 제1플레이트와 연결되도록 제2플레이트를 형성하는 공정으로 이루어 지고, 본 발명의 디램셀 구조는 필드산화막이 형성된 반도체 기판; 상기 기판에 게이트와 소오스 및 드레인영역 구비하여 형성되는 트랜지스터; 상기 소오스영역상에 콘택홀을 갖고 전면에 형성되는 절연막; 상기 콘택홀 양측 커패시터 영역의 절연막상에 형성되는 제1플레이트; 상기 제1플레이트표면에 형성되는 제1유전체막; 상기 콘택홀을 통해 소오스영역과 연결되도록 제1유전체막과 절연막상에 형성되는 스토리지 노드; 상기 스토리지 노드 표면에 형성되는 제2유전체막; 상기 제1플레이트와 연결되도록 제2유전체막위에 형성되는 제2플레이트를 포함하여 구성된다.The DRAM cell manufacturing method of the present invention comprises the steps of forming a gate insulating film and a gate electrode on a semiconductor substrate having a field region and an actuator region defined therein, forming a source and a drain region on both sides of the gate electrode, Forming a sidewall of the insulating film, depositing an insulating film on the entire surface, and selectively forming a first plate and a first dielectric film on the insulating film of the capacitor formation region, forming a storage node contact in the source region, and forming a storage node. And forming a second dielectric film on the surface of the storage node and forming a second plate to be connected to the first plate. The DRAM cell structure of the present invention includes a semiconductor substrate having a field oxide film; A transistor including a gate, a source, and a drain region in the substrate; An insulating film formed on an entire surface with a contact hole on the source region; A first plate formed on an insulating film in both capacitor regions of the contact hole; A first dielectric film formed on the surface of the first plate; A storage node formed on the first dielectric layer and the insulating layer to be connected to the source region through the contact hole; A second dielectric layer formed on a surface of the storage node; And a second plate formed on the second dielectric film so as to be connected to the first plate.

Description

디램셀의 제조방법 및 구조Manufacturing method and structure of DRAM cell

제1도는 종래의 디램셀 공정단면도.1 is a cross-sectional view of a conventional DRAM cell process.

제2도는 종래의 디램 단위셀 회로도.2 is a circuit diagram of a conventional DRAM unit cell.

제3도는 본 발명의 디램셀 공정단면도.3 is a cross-sectional view of the DRAM cell process of the present invention.

제4도는 본 발명의 디램 단위셀 회로도.4 is a DRAM unit cell circuit diagram of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 기판 2 : 게이트1 substrate 2 gate

3 : 절연막 측벽 4 : 소오스 및 드레인3: insulating film side wall 4: source and drain

5 : 필드산화막 6, 6a : LTO5: field oxide film 6, 6a: LTO

7 : 콘택 8, 8a, 8b : 폴리실리콘7: contact 8, 8a, 8b: polysilicon

9, 9a : 유전체막 10 : BPSG9, 9a: dielectric film 10: BPSG

11 : 메탈11: metal

본 발명은 메모리소자에 관한 것으로,특히 4메가 비트(4 Mega bit)급 이상의 초고집적 디램셀(Dynamic RAM Cell)에 요구되는 커패시터용량을 얻는데 적당하도록 한 디램셀의 제조방법 및 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a method and a structure for fabricating a DRAM cell suitable for obtaining a capacitor capacity required for an ultra-high density DRAM cell of 4 Mega bits or more.

종래의 디램셀 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다. 제1도는 종래의 디램셀 공정단면도로서, 제1도(a)와같이 기판(1)에 필드영역과 액티브영역을 정의하여 필드영역에 필드산화막(5)을 형성하고 액트브영역에 게이트절연막을 형성한 다음, 일정한 간격으로 게이트(2)를 형성한다. 그리고 게이트(2)를 마스크로 이용한 고농도 n형 이온주입하여 소오스 및 드레인영역(4)을 형성하고 게이트(2)측면에 절연막 측벽(3)을 형성한다.Referring to the conventional DRAM cell manufacturing method with reference to the accompanying drawings as follows. FIG. 1 is a cross-sectional view of a conventional DRAM cell process. As shown in FIG. 1A, a field region and an active region are defined in a substrate 1 to form a field oxide film 5 in a field region, and a gate insulating film is formed in an actuated region. After the formation, the gate 2 is formed at regular intervals. The source and drain regions 4 are formed by implanting high concentration n-type ions using the gate 2 as a mask, and the insulating film sidewall 3 is formed on the gate 2 side.

제1도(b)와같이 전면에 LTO(Low Temperature Oxidation)(6)를 증착하고 제1도(c)와같이 소오스영역상측의 LTO(6)를 선택적으로 제거하여 커패시터 스토리지노드(Storage node) 콘택(Contact)(7)을 형성한다.As shown in FIG. 1 (b), a low temperature oxidation (LTO) 6 is deposited on the front surface and the capacitor storage node is selectively removed by selectively removing the LTO 6 on the source region as shown in FIG. 1 (c). A contact 7 is formed.

제1도(d)와같이 전면에 스토리지노드로 사용할 폴리실리콘(8)을 증착하고 커패시터 영역을 정의하여 불필요한 부분의 폴리실리콘(8)을 선택적으로 제거한후 제1도(e)와 같이 유전체막(9)을 증착한다.As shown in FIG. 1 (d), polysilicon 8 is deposited on the front surface to be used as a storage node, and a capacitor region is defined to selectively remove unnecessary portions of polysilicon 8, followed by dielectric film as shown in FIG. (9) is deposited.

제1도(f)와같이 유전체막(9)위에 커패시터 플레이트(Plate)용 폴리실리콘(8a)을 형성하고 전면에 LTO(6a)를 증착한후 커패시터영역을 정의하여 불필요한 폴리실리콘(8a)과 LTO(6a)를 선택적으로 제거한다.As shown in FIG. 1 (f), the polysilicon 8a for the capacitor plate is formed on the dielectric film 9, the LTO 6a is deposited on the front surface, and the capacitor region is defined to define the unnecessary polysilicon 8a and The LTO 6a is selectively removed.

제1도(g)와같이 전면에 BPSG(Boron Phosphorous Silicate Glass)(10)를 증착하고 상기 드레인영역 상측의 LTO(6) 및 BPSG(8a)를 선택적으로 제거하여 비트라인(bit line) 콘택을 형성한 다음, 제1도(h)와같이 비트라인 메탈(11)을 형성한다.As shown in FIG. 1 (g), a BPSG (Boron Phosphorous Silicate Glass) 10 is deposited on the entire surface, and the bit line contact is selectively removed by selectively removing the LTO 6 and BPSG 8a on the drain region. After forming, the bit line metal 11 is formed as shown in FIG. 1 (h).

이와같이 형성한 디램셀은 제2도와같은 회로구성을 갖는다.The DRAM cell thus formed has a circuit configuration as shown in FIG.

그러나 이와같은 종래의 디램셀 제조방법에 있어서는 커패시터의 면적이 좁아서 4메가 이상의 초고집적 디램셀에 있어서는 충분한 정전용량을 확보하기가 어려운 문제점이 있었다.However, such a conventional DRAM cell manufacturing method has a problem that it is difficult to secure sufficient capacitance in an ultra-high density DRAM cell of 4 mega or more due to the narrow capacitor area.

본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로 같은 면적에서 커패시터의 면적을 증가시키는데 그 목적이 있다.The present invention has been made to solve such a problem, and its object is to increase the area of a capacitor in the same area.

이와같은 목적 달성하기 위한 본 발명의 디램셀 제조방법은 필드영역과 액팁브영역이 정의된 반도체 기판에 게이트절연막과 게이트전극을 형성하는 공정과, 상기 게이트전극 양측 기판에 소오스 및 드레인 영역 형성하고 게이트전극 측면에 절연막 측벽을 형성하는 공정과, 전면에 절연막을 증착하고 커패시터 형성영역의 절연막 상에 선택적으로 제1플레이트와 제1유전체막을 형성하는 공정과, 상기 소오스 영역에 스토리지노드 콘택을 형성하고 스토리지노드를 형성하는 공정과, 상기 스토리지노드 표면에 제2유전체막을 형성하고 제1플레이트와 연결되도록 제2플레이트를 형성하는 공정을 포함하여 이우러지고, 본 발명의 디램셀 구조는 필드산화막이 형성된 반도체 기판; 상기 기판에 게이트와 소오스 및 드레인영역을 구비하여 형성되는 트랜지스터; 상기 소오스영역상에 콘택홀을 갖고 전면에 형성되는 절연막; 상기 콘택을 양측 커패시터 영역의 절연막상에 형성되는 제1플레이트; 상기 제1플레이트포면에 형성되는 제1유전체막; 상기 콘텍홀을 통해 소오스영역과 연결되도록 제1유전체막과 절연막에 형성되는 스토리지노드; 상기 스토리지 노드 표면에 형성되는 제2유전체막; 상기 제1플레이트와 연결되도록 제2유전체막위에 형성되는 제2플레이트를 포함하여 이루어짐에 그 특징이 있다.The DRAM cell manufacturing method of the present invention for achieving the above object is a process of forming a gate insulating film and a gate electrode on a semiconductor substrate having a field region and an access region defined, the source and drain regions formed on both substrates of the gate electrode and the gate Forming an insulating film sidewall on an electrode side, depositing an insulating film on the entire surface, and selectively forming a first plate and a first dielectric film on the insulating film of the capacitor forming region, forming a storage node contact in the source region, and storing And forming a second dielectric film on the surface of the storage node and forming a second plate to be connected to the first plate. The DRAM cell structure of the present invention is a semiconductor having a field oxide film formed thereon. Board; A transistor including a gate, a source, and a drain region in the substrate; An insulating film formed on an entire surface with a contact hole on the source region; A first plate formed on the insulating film in both capacitor regions; A first dielectric film formed on the first plate cloth surface; A storage node formed on the first dielectric layer and the insulating layer to be connected to the source region through the contact hole; A second dielectric layer formed on a surface of the storage node; It is characterized in that it comprises a second plate formed on the second dielectric film to be connected to the first plate.

상기와 같은 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Referring to the present invention as described above in more detail with reference to the accompanying drawings.

제3도는 본 발명의 디램셀 공정단면도로서, 제3도 (a)와 같이 기판(1)에 필드영역과 액티브영역을 정의하여 필드영역에 필드산화막(5)을 형성하고 액티브영역에 게이트절연막을 형성한 다음,일정한 간격으로 게이트(2)를 형성한다. 그리고 게이트(2)를 마스크로 이용한 고농도 n형 이온주입하여 소오스 및 드레인영역(4)을 형성하고 게이트(2)측면에 절연막 측벽(3)을 형성한다.FIG. 3 is a cross-sectional view of the DRAM cell process according to the present invention. As shown in FIG. 3A, a field region and an active region are defined in the substrate 1 to form a field oxide film 5 in the field region and a gate insulating film in the active region. After the formation, the gate 2 is formed at regular intervals. The source and drain regions 4 are formed by implanting high concentration n-type ions using the gate 2 as a mask, and the insulating film sidewall 3 is formed on the gate 2 side.

제3도 (b)와 같이 전면에 LTO(Low Temperature Oxidation)(6)를 증착한다음 전면에 제1플레이트용 폴리실리콘(8a)을 증착하고 커패시터영역에만 남도록 패터닝한다.As shown in (b) of FIG. 3, a low temperature oxide (LTO) 6 is deposited on the front surface, and then polysilicon 8a for the first plate is deposited on the front surface and patterned to remain only in the capacitor region.

제3도 (c)와 같이 전면에 제1유전체막(9)을 증착하고 제3도 (d)와 같이 소오스영역 상측의 LTO(6) 및 제1유전체막(9)를 선택적으로 제거하여 커패시터 스토리지노드(Storage node) 콘택(Contact)(7)을 형성한 다음, 전면에 스토리지노드로 사용할 폴리실리콘(8)을 증착하고 커패시터영역을 정의하여 불필요한 부분의 폴리실피콘(8)을 선택적으로 제거한다.As shown in FIG. 3 (c), the first dielectric film 9 is deposited on the entire surface, and as shown in FIG. 3 (d), the LTO 6 and the first dielectric film 9 on the upper side of the source region are selectively removed. Form storage node contacts (7), then deposit polysilicon (8) to be used as storage nodes on the front side and define capacitor regions to selectively remove unnecessary polysilicon (8) do.

제3도 (e)와 같이 전면에 제2유전체막(9a)을 증착하고 제2유전체막(9a)이 폴리실리콘(8) 표면 부위에만 남도록 패터닝한다.As shown in FIG. 3 (e), the second dielectric film 9a is deposited on the entire surface, and the second dielectric film 9a is patterned so that only the surface portion of the polysilicon 8 remains.

제3도 (f)와 같이 상기 제1플레이트용 폴리실리폰(8a)에 연결되도록 전면에 제2폴레이트용 폴리실리콘(8b)을 증착하고 전면에 LTO(6a)를 증착한후 커패시터영역을 정의하여 불필요한 폴리실리콘(8a,8b)과 LTO(6a)를 선택적으로 제거한다.As shown in FIG. 3 (f), the second folate polysilicon 8b is deposited on the front surface and the LTO 6a is deposited on the front surface so as to be connected to the first polysilicon 8a. To selectively remove unnecessary polysilicon 8a, 8b and LTO 6a.

제3도 (g)와 같이 전면에 BPSG(Boron Phosphorous Silicate Glass)(10)를 증착하고 상기 드레인영역 상측의 LTO(6) 및 BPSG(10)를 선택적으로 제거하여 비트라인(bit line) 콘택을 형성한 다음, 제3도 (아)와 같이 비트라인 메탈(11)을 형성한다.As shown in FIG. 3 (g), a BPSG (Boron Phosphorous Silicate Glass) 10 is deposited on the entire surface, and the bit line contact is selectively removed by selectively removing the LTO 6 and the BPSG 10 on the drain region. After forming, the bit line metal 11 is formed as shown in FIG.

이와같이 형성한 디램셀은 제4도와 같은 회로구성을 갖는다.The DRAM cell thus formed has a circuit configuration as shown in FIG.

이와같이 제조되는 본 발명의 디램셀 구조는 제3도 (h)와같이 필드영역과 액티브영역으로 정의되어 필드영역에 필드산화막(5)이 형성된 기판(1)에 게이트(2)와 소오스 및 드레인(4)영역을 구비한 트랜지스터가 형성되고, 상기 소오스영역상에 콘택홀을 갖고 상기 트랜지스터를 절연시키기 위한 절연막(6)이 형성되고, 상기 콘택홀 양측의 절연막(6)위에 제1플레이트용 폴리실리콘(8a)이 형성되고, 상기 콘택홀을 통해 소오스영역과 연결되도록 제1플레이트용 폴리실리콘(8a)과 절연막(6)상에 걸쳐 커패시터 영역에 스토리지노드용 폴리실리콘(8)이 형성되고, 상기 전면에 제1플레이트용 폴리실리콘(8a)과 연결되도록 제2플레이트용 폴리실리콘(8b)이 형성되고, 상기 제1,제2플레이트용 폴리실리폰(8a,8b)과 스토리지 노드용 폴리실리콘(8)사이에 유전체막이 형성되는 구조를 갖는다.The DRAM cell structure of the present invention manufactured as described above is defined as the field region and the active region as shown in FIG. 3 (h), and the gate 2, the source and the drain (2) are formed on the substrate 1 having the field oxide film 5 formed in the field region. 4) a transistor having a region is formed, an insulating film 6 for insulating the transistor with a contact hole is formed on the source region, and polysilicon for the first plate on the insulating film 6 on both sides of the contact hole. 8A is formed, and the polysilicon 8 for the storage node is formed on the capacitor region over the first plate polysilicon 8a and the insulating layer 6 so as to be connected to the source region through the contact hole. The second plate polysilicon 8b is formed on the front surface thereof so as to be connected to the first plate polysilicon 8a, and the first and second plate polysilicons 8a and 8b and the storage node polysilicon ( 8) A dielectric film is formed between It has the following structure.

이상에서 설명한 바와같은 본 발명의 디렘셀의 제조방법 및 구조에 있어서는 플레이트전극이 이중 구조로 적층되어 동일 면적내에서 커패시터 면적을 증가 시키므로 고집적 디램셀을 실현할 수 있는 효과가 있다.As described above, in the method and structure of manufacturing the dramcell of the present invention, since the plate electrodes are stacked in a double structure to increase the capacitor area within the same area, it is possible to realize a highly integrated DRAM cell.

Claims (1)

필드영역과 액티브영역이 정의된 반도체 기판에 게이트절연막과 게이트 전극을 형성하는 공정과, 상기 게이트전극 양측 기판에 소오스 및 드레인 영역을 형성하고 상기 게이트전극 측면에 절연막 측벽을 형성하는 공정과, 전면에 절연막을 증착하고 커패시터 형성영역의 절연막 상에 선택적으로 제1플레이트와 제1유전체막을 형성하는 공정과, 상기 소오스영역에 스토리지노드 콘택을 형성하고 스토리지노드를 형성하는 공정과, 상기 스토리지노드 표면에 제2유전체막을 형성하로 제1플레이트와 연결되도록 제2플레이트를 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 디램셀 제조방법.Forming a gate insulating film and a gate electrode on a semiconductor substrate having a field region and an active region defined therein; forming a source and a drain region on both substrates of the gate electrode; and forming an insulating film sidewall on the side of the gate electrode; Depositing an insulating film and selectively forming a first plate and a first dielectric film on the insulating film of the capacitor formation region, forming a storage node contact in the source region and forming a storage node, and forming a storage node on the surface of the storage node. And forming a second plate to be connected to the first plate to form a second dielectric film.
KR1019890009033A 1989-06-29 1989-06-29 Semiconductor memory and manufacture thereof KR0156097B1 (en)

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