JPH04216666A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To ensure a sufficient capacitor capacitance without difficulty in working when the capacitor area is reduced in a planar domain, by constituting a capacitor by using a conducting film whose side wall part is in an uneven type, a dielectric film coating the conducting film, and a second conducting film on the dielectric film. CONSTITUTION:A capacitor 22 is constituted of the following; an insulating film 8a formed on the upper part and the side wall part of a gate electrode 4a, a first conducting film 15 which is connected with the upper part of a first impurity region, the end portion of which film 15 is formed on the insulating film 8a above the gate electrode 4a, and the side wall part 23 of which film 15 is in an uneven type, a dielectric film 16 formed so as to cover the conducting film 15, and a second conducting film 17 formed on the film 16. Further a third conducting film 19b and the like are formed, which film is formed on the conducting film 15, the dielectric film 16, and the second conducting film 17, and connected with a second impurity region 9a directly or via a signal transmission line.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor device.
In particular, DRAM (Dyn
amic Random Access Memory
) and other semiconductor devices and their manufacturing methods.

0002

[Prior Art] FIG. 7 shows a DRAM which is a conventional semiconductor device.
2 is a cross-sectional view of a memory cell of FIG. A gate oxide film 3 is formed on the substrate 1 in a predetermined area by thermal oxidation of the substrate 1, a gate electrode 4a is formed on the gate oxide film 3, and a gate electrode 4b is formed on the element isolation region 2. , these gate electrodes 4a, 4b
Insulating films 8a and 8b are formed to cover.

Furthermore, using the insulating films 8a and 8b as masks, impurity ions are implanted into the surface of the substrate 1 in predetermined regions by an ion implantation method to form impurity regions 6a and 6b on both sides of the gate electrodes 4a and 4b. electrode 4a,
A lower electrode 7 is formed on the impurity region 6b and on the impurity region 6b, the surface of the lower electrode 7 is covered with a dielectric film 16, the dielectric film 16 is further covered with an upper electrode 17, and an insulating film for interlayer insulation is formed on the upper electrode 17. 18 is formed, and a conductive film 20 serving as read/write electrodes is formed on the insulating film 18 to complete the memory cell.

At this time, the conductive film 20 is in contact with the impurity region 6a through the opening formed in the insulating film 18, and the lower electrode 7, the dielectric film 16, and the upper electrode 17 constitute a charge storage capacitor 22. , gate electrodes 4a, 4b, and both impurity regions 6a, 6b constitute a transistor 21.

Then, the transistor 21 is turned on, and the capacitor 22 is connected through the conductive film 20 and the transistor 21.
Charge is accumulated and released, and information is written and read.

[0006]

[Problems to be Solved by the Invention] In conventional semiconductor devices of this type, when the memory cell size is reduced due to higher integration, the capacitor area is also reduced accordingly. Stable operation and reliability must be guaranteed, and the amount of charge that can be stored in a memory cell must be maintained approximately constant even with high integration.

Conventionally, the capacitor 22 is made as large as possible in plan to maintain the capacitance. However, after the capacitor 22 is formed, the insulating film 18
, when forming the conductive film 20 and processing the pattern, the connection portion of the conductive film 20 with the impurity region 6a and the capacitor 22
There was a problem in that the distance between the end of the holder and the end of the holder became very narrow, and there was a risk of a short circuit.

The present invention has been made to solve the above-mentioned problems, and even if the area of a capacitor is reduced in two dimensions due to the increase in the degree of integration of semiconductor devices, it can be achieved without causing difficulties in pattern processing. The object of the present invention is to obtain a semiconductor device that can secure sufficient capacitance.

[0009]

[Means for Solving the Problems] A semiconductor device according to the present invention includes first and second semiconductor devices formed at a predetermined interval in a surface region surrounded by an element isolation region on a semiconductor substrate of a first conductivity type. a second conductivity type impurity region, a gate electrode formed on the semiconductor substrate between the first and second impurity regions via a first insulating film, and an upper and sidewall portion of the gate electrode. A first insulating film connected to the formed second insulating film and the first impurity region, the end of which is formed on the second insulating film on the gate electrode, and the sidewall of which is uneven. A capacitor comprising a conductive film, a dielectric film formed to cover the first conductive film, and a second conductive film formed on the dielectric film, the first conductive film, a third insulating film formed on the dielectric film and the second conductive film; and a third insulating film formed on the third insulating film and connected to the second impurity region directly or via a signal transmission line. It has a conductive film.

A method for manufacturing a semiconductor device according to the present invention includes the steps of forming an element isolation region on a semiconductor substrate of a first conductivity type, and forming a first conductivity type on a main surface of the semiconductor substrate surrounded by the element isolation region. a step of forming an insulating film, a step of forming a gate electrode on the first insulating film and the element isolation region, a step of forming a second insulating film on the upper part of the gate electrode and on the sidewalls,
forming at least two impurity regions of a second conductivity type in a region other than the region where the gate electrode is formed on the main surface of the semiconductor substrate surrounded by the element isolation region; a step of stacking polycrystalline silicon with different concentrations on the impurity region and the second insulating film and etching it to form a first conductive film having unevenness on the sidewall; forming a dielectric film and a second conductive film, and forming a third insulating film having an opening on the other one of the two impurity regions on the first conductive film, the dielectric film, and the second conductive film. and forming a signal transmission line on the impurity region through the opening.

0012

[Operation] In the semiconductor device according to the present invention, the sidewalls of the first conductive film and the dielectric film constituting the capacitor are formed in an uneven shape, and by utilizing the surface, the semiconductor device can be integrated. Even if the area of the formation region is reduced, it is possible to obtain a semiconductor device with sufficient capacitance without increasing the size of the capacitor in plan view, and without causing difficulties such as short circuits during pattern processing.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the step of forming the lower electrode, polycrystalline silicon having different concentrations is stacked and etched, thereby making it possible to form the side wall portion of the lower electrode in an uneven shape.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a stacked type memory cell of a DRAM according to an embodiment of the present invention. In the figure, the memory cell is composed of one access transistor 21 and one capacitor 22. This memory cell is insulated and isolated from adjacent memory cells by an element isolation region 2 formed on the surface of a semiconductor substrate 1.

Access transistor 21 includes impurity regions 6a, 9a and 6b formed on the surface of semiconductor substrate 1.
, 9b and a gate electrode 4a located between the impurity regions 6a, 9a and 6b, 9b with a thin gate oxide film 3 interposed therebetween.

The capacitor 22 includes a lower electrode 15 made of a conductive material such as polycrystalline silicon, and a dielectric layer made of a dielectric material such as a laminated film of a nitride film and an oxide film or a tantalum oxide film formed on the lower electrode 15. 16, and an upper electrode 17 formed on the dielectric layer 16 and made of a conductive material such as polycrystalline silicon. The lower electrode 15 is connected to the source or drain region 6b, 9 of the access transistor 21.
directly connected to b. The bit line 19b is connected to the interlayer insulating film 1 formed on the capacitor 22 and the transistor 21.
8 and is connected to source or drain regions 6a, 9a of access transistor 21 directly or via a conductive layer (bit line) 19a.

In this memory cell, capacitor 2
The side wall portion 23 of the lower electrode 15 of No. 2 is formed into an uneven shape. This makes it possible to increase the area of the capacitor by the amount that the side wall portion 23 has an uneven shape. therefore,
The area of the capacitor can be easily increased without changing the area seen from a plane, and a sufficient capacity can be ensured even if the memory cell size is reduced.

A method of manufacturing the present semiconductor device will be described with reference to FIGS. 2 to 6. 2 to 6 are cross-sectional structural diagrams for explaining the manufacturing process of the memory cell shown in FIG. 1.

First, as shown in FIG. 2(a), an element isolation region 2 is formed in a predetermined region of the surface of a semiconductor substrate 1 using the LOCOS method. Next, as shown in Figure 2(b),
The surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 3 on the surface of the semiconductor substrate 1 surrounded by the element isolation region 2. A conductive film 4 of polycrystalline silicon doped with phosphorus is formed on the oxide film 3 by low pressure CVD, and an insulating film 5 made of an oxide film is further formed by low pressure CVD. Figure 3(a)
As shown in FIG.
is removed leaving only a predetermined portion. As a result, gate oxide film 3 and gate electrodes 4a and 4b of the access transistor and word line, and insulating films 5a and 5b thereon are formed. Next, as shown in FIG. 3(b), the gate electrode 4a
, 4b and the insulating films 5a, 5b formed thereon as masks, relatively low concentration impurity regions 6a, 6b are formed on the surface of the semiconductor substrate 1 by ion implantation. As shown in FIG. 3(c), an insulating film 8 made of an oxide film is formed over the entire surface of the semiconductor substrate 1 by low pressure CVD. Next, as shown in FIG. 4(a), the insulating film 8 is selectively removed by anisotropic etching, and the gate electrodes 4a,
Insulating films 8a and 8b are formed on the top and sidewalls of 4b. Next, as shown in FIG. 4(b), the gate electrodes 4a, 4
Relatively high concentration impurity regions 9a and 9b are formed on the surface of semiconductor substrate 1 by ion implantation using insulating films 8a and 8b on the semiconductor substrate 1 as masks. As a result,
Although a transistor having a so-called LDD structure is formed, the structure of the access transistor does not have to be an LDD structure, and may have another structure. Next, as shown in FIG. 4(c), an insulating film 1 made of a nitride film is formed by low pressure CVD.
0 is formed on the semiconductor substrate 1, and then the nitride film 10 in the source/drain regions 6b and 9b to which the lower electrodes of the capacitors are connected is selectively removed using conventional photolithography and etching methods. Next, as shown in FIG. 5A, a conductive film 11 made of polycrystalline silicon and a conductive film made of polycrystalline silicon doped with phosphorus, for example, which has a higher concentration than the conductive film 11 made of polycrystalline silicon, are formed by low pressure CVD. 12 and a conductive film 13 made of polycrystalline silicon having a concentration lower than that of the conductive film 12 or equivalent to that of the conductive film 11 are sequentially deposited over the entire surface of the semiconductor substrate 1. Next, Figure 5(b)
As shown in FIG. 2, the conductive film 1 is removed by using ordinary photolithography and etching methods except for the source/drain regions 6a, 9b and the portions extending to the nitride film 10.
1, 12, and 13 are selectively removed. At this time, the etching amount varies depending on the concentration difference of the polycrystalline silicon 11, 12, and 13, and a conductive film (lower electrode) 15 whose side wall portion 23 is uneven (concave) is formed. Next, as shown in FIG. 5C, a nitride film is formed on the entire surface of the semiconductor substrate 1 by low pressure CVD, and the semiconductor substrate 1 is heat-treated in an oxygen atmosphere. As a result, a portion of the nitride film is oxidized to form the dielectric film 16 of the capacitor. A conductive film 17 made of polycrystalline silicon is formed over the entire surface of the semiconductor substrate 1 by low pressure CVD. Then, portions other than those forming the capacitor 22 are removed. Next, as shown in FIG. 6, an insulating film 18 made of an oxide film is formed over the entire surface of the semiconductor substrate 1 by the CVD method. The insulating film 18 at the connection portion between the bit line 19a and the source/drain regions 6a, 9a of the access transistors is selectively removed by ordinary photolithography and etching to form an opening. Next, a tungsten film 19a is selectively formed in the opening of the insulating film 18 by the CVD method, and the opening is filled with the tungsten film 19a. Furthermore, a conductive film made of tungsten silicide is deposited over the entire surface using a sputtering method. Thereafter, the bit line 19b is formed by patterning into a predetermined shape using ordinary photolithography and etching methods, thereby completing the device.

As described above, according to this embodiment, since the lower electrode is formed by laminating and etching polycrystalline silicon having different concentrations, the lower electrode can be formed with unevenness on the side wall portion.

Furthermore, according to this embodiment, since the surface area of the capacitor increases due to the unevenness of the side wall, a sufficient capacity can be obtained without increasing the capacitor in plan view.

In this embodiment, a tungsten silicide film is used as the bit line 19a, but the present invention is not limited to this, and may be made of a polycrystalline silicon film, a metal silicide film, a metal film, a TiN film, or any of these films. It may also be a composite membrane layered alternately. Further, although a tungsten silicide film deposited by sputtering is shown as the bit line 19b, the present invention is not limited to this, and the present invention is not limited to this. It may also be a composite membrane layered on top of each other. Further, in this embodiment, the bit line 19b is connected to the source/drain regions 6a, 9a of the access transistors via the bit line 19a.
Although the present invention is not limited to this, the present invention is not limited to this.
The bit line 19b may be directly connected to the source/drain regions 6a and 9a without using the bit line 19a.

Further, in this embodiment, when forming the lower electrode 15, a three-layer structure of polycrystalline silicon 11, 12, and 13 was shown, but the present invention is not limited to this. It may also be a composite membrane made of Furthermore, in this embodiment, when forming the lower electrode 15, polycrystalline silicon films with different concentrations are sequentially deposited. It's okay. Further, in the case of ion implantation, implantation may be performed only into the side wall portion 23. Furthermore, although an example has been shown in which the lower electrode 15 is formed using a dry etching method, the present invention is not limited to this, and the side wall portion 23 is formed into an uneven shape using isotropic etching or the like after dry etching. It's okay.

[0026]

As described above, according to the present invention, the side wall portion of the lower electrode is formed into an uneven shape, and by utilizing the side wall portion, the capacity is increased without increasing the planar area. Even when the cell size is reduced, it is possible to obtain a semiconductor device suitable for high integration, which can ensure capacitor capacity without any difficulty in pattern formation.

Further, according to the present invention, in the step of forming the lower electrode of the capacitor, the first conductive film, the second conductive film having a lower concentration than the first conductive film, and the second conductive film having a lower concentration than the second conductive film are formed. Alternatively, a third conductive film having the same concentration is sequentially formed and etched using a dry etching method, which has the effect of forming a lower electrode with an uneven side wall portion.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a DRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a cross-sectional structural diagram for explaining a part of the manufacturing process of the DRAM memory cell shown in FIG. 1;

FIG. 3 is a cross-sectional structural diagram for explaining a part of the manufacturing process of the DRAM memory cell shown in FIG. 1;

FIG. 4 is a cross-sectional structural diagram for explaining a part of the manufacturing process of the DRAM memory cell shown in FIG. 1;

FIG. 5 is a cross-sectional structural diagram for explaining a part of the manufacturing process of the DRAM memory cell shown in FIG. 1;

FIG. 6 is a cross-sectional structural diagram for explaining a part of the manufacturing process of the DRAM memory cell shown in FIG. 1;

FIG. 7 is a cross-sectional view of a conventional stacked type memory cell.

[Explanation of symbols]

1 Semiconductor substrate 2 Element isolation region 3 Oxide film 4 Conductive film 4a Gate electrode 4b Gate electrode 5 Insulating film 5a Insulating film 5b Insulating film 6a Impurity region 6b Impurity region 7 Lower electrode 8 Insulating film 8a Insulating film 8b Insulating film 9a Impurity region 9b Impurity region 10 Insulating film 11 Conductive film 12 Conductive film 13 Conductive film 15 Lower electrode 16 Dielectric film 17 Conductive film 18 Insulating film 19a Tungsten film 19b bit line 21 Access transistor 22 Capacitor 23 Side wall part

Claims (2)

[Claims] Claims: 1. In a semiconductor device having a charge storage capacitor, a first semiconductor substrate is formed at a predetermined interval in a surface region surrounded by an element isolation region on a semiconductor substrate of a first conductivity type.
, a second impurity region of a second conductivity type, a gate electrode formed on the semiconductor substrate via a first insulating film between the first and second impurity regions, and an upper part of the gate electrode. and a second insulating film formed on the side wall portion and connected on the first impurity region, an end thereof is formed on the second insulating film on the gate electrode, and the side wall portion has an uneven shape. a first conductive film, a dielectric film formed to cover the first conductive film, and a second conductive film formed on the dielectric film; conductive film, dielectric film, second
a third insulating film formed on the conductive film, and a second insulating film formed on the third insulating film directly or via a signal transmission line.
A semiconductor device comprising a third conductive film connected to an impurity region. [Claim 2] In a method of manufacturing a semiconductor device, a first
forming a device isolation region on a conductive type semiconductor substrate; forming a first insulating film on the main surface of the semiconductor substrate surrounded by the device isolation region; and forming a first insulating film on the first insulating film. and a step of forming a gate electrode on the element isolation region, a step of forming a second oxide film on the upper and side wall portions of the gate electrode, and a step of forming a second oxide film on the main surface of the semiconductor substrate surrounded by the element isolation region. forming at least two impurity regions of a second conductivity type in a region other than the region where the gate electrode is formed; a step of stacking different polycrystalline silicones and etching to form a first conductive film with uneven side walls; a step of forming a dielectric film and a second conductive film on the first conductive film; forming a third insulating film having an opening on the other one of the two impurity regions on the first conductive film, the dielectric film, and the second conductive film; A method of manufacturing a semiconductor device, comprising the steps of: forming a third conductive film; and forming a signal transmission line on the impurity region through the opening.