JP2772375B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor memory device and a method of manufacturing the same, particularly, a highly integrated and high performance dynamic random access memory (DR).
AM) A method of forming a cell structure, which aims to form a structure that increases storage capacitance per area, and selectively removes a film between an insulating film on a bit line and a storage electrode on the insulating film. After forming a gap by (etching), the bit line is made of a conductor that supplies a common electrode potential to a plurality of memory cells in common, and the bit line is covered with the insulating film, and the storage is made with a dielectric film. The method includes forming a counter electrode facing the upper surface, the side surface, and the lower surface of the electrode. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a method of forming a highly integrated and high performance dynamic random access memory (DRAM) cell structure. [Prior Art] FIG. 8 is an explanatory diagram relating to a DRAM cell according to a conventional example. FIG. 2A is an electric circuit diagram of the DRAM cell. In the figure, T is a transfer transistor composed of a MOS transistor or the like for transferring data (charge), C is a storage capacitor for storing charge, WL is a word line, and BL is a bit line. Reference numeral 6 denotes a storage electrode, 7 denotes a dielectric film, and 8 denotes a counter electrode. FIG. 1B is a sectional view showing the DRAM cell structure. In the figure, 1 is a Si substrate such as a p-type epitaxial layer, and 2 is a field oxide film (SiO ₂₎ formed by a selective LOCOS method or the like.
Films) 3, 4 are impurity diffusion layers formed by diffusing A ⁺ ions and the like, and are source or drain of the transfer transistor T. 5 is an insulating film for insulating the word line WL, and CV
D oxide film (Si ₃ N ₄ film or SiO ₂ film). Reference numeral 6 denotes an electrode formed by doping impurity ions in the poly-Si film, and is a storage electrode constituting a storage capacitor C. 7 is SiO ₂ film or Si ₃ N
_This is a dielectric film formed by an insulating film such as _four films. Reference numeral 8 denotes an electrode formed by doping impurity ions in the poly-Si film, and is a counter electrode constituting the storage capacitor C. Reference numeral 9 denotes an insulating film that insulates the counter electrode 8, such as a PSG film. Reference numeral 10 denotes a contact hole for the bit line BL. WL is a gate electrode of the transfer transistor T formed of a poly-Si film or the like, and is a word line. Also, BL
Is a bit line formed of a poly-Si film or a polycide film doped with impurities. [Problems to be Solved by the Invention] According to the conventional example, the area of the memory cells of the DRAM is further reduced as the integration degree of the semiconductor memory device is increased and the semiconductor element is miniaturized. Therefore, there are the following problems. First, the storage capacity of the memory cell, which depends on the size of the area of the substrate region where the storage electrode is arranged, decreases, and second, the soft error due to α-ray incidence increases due to the decrease in the storage capacity. Third, when the storage capacitance is small, interference due to signal voltage between bit lines cannot be ignored, and a read malfunction due to the interference is likely to occur. The present invention has been made in view of the problems of the related art, and has as its object to provide a method of manufacturing a semiconductor memory device capable of increasing the storage capacity per capacitor area. [Means for Solving the Problems] The present invention provides a transfer transistor having a pair of impurity diffusion layers 33 and 34 and a gate electrode, as illustrated in FIG.
In a method for manufacturing a semiconductor memory device having a plurality of memory cells each including a storage capacitor connected to the transfer transistor T4, a step of forming the transfer transistor T4 on a semiconductor substrate, and a first step of covering the transfer transistor T4 Forming an insulating film 35, and forming a bit line BL4 on the first insulating film 35 to be connected to one of the pair of impurity diffusion layers 33 and 34 through an opening 36 formed in the first insulating film 35. A step of forming a second insulating film 38 covering the bit line BL4; a step of covering the second insulating film 38 with a film 39 of a material different from that of the second insulating film 38; Forming a first conductor film 40 connected to the other of the pair of impurity diffusion layers 33 and 34 on the film 39, and patterning at least the first conductor film 40 into the shape of the storage electrode 45. When,
The film 39 is selectively removed so that the storage electrode 45 and the second
Forming a gap between the insulating film 38 and the storage electrode
Forming a dielectric film 46 on the surface of the storage electrode 45; extending in the gap to cover the bit line BL4 via the second insulating film 38; and forming the storage electrode 45 via the dielectric film 46. The second conductive film facing the upper surface, the side surface, and the downward surface is provided with a counter electrode.
47. A method of manufacturing a semiconductor memory device, comprising: For example, the film 39 is silicon oxide, the second insulating film 38
Is silicon nitride, and the second conductor film 40 is silicon. It should be noted that the drawings and reference numerals quoted here are only for facilitating the understanding of the invention, and are not limited thereto. [Operation] According to the present invention, after a film between an insulating film on a bit line and a storage electrode on the insulating film is selectively removed (etched) to form a gap, a counter electrode potential is supplied. The method includes a step of manufacturing a capacitor made of a conductor and covering the bit line with the insulating film interposed therebetween, and forming a counter electrode facing the upper, side, and lower surfaces of the storage electrode with the dielectric film interposed therebetween. . As described above, since the capacitance value of the memory cell capacitor is greatly increased by forming the counter electrode which goes under the storage electrode, the memory cell can be highly integrated without increasing the area occupied by one memory cell. Can be achieved.
In addition, due to the increased storage capacity, soft errors due to α-ray incidence etc. are greatly reduced, bit line interference is reduced, and DR
The reliability of the memory characteristics of the AM cell can be improved. The selective etching of the film between the insulating film and the storage electrode can be easily realized by making the material forming the film different from the material of the insulating film and the storage electrode. Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a structure of a first DRAM cell according to a first reference example. 2A and 2B are cross-sectional views of a first DRAM cell, and FIG. 1C is a plan view thereof. In addition, FIG.
Is a cross-sectional view taken along the line AA 'in FIG.
Is a sectional view taken along the line BB 'in FIG. In the figure, 11 is an Si substrate such as an epitaxial layer, 12 is a field oxide film which has been selectively LOCOS oxidized, and 13 and 14 are impurity diffusion layers formed by thermally diffusing impurities such as As ⁺ ions. _{1 is} the source and drain. WL ₃ , WL ₄
Is a gate electrode formed of a poly-Si film, etc.
A word line in a cell. Reference numeral 15 denotes an insulating film such as a gate oxide film that insulates the gate electrodes WL ₃ and WL ₄ and is formed of a Si ₃ N ₄ film or a SiO ₂ film. BL ₁
Denotes a bit line, which is formed by a poly-Si film 17 containing impurities or a polycide film. 18 is a SiO ₂ film for insulating the bit line BL _1. Thus like constituting the transfer transistor T _1. 20a is a poly-S containing impurity with a desired film thickness.
This is a storage electrode formed by the i film. Reference numeral 21 denotes a dielectric film, which is formed by heat-treating the storage electrode 20a. Incidentally, 22 is a counter electrode formed by the poly-Si film containing impurities, to form a storage capacitor C ₁ with the storage electrode 20a and the dielectric film 21. Also, in FIG.
Is a contact hole of the bit line BL _1. These constitute a first DRAM cell. FIGS. 2A and 2B are structural views of a DRAM cell according to a second reference example, wherein FIGS. 2A and 2B are sectional views and FIG. 2B is a plan view thereof. Incidentally, in FIG., T ₂ is a transfer transistor, C ₂ is the storage capacity, the same reference numerals have the same functions as the first embodiment. 16a and 16b are bit lines BL ₂₁ ,
The contact holes of the BL ₂₂ are different from those of the first reference example in that the contact holes 16a and 16b of the bit lines BL ₂₁ and BL ₂₂ are provided.
Are shifted. That is, in the second embodiment, the distance between the contact hole 16a and the other or the interval between the bit lines BL _22, likewise the contact hole 16b and the other bit line BL ₂₃ of the bit line BL ₂₂ of the bit line BL ₂₁ second The width is wider than in the case of the first embodiment to improve the withstand voltage. Incidentally, the forming method is compared with the first reference example, the transfer transistor T ₂ of the extending the impurity diffusion layers for the source and the contact holes 16a, done by changing the resist pattern 16b, etc., of other The formation process is performed in the same manner as in the first reference example. FIG. 3 is a structural view of a third DRAM cell according to a third reference example, wherein FIGS. 3 (a) and 3 (b) are sectional views thereof and FIG. 3 (c) is a plan view thereof. 2A is a sectional view taken along the line AA 'in FIG. 1C, and FIG. 2B is a sectional view taken along the line BB' in FIG. 1C. In FIG, T ₃ transfer transistor, C ₃ is a storage capacitor, is of the same sign as the first reference example has the same function. 25a is a storage electrode, 26 is a dielectric film, 2
7 is a counter electrode. What is different from the first reference example is that
Opening 24 for connecting drain 13 and storage electrode 25a
Also, the contact hole of the bit line (not shown)
The point is that the SiO ₂ films 18 and 23 are formed in a self-aligned manner by anisotropic etching such as RIE. As a result, the alignment of the electrode contact holes is facilitated, the distance between the bit lines can be increased, and the dielectric strength can be increased. FIG. 4 is a structural diagram of a DRAM cell formed by a manufacturing method according to an embodiment of the present invention, and an embodiment of the manufacturing method will be described later. 2A and 2B are cross-sectional views, and FIG. 1C is a plan view. 2A is a sectional view taken along the line AA 'in FIG. 1C, and FIG. 2B is a sectional view taken along the line BB' in FIG. 1C. The difference from the first reference example is that the storage electrode forming the storage capacitor has a cross-sectional tree structure. That is, in the figure, reference numeral 31 denotes Si such as an epitaxial layer.
Substrate, 32 is selected LOCOS oxidized field oxide, 3
3,34 is an impurity diffusion layer formed by thermal diffusion of impurities such as As ⁺ ions, a source and a drain of the transfer transistor T _4. WL ₅ and WL ₆ are electrodes formed of a poly-Si film or the like, and are word lines of the DRAM cell. Reference numeral 35 denotes an insulating film such as a gate oxide film that insulates the gate electrodes WL ₅ and WL ₆ and is formed of a Si ₃ N ₄ film or a SiO ₂ film. BL ₄
Is a bit line, a poly-Si film 37 containing impurity ions.
And a polycide film. Reference numeral 38 denotes a Si ₃ N ₄ film that insulates the bit line BL ₄ . Thus like constituting the transfer transistor T _4. Reference numeral 45a denotes a storage electrode formed on a Si ₃ N ₄ film that insulates the bit line BL ₄ , and is a poly-Si containing impurity ions.
It has a cross-sectional dendritic structure formed by the film. Reference numeral 46 denotes a dielectric film, which is formed by heat-treating the storage electrode 45a. Incidentally, 47 is a counter electrode formed by the poly-Si film containing an impurity ions to form a storage capacitor C ₄ with the storage electrode 45a and the dielectric film 46. Thus, the DRAM cell formed according to the embodiment of the present invention is configured, and the storage electrode 45a has a cross-sectional tree structure, so that the storage electrode area can be increased. This makes it possible to several times larger than the storage capacitor C ₄ to the conventional. FIG. 5 is a process chart for forming a first DRAM cell according to the first reference example. Incidentally, FIG. _{(A 1) ~ (f 1} ) is a forming process view of A-A 'cross section of the first DRAM cell, FIG. (A ₂₎ ~
(F ₂ ) is a view showing the step of forming the BB ′ section. In the figure, first, a Si substrate 11 such as a D-type epitaxial layer
Thermal oxidation by selective LOCOS method etc.
12 are formed, and desired impurity ions such as As ⁺ ions are implanted into the Si substrate 11. Thereafter, heat treatment is performed to form n ⁺ impurity diffusion layers 13 and 14. The n ⁺ impurity diffusion layers 13 and 14
The source of the transfer transistor T _1, the drain. Further, a gate electrode WL is formed by a poly-Si film through a not-shown SiO ₂ film (gate oxide film) formed by a selective LOCOS method or the like.
_3, to form a WL _4. The gate electrodes WL ₃ and WL ₄ become word lines in the DRAM cell (FIGS. (A ₁ ) and (a ₂ )). Then, the gate electrode WL _3, WL ₄ a thickness of about 1000Å of SiO ₂
Insulated by the film 15, using a resist film (not shown) as a mask
The SiO ₂ film 15 is opened by anisotropic etching such as RIE, and an opening 16 is formed. The opening 16 serves as a bit line contact wheel. The etching gas used for anisotropic etching is CF ₄ / O ₂ ((b ₁ ) and (b ₂ ) in the figure). Further, the entire surface of the Si substrate 11 having the opening 16 is
The poly Si film 17 doped with about 不純 物 impurity ions is decompressed by CV.
It is formed by the D method or the like, and is patterned by the RIE method or the like using a resist film (not shown) as a mask (FIG. (C ₁ ))
(C _2)). Next, an insulating film 18 is formed on the entire surface of the patterned poly-Si film 17.
As the SiO ₂ film and the Si ₃ N ₄ film is formed, then the resist film (not shown) as a mask, an opening and an insulating film 18 and the SiO ₂ film 15, an opening 19. Note the opening 19 is a contact hole of the storage electrode (FIG. _{(D 1), (d 2} )). Next, a poly-Si film 20 containing impurities is formed with a desired thickness on the entire surface of the Si substrate 11 provided with the opening 19, and thereafter, the poly-Si film 20 is etched using a resist film (not shown) as a mask. It is patterned by isotropic etching. Note that poly
The storage electrode 20a is formed by patterning the Si film 20. The etching gas is CCl ₄ / O ₂ (see FIG.
_{1), (e 2))} . Further, the storage electrode 20a is heat-treated to form a dielectric film 21 such as a SiO ₂ film (FIGS. (F ₁ ) and (f ₂ )). After the steps of forming (f ₁ ) and (f ₂ ) in the same figure, a poly-Si film containing impurity ions is formed on the entire surface of the dielectric film 21 as the counter electrode 22 (not shown) as in the conventional case. As a result, a first DRAM cell as shown in FIGS. 1A and 1B can be manufactured. FIG. 6 is a process chart of forming a DRAM cell according to a third reference example. In the DRAM cell formation process diagram according to the third reference example, the formation processes according to FIGS. (A ₁ ), (b ₁ ), (a ₂ ), and (b ₂ ) are the same as those shown in FIG. The steps of forming the DRAM cell of the reference example (a ₁ ), (b ₁ ), (a ₂ ), and (b ₂ ) are the same as those of FIG. That is, a poly-Si film 17 or a poly-silicide film containing impurities and an SiO ₂ film 18 are formed by a low-pressure CVD method on the entire surface of the Si substrate 11 provided with the opening 16 (FIG. (C ₁ )). , (c _2)). Next, using a resist film (not shown) as a mask, the bit line
The poly-Si film 17 to be BL ₃ is patterned by anisotropic etching such as RIE. At this time, the SiO ₂ film 18 is left on the poly-Si film 17 (FIGS. (D ₁ ) and (d ₂ )). Further, an SiO ₂ film 23 having a thickness of about 1000 ° is formed on the entire surface of the Si substrate 11 on which the poly-Si film 17 is patterned by a CVD method or the like (FIGS. (E ₁ ) and (e ₂ )). Then, the opening of the contact hole of the transfer transistor T ₃ and the resist film as a mask to partial bit line BL ₃ 24
Is formed by anisotropic etching such as RIE. Note the opening 24 can be formed in a self-aligned manner (FIG. _{(F 1), (f 2} )). Further, a poly-Si film 25 having a desired film thickness is reduced on the entire surface of the Si substrate 11 having the openings 24 in the same manner as in the manufacturing process of the first reference example.
It is formed by a CVD method or the like. Thereafter, the poly-Si film 25 is patterned by anisotropic etching such as RIE using a resist film (not shown) as a mask. The storage electrode 25a is formed by patterning the poly-Si film 25 ((g ₁ ) in FIG.
(G _2)). Subsequent formation process, conventional heat treated similarly storage electrodes 25a, SiO ₂ dielectric film 26 is formed of such film, further as a counter electrode 27, a dielectric film 26 of poly-Si film containing an impurity ions Formed over the entire surface of the substrate. As a result, a third DRAM cell as shown in FIG. 3 can be manufactured. Figure 7 is a forming process drawing of a DRAM cell according to an embodiment of the method of manufacturing the semiconductor memory device of the present invention, FIG. (A ₁₎ ~
(I ₂ ) is a process drawing relating to the formation of a cross section taken along the line AA ′ in FIG. 4 (c), and FIGS. (A ₂ ) to (i ₂ ) are formations of the cross section taken along the line BB ′ It is a process drawing. In the figure, first, similarly to the first reference example, a field oxide film 32 is formed on a Si substrate 31 such as a P-type epitaxial layer by a selective LOCOS method or the like, and a desired As ⁺
Impurity ions such as ions are implanted into the Si substrate 31. Thereafter, heat treatment is performed to form n ⁺ impurity diffusion layers 33 and. Incidentally n ⁺ impurity diffusion layers 33 and 34 are the source of the transfer transistor T _4, the drain. Further, via an unshown SiO ₂ film (gate oxide film),
Gate electrodes WL ₅ and WL ₆ are formed by a poly-Si film or the like. Note that the gate electrodes WL ₅ and WL ₆ become word lines in the DRAM cell ((a ₁ ) and (a ₂ ) in the figure). Then, the gate electrode WL _5, WL ₆ a thickness 1000Å about SiO ₂
The insulating film 35 is insulated by an insulating film 35 such as a film or a Si ₃ N ₄ film, and the insulating film 35 is opened by anisotropic etching such as RIE using a resist film (not shown) as a mask to form an opening 36. Note that the opening 36 becomes a contact hole for the bit line. The etching gas used for anisotropic etching is CF ₄ / O ₂ ((b ₁ ) and (b ₂ ) in the figure). Further, a film thickness of 1000
Low pressure CVD of poly-Si film 37 containing about Å impurity ions
Formed using a resist film (not shown) as a mask.
Patterning by RIE method etc. ((c ₁ ) in the same figure,
(C _2)). Next, in this embodiment, a heat-resistant oxidizing insulating film having a thickness of about 1000 mm is formed on the entire surface of the patterned poly-Si film 37 as Si ₃ N _4.
A film 38 is formed (FIGS. (D ₁ ) and (d ₂ )). Next, on the entire surface of the Si substrate 31 on which the Si ₃ N ₄ film 38 was formed,
Approximately 000 mm of SiO ₂ film 39 and a poly-Si film 40 containing impurity ions of the same thickness are sequentially laminated, and further a SiO ₂ film 40 of the same thickness and a poly-Si film 42 containing the impurity ions are laminated, An SiO ₂ film 43 is formed on the top. The step of forming the two layers of the SiO ₂ film and the poly-Si film containing the impurity ions may be performed by N
Repeatedly carried out times (Fig. _{(E 1), (e 2} )). Next, using a resist film (not shown) as a mask, the SiO ₂ film selectively laminated N + 1 times, the poly-Si film laminated N times, the Si ₃ N ₄ film 38, and the insulating film 35 are formed by different methods such as RIE. An opening 44 is formed by removing the opening by anisotropic etching. The etching gas is CF ₄ / SiO ₂ film and Si ₃ N ₄ film.
CCl ₄ / O ₂ is used for O ₂ and poly-Si film ((f ₁ ) in FIG.
(F _2)). Further, the entire thickness of the SiO ₂ film 43 having the opening 44 is 1000 Å.
A poly-Si film 45 containing a small amount of impurities is formed by a low-pressure CVD method or the like ((g ₁ ) and (g ₂ ) in the figure). Then, using a resist film (not shown) as a mask, the poly-Si film
The 45, 42, 40 and the SiO ₂ films 43, 41, 39 are patterned by anisotropic etching such as RIE (FIG. (H ₁ )
(H _2)). Next, the patterned SiO ₂ films 43 and 41 are entirely removed by isotropic etching such as HF (hydrofluoric acid) to remove the storage electrode 45.
Form a. Incidentally, the poly Si film 37 to form a bit line BL ₄
The Si ₃ N ₄ film 38 that insulates the gate electrodes WL ₅ and WL ₆ from each other is not etched even if exposed to the HF solution. The storage electrode 45a becomes sectional dendritic structure (FIG. _{(I 1), (i 2} )). In addition, SiO ₂
The film 39 may be omitted. After the steps of forming (i ₁ ) and (i ₂ ), the storage electrode 45 a is heat-treated in the same manner as in the prior art to form a dielectric film 46 such as a SiO ₂ film. This is performed by forming a poly-Si film containing Si over the entire surface, the poly-Si film covers the bit line BL ₄ via the dielectric film 46 as shown in the figure, and furthermore, the surface of the storage electrode 45a having a resin-like cross section is formed. , And also into the gap between the storage electrode 45a and the Si ₃ N ₄ film 38. Thus it is possible to produce a DRAM cell having a fourth transfer transistor T ₄ and the storage capacitor C _4, as shown in FIG. In this way, the storage electrode 20a, 25a and 45a are the bit lines BL ₁ the previously formed, BL _2, BL ₃ and the insulating film for insulating BL ₄
It is provided on 18, 23 and 38. This allows the storage electrode
Even if 20a, 25a and 45a are formed three-dimensionally, bit lines BL ₁ and BL
_2, BL ₃ and it is possible to reduce the aspect ratio of the contact hole BL ₄ become. Further, the storage electrodes 20a, 25a
Three-dimensional laminated structure, by the storage electrode 45a and the cross-sectional dendritic structure, it is possible to increase the storage electrode area, therefore it is possible to increase several times as compared to the storage capacitor C ₄ to the conventional. Further, according to the manufacturing method of the embodiment of the present invention, the SiO ₂ film 3
9, 41, 43 and poly-Si films 40, 42, 4 containing impurity ions
5 is repeated N times, and the SiO ₂ films 39, 41, 43 and the poly-Si films 40, 42, 45 that have been repeated N times are patterned, and then N times are continued. SiO ₂ films 39, 41,
By removing only 43 by isotropic etching, it becomes possible to form the storage electrode 45a having a cross-sectional tree structure. [Effects of the Invention] As described above, according to the present invention, after a film between an insulating film on a bit line and a storage electrode on the insulating film is selectively etched to form a gap, a plurality of memories are formed. A counter electrode that is made of a conductor that supplies a common electrode potential to the cell in common, and covers the bit line via the insulating film, and opposes the upper, side, and lower surfaces of the storage electrode via a dielectric film. Because of this, the capacitance of the memory cell capacitor can be greatly increased by the counter electrode wrapped under the storage electrode, the soft error due to α-ray incidence, etc. is greatly reduced, and the bit line interference is reduced. And the reliability of the memory characteristics of the DRAM cell can be improved. Therefore, a semiconductor memory device such as a DRAM cell suitable for high integration and ultra-miniaturization can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural diagram of a DRAM cell according to a first reference example, FIG. 2 is a structural diagram of a DRAM cell according to a second reference example, and FIG. FIG. 4 is a structural diagram of a DRAM cell formed by an embodiment of a method of manufacturing a semiconductor memory device according to the present invention. FIG. 5 is a structural diagram of a DRAM cell according to the first embodiment. FIG. 6 is a cross-sectional view showing a DRAM cell manufacturing process, FIG. 6 is a cross-sectional view showing a DRAM cell manufacturing process according to a third reference example, and FIG. 7 is an embodiment according to the semiconductor memory device manufacturing method of the present invention. Sectional drawing which shows the manufacturing process of the DRAM cell of an example, FIG. 8 is explanatory drawing of the DRAM cell which concerns on a prior art example. (Description of symbols) T, T ₁ through T ₄ ...... transfer transistors, C, C ₁ -C ₄ ...... storage capacitor, 1,11,31 ...... Si substrate (semiconductor substrate), 2,12,32 ...... field oxide film, 3,13,33 ...... drain (impurity diffusion layer), 4,14,34 ...... source (impurity diffusion layer), 15 ...... Si ₃ N ₄ film or SiO ₂ film (insulating film), 6 , 20a, 25a, 45a ... storage electrode, 7,21,26,46 ... dielectric film, 8,22,27,47 ... counter electrode, 9 ... PSG film, 10 ... bit line contact hole , 18,23,35,39,41,43 …… SiO ₂ film (insulating film), 38 …… Si ₃ N ₄ film (heat-resistant oxidizing insulating film), 17,20,25,37,40,42, 45: Poly-Si film (conductor film), 19, 24: Opening (storage electrode contact part), 16, 36: Opening (source contact part), WL, WL _{1 to} WL _6: Word line (Gate electrode), BL, BL _{1 to} BL ₄ , BL _{21 to} BL ₂₃ ... Bit lines.

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor memory device having a plurality of memory cells each including a transfer transistor having a pair of impurity diffusion layers and a gate electrode, and a storage capacitor connected to the transfer transistor, the transfer transistor is formed on a semiconductor substrate. Forming a first insulating film covering the transfer transistor; and connecting a bit line connected to one of the pair of impurity diffusion layers through an opening formed in the first insulating film to the first insulating film. Forming a second insulating film covering the bit line; covering the second insulating film with a film made of a different material from the second insulating film; Forming a first conductor film connected to the other of the impurity diffusion layers on the film, and patterning at least the first conductor film into a shape of a storage electrode; Selectively forming a gap between the storage electrode and the second insulating film, forming a dielectric film on the surface of the storage electrode, extending into the gap, Forming a second conductor film facing the upper surface, side surface, and lower surface of the storage electrode as a counter electrode through the dielectric film while covering the bit line via a second insulating film. Manufacturing method of a semiconductor memory device. 2. 2. The method according to claim 1, wherein the film is silicon oxide, the second insulating film is silicon nitride, and the second conductor film is silicon.