JPH09232537A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method capable of eliminating the layout including the defective alignment of lithography in relation to a semiconductor and its manufacturing method. SOLUTION: The first insulating film 2, a conductive film 3, the second insulating film 4 and a semiconductor layer to be an active region 5 are provided on a substrate 1 and simultaneously, a conductive material electrically connecting to one of the source drain region 9 of an insulating gate field-effect transistor self-matching a sidewall 7 provided on the side of a gate electrode 6 of said transistor provided on the active region 5 to be further buried in a trench 8 reaching the conductive film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a 1Tr-1C type D.
RAM (Dynamic Random Access Memory)
The present invention relates to a semiconductor device using a buried bit line and a method of manufacturing the same in order to improve the degree of integration.

[0002]

2. Description of the Related Art Conventionally, the structure of a DRAM is 1Tr.
The -1C type is generally used, but in order to improve the degree of integration of this DRAM, it is necessary to reduce the occupied area per cell and integrate as many cells as possible into one chip.

In such a DRAM, when the charge stored in the memory cell is read out, the charge is shared with the bit line. However, since the bit line also has a parasitic capacitance, the charge information of the memory cell becomes small. Therefore, there is a problem that it becomes difficult to read information.

To solve this problem, it is sufficient to reduce the bit line capacitance, and as one method therefor, a method of reducing the number of cells connected to the sense amplifier through one bit line can be considered. In this case, there is a drawback that the number of sense amplifiers becomes too large and the chip area is increased in a large capacity DRAM.

Therefore, in order to improve the degree of integration of a large capacity DRAM, it is necessary to reduce the bit line capacity itself without increasing the chip area. However, this bit line capacity depends on the bit line and cell plate. Since the wiring interlayer capacitance between the electrodes and the wiring interlayer capacitance between the bit lines and the word lines occupy most of them, in order to reduce the bit line capacitance itself, the bit lines, the word lines, and the cell plate can be reduced. It is necessary to make the distance to other wiring layers such as lines sufficiently large.

A DRAM for enabling such a request
As a cell structure, an SOI (Silicon on I) is manufactured by using a silicon substrate bonding technique and a selective polishing technique.
It is proposed to embed a bit line under the (insulator) layer (if necessary, JP-A-4-118967, JP-A-4-237131, and JP-A-4-324).
No. 660), this embedded bit line type DRAM will be described with reference to FIGS. 6 and 7.

First, referring to FIG. 6A, the p-type silicon substrate 4 is formed.
1 is oxidized to form a SiO ₂ film 42 having a thickness of about 1 μm, and a deep groove 43 reaching the inside of the p-type silicon substrate 41.
Then, the groove 43 is filled with P (phosphorus) -doped polycrystalline Si by a CVD method to form a buried conductive layer 44, and then a polycide film is provided thereon and patterned to form a bit line 45. To do.

Next, referring to FIG. 6B, TEOS is formed on the entire surface.
(Tetra-Ethyl-Ortho-Silica
After the SiO ₂ film 46 is formed by the CVD method using te) and the surface is flattened, the silicon support substrate 47 is bonded, and then the p-type silicon substrate 41 is placed on the back surface side until the embedded conductive layer 44 is exposed. Then, the single crystal element region 48 is formed by polishing.

Next, referring to FIG. 7, an element isolation insulating film 49 is formed in the single crystal element region 48, and a gate oxide film 50 is formed in the other regions. At this time, since polycrystalline Si is more easily oxidized than single crystal Si, an oxide film thicker than the gate insulating film 50 is formed on the surface of the buried conductive layer 44, and P in the buried conductive layer 44 is solid phased. One of the source / drain regions 52 is formed by diffusion.

Next, a polycrystalline Si film is deposited and patterned to form a word line gate electrode 51.
After forming S, the other of the source / drain regions 53 is formed by ion implantation of P, and then S which becomes an interlayer insulating film is formed.
An iO ₂ film 54 is deposited, a storage electrode 55 made of n ⁺ -type polycrystalline Si is provided, which is connected to the source / drain region 53 through a contact hole provided in the SiO ₂ film 54, and then a dielectric film 56 is formed. After being provided, a common cell plate electrode 57 made of a metal film is provided, and the storage electrode 55 /
A storage capacitor composed of the dielectric film 56 / cell plate electrode 57 is formed.

With such a structure, the distance between the bit line 45 and the word line also serving as the gate electrode 51, or the distance between the bit line 45 and the cell plate electrode 57 is set to the SiO ₂ film 42. , And the parasitic capacitance, that is, the bit line capacitance, is reduced because it increases through the single crystal element region 48.

[0012]

However, in the conventional buried bit line type DRAM, after the buried conductive layer 44 connecting the bit line 45 and the cell transfer transistor is formed in advance, the buried conductive layer 44 is formed in the buried conductive layer 44. Although the gate electrode 51 is provided so as to be aligned as much as possible, when patterning the gate electrode 51, it is necessary to have a layout that includes a lithography alignment error, which is suitable for manufacturing a fine large-capacity DRAM. It wasn't a structure.

Therefore, according to the present invention, the embedded bit line type D
An object of the present invention is to provide a structure and a manufacturing method that do not require a layout including a lithography alignment error when forming a semiconductor device such as a RAM.

[0014]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. See FIG. 1 (1) The present invention provides a first semiconductor device on a substrate 1.
The insulating film 2, the conductive film 3, the second insulating film 4, and the semiconductor layer to be the active region 5, and the side portion of the gate electrode 6 of the insulated gate field effect transistor provided on the active region 5. A conductive material 10 which is self-aligned with the sidewall 7 and which reaches the conductive film 3 and which is electrically connected to one of the source / drain regions 9 of the insulated gate field effect transistor. It is characterized by that.

As described above, since the conductive material 10 electrically connected to one of the source / drain regions 9 of the insulated gate field effect transistor is embedded in the groove self-aligned with the sidewall 7, the gate electrode 6 is formed. Since the alignment with the groove 8 is completely unnecessary, it is not necessary to consider the alignment error due to the lithography, and the integration degree is improved.

(2) According to the present invention, in the above (1), the conductive film 3 forms a bit line, and the gate electrode 6 of the insulated gate field effect transistor forms a word line.
A storage capacitor is connected to the other of the source / drain regions of the insulated gate field effect transistor.

When such a wiring structure is applied to a DRAM, the distance between the conductive film 3 forming the bit line and the gate electrode 6 forming the word line, and the conductive film 3 forming the bit line. The distance between the cell plate electrode and the cell plate electrode that constitutes the storage capacitor can be increased, whereby a DRAM having a small bit line capacitance can be configured.

(3) In the method of manufacturing a semiconductor device according to the present invention, an element isolation insulating film is formed on the surface of a silicon substrate, a silicon oxide film is formed on the entire surface, and then the conductive film 3 and silicon oxide are formed. After sequentially depositing films, this silicon substrate and another substrate 1 are bonded together, and the back surface of the silicon substrate is polished to make it a thin layer, thereby forming the active region 5.
Then, a sidewall 7 is formed on a side portion of the gate electrode 6 of the insulated gate field effect transistor provided on the active region 5, and then the trench 8 reaching the conductive film 3 is formed by using the sidewall 7 as a mask. Is formed, and a conductive material 10 electrically connected to one of the source / drain regions 9 of the insulated gate field effect transistor is buried in the groove 8.

As described above, the groove 8 for burying the conductive material 10 electrically connected to one of the source / drain regions 9 of the SOI type insulated gate field effect transistor is formed.
Since the sidewalls 7 are formed in a self-aligned manner using the masks, the alignment between the gate electrode 6 and the groove 8 is completely unnecessary, and it is not necessary to consider the alignment error due to lithography, and the integration degree is improved.

(4) According to the present invention, in the above (3), when the conductive material 10 is embedded in the groove 8, the conductive material 10 is deposited on the entire surface and then reactive ion etching is performed. The conductive material 10 is formed into a sidewall shape.

In this way, the conductive material 1 to be embedded in the groove 8
Even when 0 is patterned to form the connection electrode, it is possible to perform the maskless patterning by using the reactive ion etching, and consider the alignment error due to the lithography when patterning the conductive material 10. It is not necessary and the degree of integration is further improved.

(5) Further, in the present invention according to the above (3) or (4), the conductive film 3 constitutes a bit line, and the gate electrode 6 of the insulated gate field effect transistor constitutes a word line. A storage capacitor is connected to the other of the source / drain regions of the insulated gate field effect transistor.

By applying the method of manufacturing such a wiring structure to the DRAM, the conductive film 3 forming the bit line is formed.
And the gate electrode 6 forming the word line, and the distance between the conductive film 3 forming the bit line and the cell plate electrode forming the storage capacitor can be increased, whereby the bit line capacitance can be increased. Highly integrated DRAM
Can be manufactured.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a manufacturing process of a first embodiment of the present invention will be described with reference to FIGS. 2A, first, the element isolation oxide film 12 is formed by selectively oxidizing the silicon substrate 11 using a silicon nitride film pattern (not shown) provided via a pad oxide film as a mask.
Next, after removing the silicon nitride film pattern and the pad oxide film, a SiO ₂ film having a thickness of about 0.5 μm is deposited on the entire surface by the CVD method, and then the thickness on the element isolation oxide film 12 is reduced to 0.3. By polishing to 0.4 μm, for example, 0.3 μm, the SiO ₂ film 13 having a flat surface is formed.

Then, using a CVD method, the impurity concentration is 1 × 10 ^{21 to} 5 × 10 ²¹ cm ⁻³ , for example, 3 × 10 ²¹ c.
m ⁻³ and the thickness is 0.1 to 0.3 μm, for example, 0.2
P-doped n ⁺ -type polycrystalline Si having a thickness of 0.1 μm to 0.35 μm is formed by patterning it.
For example, the bit line 14 of 0.15 μm is formed.

Next, the SiO ₂ film 15 is deposited by the CVD method using TEOS to make the surface flat, and the SiO ₂ film 15 is superposed on the silicon supporting substrate 16 and heat-treated at a high temperature of 600 to 1000 ° C., for example, 850 ° C. The silicon substrate 11 and the silicon support substrate 16 are firmly bonded together.

Next, referring to FIG. 2B, the device isolation oxide film 12 is formed on the back surface of the silicon substrate 11.
By polishing until it is exposed to a thin layer, a single crystal element region 17 having a thickness of 0.1 to 0.2 μm, for example, 0.1 μm is formed.

Next, referring to FIG. 3C, the surface of the single crystal device region 17 surrounded by the device isolation oxide film 12 is thermally oxidized to a gate oxide film having a thickness of 4.0 to 10.0 nm, preferably 4.0 nm. After forming the film 18, a polycrystalline S having a thickness of 100 to 200 nm, for example, 150 nm is formed.
The gate electrode 19 and the SiN film 20 are formed by sequentially depositing and patterning i and a SiN film having a thickness of 10 to 100 nm, for example, 20 nm.

Next, using the gate electrode 19 as a mask, A
After forming the source / drain regions 21 by ion implantation of s, a SiN film having a thickness of 30 to 70 nm, for example, 50 nm is deposited on the entire surface, and RIE (reactive ion etching) using CHF ₃ + CF ₄ as a reaction gas is performed. ) Is used to form the sidewall 22 made of a SiN film on the sidewall of the gate electrode.

Next, as shown in FIG. 3D, a resist is applied to the resist pattern 2 having a rough precision such that an opening is formed between the two gate electrodes 19.
3 to form the resist pattern 23 and the SiN film 2
0 and the exposed silicon layer using the sidewall 22 as a mask, that is, one of the source / drain regions 21 and the SiO ₂ film 13 thereunder are etched by RIE using CHF ₃ as a reaction gas, Bit line 14
Forming a groove 24 reaching

Next, referring to FIG. 4E, P-doped n ⁺ type polycrystalline Si is deposited on the entire surface to fill the groove 24, and then RI is used with HBr as a reaction gas.
By etching the n ⁺ -type polycrystalline Si with E, the sidewall-shaped connection electrode 25 is formed.

The connection electrode 25 is connected to one of the source / drain regions 22, and the side wall-shaped n ⁺ -type polycrystalline Si remains on the side part of the side wall 22 on the opposite side. Will be done.

Next, referring to FIG. 4 (f), a thickness of 0.3 to 0.5 is formed on the entire surface by the CVD method.
A SiO ₂ film 26 having a thickness of, for example, 0.5 μm is deposited as an interlayer insulating film, and then a contact hole reaching the other of the source / drain regions 21 is formed.

Next, P-doped n ⁺ type polycrystalline Si is formed on the entire surface.
And then etched back to form a polycrystalline Si plug 27 embedded in the contact hole.

Next, P-doped n ⁺ -type polycrystalline Si having a thickness of 10 to 30 nm, for example, 20 nm is deposited on the entire surface and then patterned to form a storage electrode 28 constituting a storage capacitor.

Next, as a dielectric film 29, a SiO ₂ film having a thickness of 3 to 6 nm, for example, 4 nm is deposited on the entire surface, and then the common cell plate electrode 30 has a thickness of 200 to 5
Embedded bit line DRAM by depositing P-doped n ⁺ -type polycrystalline Si of 00 nm, for example 300 nm
The basic composition of is completed.

As described above, in the first embodiment of the present invention, the buried bit line type D utilizing the conventional SOI structure is used.
Similar to the RAM, since the distance between the bit line 14 and the gate electrode 19 serving as the word line or the distance between the bit line 14 and the cell plate electrode 30 can be increased, the bit line capacitance is significantly increased. Since it is possible to read even with a small amount of accumulated charge,
There is no problem even if the cell is miniaturized.

Further, in the first embodiment of the present invention, the sidewall 22 provided on the sidewall of the gate electrode 19 is provided.
Since the groove 24 for reaching the bit line 14 and self-aligning with the side wall 22 and for burying the connection electrode 25 is formed by using, it is necessary to consider the alignment error due to lithography. Since it is eliminated, the manufacturing process can be simplified and the cell can be miniaturized.

Further, when patterning the connection electrode 25, since etching is performed by using RIE, it is not necessary to consider a positioning error due to lithography, which simplifies the manufacturing process and further reduces the size of the cell. Becomes possible.

Next, the second and third embodiments of the present invention will be briefly described with reference to FIG. Refer to FIG. 5A. FIG. 5A shows a known open bit line structure D for the wiring structure and the manufacturing method according to the first embodiment of the present invention.
FIG. 2 is a schematic plan view when applied to a RAM, showing a bit line contact 34 for connecting the bit line 31 and one of source / drain regions forming a transistor region 32 and two word lines 33. Capacitor contacts 35 for connecting the other of the source / drain regions forming the transistor region 32 between them to the storage electrode are periodically formed.

Also, FIG. 5B shows a case where the wiring structure and the manufacturing method of the first embodiment of the present invention described above are applied to a DRAM of the same known folded bit line structure. FIG. 3 is a schematic plan view of a memory cell, in which a combination of a transistor region 32, a bit line contact 34, and two capacitor contacts 35, that is, memory cells are alternately dispersed and periodically arranged. .

As described above, in any of the bit line structures, in the present invention, since the bit line region is previously formed as the buried layer, it is necessary to provide the wiring layer for the bit line in the cell. Instead, the degree of integration is improved.

In the description of the embodiment of the present invention, P-doped polycrystalline Si is used as the bit line, but the bit line is not limited to P-doped polycrystalline Si.
It may be doped polycrystalline Si, amorphous Si doped with P or As, polycide, or a conductive film of Ti, W, TiN, or the like.

Further, as the dielectric film 29, SiO is used._TwoUse membrane
However, SiN film and Ta_TwoO _FiveFilm, TiO_Twofilm,
SrTiO_ThreeMembrane, BaTiO_ThreeMembrane and BaSrTi
O_ThreeIt is also possible to use a ferroelectric film such as a film.
And Ta_TwoO_FiveFilm, TiO_TwoMembrane, SrTiO_ThreeMembrane, Ba
TiO_ThreeMembrane and BaSrTiO_ThreeA dielectric film such as a film
When used, the storage capacity can be increased.

In the above embodiment, the source / drain regions are formed using the gate electrode 19 as a mask, but the present invention is not limited to such a form.
After forming a shallow low-resistance source / drain region using the gate electrode 19 as a mask, a sidewall 22 is formed, and then a deep source / drain is formed using the sidewall 22 as a mask to form a so-called LDD (Lightl).
(y Doped Drain) structure may be used.

Further, in the above-described embodiment, when the substrates are bonded together, Si is formed on the surface of the silicon supporting substrate 16.
Although the O ₂ film is not formed, the SiO ₂ film may be formed on the surface of the silicon supporting substrate 16 and then the substrates may be bonded together. Further, an insulating substrate such as a quartz substrate may be used as the supporting substrate. It is a thing.

In the description of the embodiment of the present invention, the 1Tr-1C type DRAM is explained. Although such a DRAM is a typical example of the embodiment of the present invention, the present invention is not limited to the DRAM. The present invention is not limited to the above, and is also applied to SRAM (Static Random Access Memory) and general semiconductor devices, in particular, local wiring of MOS type semiconductor integrated circuit devices (Local Interconnect), and in any case, The basic technical idea of the present invention is that a deep groove reaching the buried wiring layer is provided in a self-aligning manner by etching using the side wall, and the connection electrode is provided in the groove.

Further, according to the present invention, by using RIE when patterning the connection electrode provided in the groove,
Another feature is that the sidewall-shaped connection electrode is formed in self-alignment with the sidewall.

[0049]

According to the present invention, since the buried bit line structure is used, the bit line capacitance can be reduced, and the gate electrode side portion can be formed when the connection electrode connected to the bit line is formed. Since it is formed in a self-aligned manner by using the sidewall provided in, it can be processed accurately without including the alignment margin associated with lithography.
It is possible to manufacture a buried bit line type DRAM having a high degree of integration.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of a manufacturing process according to second and third embodiments of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process up to the middle of a conventional embedded bit line DRAM.

FIG. 7 is an explanatory diagram of the manufacturing process of the conventional embedded bit line type DRAM after FIG. 6;

[Explanation of symbols]

1 Substrate 2 First Insulating Film 3 Conductive Film 4 Second Insulating Film 5 Active Region 6 Gate Electrode 7 Sidewall 8 Groove 9 Source / Drain Region 10 Conductive Material 11 Silicon Substrate 12 Element Isolation Oxide Film 13 SiO ₂ Film 14 bit line 15 SiO ₂ film 16 silicon support substrate 17 single crystal element region 18 gate insulating film 19 gate electrode 20 SiN film 21 source / drain region 22 sidewall 23 resist pattern 24 groove 25 connection electrode 26 SiO ₂ film 27 polycrystalline Si Plug 28 Storage electrode 29 Dielectric film 30 Cell plate electrode 31 Bit line 32 Transistor region 33 Word line 34 Bit line contact 35 Capacitor contact 41 p-type silicon substrate 42 SiO ₂ film 43 groove 44 Embedded conductive layer 45 Bit line 46 SiO ₂ Membrane 47 Silicon Supporting substrate 48 single crystal device region 49 element isolation insulating film 50 a gate insulating film 51 gate electrode 52 source and drain regions 53 the source and drain regions 54 SiO ₂ film 55 storage electrode 56 dielectric layer 57 cell plate electrode

Claims (5)

[Claims] 1. A first insulating film, a conductive film, and a second film on a substrate.
Of the insulating film and the semiconductor layer to be the active region, self-aligned with the sidewall provided on the side of the gate electrode of the insulated gate field effect transistor provided on the active region, and A semiconductor device, wherein a conductive material electrically connected to one of the source / drain regions of the insulated gate field effect transistor is provided in the groove reaching the film. 2. The conductive film constitutes a bit line, the gate electrode of the insulated gate field effect transistor constitutes a word line, and the other of the source / drain regions of the insulated gate field effect transistor is formed. 2. The semiconductor device according to claim 1, wherein the storage capacitor is connected to. 3. An element isolation insulating film is formed on the surface of a silicon substrate, a silicon oxide film is formed on the entire surface, and then a conductive film and a silicon oxide film are sequentially deposited, and then the silicon substrate and another substrate. And a back surface of the silicon substrate is polished to form a thin layer to form an active region, and then a sidewall is formed on a side portion of a gate electrode of an insulated gate field effect transistor provided on the active region. Is formed, a trench reaching the conductive film is formed using the sidewall as a mask, and a conductive material electrically connected to one of the source / drain regions of the insulated gate field effect transistor is formed in the trench. A method for manufacturing a semiconductor device characterized by being embedded. 4. When burying the conductive material in the groove, the conductive material is deposited on the entire surface, and then reactive ion etching is performed to form the conductive material into a sidewall shape. The method for manufacturing a semiconductor device according to claim 3. 5. The conductive film forms a bit line, the gate electrode of the insulated gate field effect transistor forms a word line, and the source / drain region of the insulated gate field effect transistor is formed on the other side. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the storage capacitor is connected.