JP3416929B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor as an information storage unit such as a dynamic RAM (DRAM).

[0002]

2. Description of the Related Art In recent years, with the trend toward higher integration of LSIs, the area of elements has been reduced. Therefore, in a DRAM composed of one transistor and one capacitor, the area of a capacitor serving as an information storage section has been reduced. As a result, the memory function of information is impaired. Therefore, there has been proposed a device that does not reduce the capacitance of the capacitor even if the element area is reduced. For example, JP-A-6-204402 and JP-A-7-153.
No. 916 Bulletin and Symposium on BUILS Technology Digest of Technical.
Papers (Symposium on VLSI Technology Digest of
Micro paper patterning technology for 256 mega hits described in Technical papers)
Dynamic RAM / Stack cell (Micro Villus PAt
terning (MVP) Technology for 256Mb DRAM Stack cell
), A micro pillar beyond the resolution of photolithography technology is formed on the capacitor electrode,
A capacitor structure has been proposed in which the capacitance is increased by increasing the effective surface area of the capacitor electrode.

FIG. 6 is a sectional view showing the steps of manufacturing a memory cell of a DRAM of this type. O. B (Capacito
A memory cell having an r Over Bit-Line structure will be described as an example. First, in FIG. 6A, 1 is a P-type silicon substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is an n-type diffusion layer, 5 is a silicon dioxide film, 6 is a BPSG film, 7 is a bit line, Reference numeral 8 is a BPSG film, and 9 is a silicon dioxide film, which is configured as a known MOS transistor.
Then, the silicon dioxide film 9, the BPSG film 8,
6, a contact hole 10 reaching the n-type diffusion layer 4 is opened over the silicon dioxide film 5, a P (phosphorus) -doped polysilicon film 11 and a silicon dioxide film 12 are sequentially stacked, and a desired photolithography technique is used. Formed in a pattern to obtain a capacitor electrode. After that, an amorphous silicon film is deposited on the entire surface and annealed to form a silicon film (Hemi-Spherical Grained s) having hemispherical grains.
Silicon, hereinafter referred to as HSG silicon film) 13 is formed.

Next, as shown in FIG.
The SG silicon film 13 is entirely etched back to expose a part of the silicon dioxide film 12 in a portion corresponding to the concave portion of the hemispherical grain. Further, the silicon dioxide film 12
Of silicon dioxide film 13 by advancing the etching of
Are patterned according to the hemispherical grains, and then the surface portion of the polysilicon film 11 is anisotropically etched using the patterned silicon dioxide film 12 as a mask to form a plurality of pillars as shown in FIG. The protrusion 23 is formed.

Thereafter, as shown in FIG. 7B, wet etching is performed to remove the silicon dioxide film 12 by etching to obtain a capacitor electrode 24. Further, a silicon nitride film 21 is deposited on the surface and a conductive film is formed on the silicon nitride film 21 to form a plate electrode 22. As a result, a capacitor using the peripheral surfaces of the plurality of columnar protrusions 23 formed on the capacitor electrode 24 is formed, and a capacitor having a large facing area and an increased capacitance can be obtained.

[0006]

In such a conventional structure, since the HSG silicon film 13 used as a mask for forming the columnar protrusions 23 of the capacitor electrode has mixed grains of different sizes, the columnar protrusions are mixed. 23 varies in size. Therefore, the mechanical strength of the extremely small columnar projection is poor, and for example, when the mask silicon dioxide film 12 is removed by wet etching,
The cleaning process for removing particles causes breakage of the columnar protrusions, which causes a reduction in yield. Further, in order to further increase the capacitance of the capacitor, it is necessary to make the height of the columnar projections 23 higher. However, if the height of the columnar projections 23 is made larger, the mechanical strength of the columnar projections 23 is reduced accordingly. Therefore, it becomes difficult to realize a sufficient capacitor capacity.

In this respect, the above-mentioned Japanese Patent Laid-Open No. 6-204402
In the technique described in the publication, a technique is proposed in which a grain of an HSG silicon film is used, and a recess is formed in a capacitor electrode by using an insulating film buried in the recess of the grain as a mask to increase the surface area. However, in this technique, the insulating film as a mask has a thin film thickness around the grains, and therefore, when the capacitor electrode is etched, HS is used.
As the etching of the G silicon film progresses, the shape of the insulating film as a mask collapses, it is difficult to function as a suitable mask when forming a recess, and it is difficult to form a recess having a desired size. Actually, it is difficult to realize an electrode having a plurality of recesses.
Further, it is difficult to secure a sufficient capacity when the element is further miniaturized by simply forming the concave portion.

An object of the present invention is to provide a semiconductor device having a capacitor structure capable of increasing the capacitance while increasing the mechanical strength of the capacitor electrode, and a manufacturing method thereof.

[0009]

The semiconductor device of the present invention comprises:
A capacitor including a first conductive film, a capacitive insulating film deposited on the surface of the first conductive film, and a second conductive film deposited on the surface of the capacitive insulating film is formed. In the semiconductor device having the above, a plurality of well-shaped recesses are formed on the surface of the first conductive film from the surface to the lower surface, and a hemispherical surface is formed on the surface of the first conductive film including the inner surface of the recesses. A silicon film having a grain shape is formed. The plurality of recesses are formed to a depth that does not reach the lower surface of the first conductive film, and the first conductive films are connected to each other around each of the recesses. is there. In addition, the plurality of recesses are independently formed on the surface of the first conductive film.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first conductive film on an insulating film formed on a semiconductor substrate, and a hemispherical grain on the surface of the first conductive film. Forming a silicon film; anisotropically etching the silicon film to form an island pattern; and using the island pattern as a mask to shallowly etch the surface of the first conductive film to form the island pattern. Forming a shallow groove in a region other than the pattern; forming a film on the first conductive film; etching the island pattern and part of the film to remove the film in the shallow groove; Including a step of burying a plurality of recesses, a step of etching the surface of the first conductive film using the coating film as a mask to form a plurality of recesses on the surface of the first conductive film, and an inner surface of the plurality of recesses. First
And a step of depositing a capacitive insulating film on the surface of the conductive film, and a step of depositing a second conductive film on the capacitive insulating film. Here, after forming a plurality of well-shaped recesses on the first conductive film, a second silicon film having hemispherical grains is formed on the surface of the first conductive film including the surfaces of the plurality of recesses. It is preferable to include a step of forming and depositing the capacitance insulating film and the second conductive film on the surface of the second silicon film.

In the semiconductor device of the present invention, a plurality of well-shaped recesses are formed in the surface of the first conductive film to a depth that does not reach the lower surface of the first conductive film. The above
HSG silicon films each having a hemispherical grain are formed on the inner surface of each of the recesses and are connected to each other around the periphery of each of the recesses. Since the capacitor opposed to the second conductive film is formed, the first conductive film is connected around the recess .
Ri, while mechanical strength of the capacitor electrodes can be improved, can be increased opposing area of the capacitor by hemispherical grains of the inner surface of the well-shaped recesses, it is possible to secure a sufficient capacitance.

In the manufacturing method of the present invention, an HSG silicon film is used to form an island pattern with the first film,
With this island pattern, a shallow groove is formed on the surface of the first conductive film, a second film is buried in the shallow groove, and then the first conductive film is etched using the second film as a mask. Since the well-shaped recess is formed as a result, the mask shape does not collapse during etching of the first conductive film, and the recess having a desired shape can be reliably formed. Therefore, the method of the present invention is also effective when manufacturing the semiconductor device having the above-described conventional configuration. Further, the present invention can be manufactured by directly utilizing the conventional manufacturing technique.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a DRAM having a capacitor structure of the present invention. FIG. 2 is a sectional view of the manufacturing process, which will be described below according to the manufacturing process. First, in FIG. 2A, the element isolation region 2 is formed on the silicon substrate 1.
Is formed to partition the element region, and then a MOS transistor having an impurity-doped region 4 and a gate electrode 3 for controlling a current flowing between the impurity-doped regions 4 is formed in the element region. Then, a first insulating film 5 made of CVD silicon dioxide or the like and B for covering the surface of the gate electrode 3 is formed.
After forming the second insulating film 6 such as a PSG film, a contact hole 10 reaching a part of the impurity-doped region 4 is opened in each of the first and second insulating films 5 and 6, and the contact hole 10 is formed. The bit line 7 is formed of a conductive film such as aluminum connected to the impurity-doped region 4 through, and a third insulating film 8 such as a BPSG film and a fourth insulating film 9 such as a silicon dioxide film are further formed thereon. Form. Then, a first conductive film 11 made of a P (phosphorus) -doped polysilicon film is formed thereon, and a first coating film 12 made of a silicon dioxide film is further formed thereon by a CVD method to about 50.
About 0Å is deposited, and then the first conductive film 11 and the first coating 12 are simultaneously processed into a desired pattern by a photoetching technique.

Next, as shown in FIG. 2B, an amorphous silicon film 80 is formed on the entire surface including the first coating film 12.
After growing about 0Å to 1200Å, for example, annealing is performed in an N ₂ atmosphere at about 550 ° C. for about 20 minutes. As a result, fine hemispherical irregularities are formed on the surface of the amorphous silicon film, and as a result, the second coating 13 made of the HSG silicon film is formed.

Next, as shown in FIG. 3 (a), anisotropic dry etching is performed on the second coating 13 to leave convex and concave portions on the HSG silicon film as the second coating. The recess is etched in this state to expose a part of the first coating film 12. Further, by continuing the anisotropic dry etching, the first coating film 1 is formed.
2 is selectively etched, and as a result, a large number of island-shaped patterns 14 having a minute circle corresponding to the convex portions of the HSG silicon film 13 are formed as shown by the hatched lines in FIG. The size of the island-shaped pattern 14 formed at this time is about 0.1 to 0.2 μm.

Subsequently, as shown in FIG. 3B, the surface of the first conductive film 11 is etched and removed to a depth of about 500Å to 1000Å using the island pattern 14 as a mask. At this time, the HSG silicon film 13 on the surface side forming the island pattern 14 is simultaneously removed by etching. By this etching, the surface of the first conductive film 11 is
Short-cylindrical protrusions are left in the shaded portions in FIG. 5A, and the other region has a shallow groove 15. Then, a third coating 16 of 0.1 μm is formed on the front surface.
A silicon dioxide film having a thickness of about 0.15 μm is deposited by, for example, a low pressure CVD method (hereinafter referred to as an LPCVD method), and the shallow groove 1 formed on the surface of the first conductive film 11 is deposited.
5 is completely buried.

Subsequently, as shown in FIG. 4 (a), the third coating 16 and the first coating are subjected to full-face etching back to completely remove the first coating 12. As a result, the third film 16 is left on the surface of the first conductive film 11 only in the shallow groove 15. That is, as shown by hatching in FIG. 5B, the reverse pattern 17 in which the third coating film 16 is left only in the pattern region where the island pattern is reversed.
Are formed, and the surface of the first conductive film 11 is exposed in other regions. At this time, depending on the etching conditions, as shown in FIG. 4A, the second and third coatings 13 and 16 are left on the side surface of the first conductive film 11.

Then, as shown in FIG. 4B, the first conductive film 11 is anisotropically dry-etched using the inversion pattern 17 as a mask, and the surface of the first conductive film is exposed to 0.
A large number of circular well-shaped recesses 18 having an inner diameter of 1 μm to 0.2 μm are formed. Then, the third coating and the second coating are wet-etched to completely remove the third coating and the second coating. Thus, a surface portion in the non-hatched region removed in FIG. 5 (b), the capacitor electrode 19 made of the first conductive film in a state of being connected to each other by the shaded region. Therefore, the surface area of the capacitor electrode 19 is increased only by the inner surface of the well-shaped recess 18.

Thereafter, as shown in FIG. 1, annealing is performed at about 550 ° C. in an N ₂ atmosphere to form the HSG silicon film 20 on the inner wall of the well-shaped recess 18 of the capacitor electrode. Thereby, on the inner surface of the well-shaped recess 18,
Furthermore, since the HSG silicon film 20 has irregularities made of grains, the surface area of the inner surface of the recess 18 is increased. Then, a silicon nitride film is deposited on the surface of the first conductive film 11 including the well-shaped recess 18 by a CVD method to form a capacitive insulating film 20, and a second conductive film is further deposited thereon. Then, the plate electrode 21 is formed. As a result, in the area including the inner surface of the well-shaped recess 18, the capacitor electrode 19 and the plate electrode 21 are arranged to face each other with the capacitance insulating film 20 interposed therebetween, thereby forming a capacitor.

As is clear from the above description of the steps, the first coating film 12 functions as a stopper when the second coating film 13 having irregularities is etched back, and therefore the second coating film 13 is formed. It is desirable that the first coating film 12 and the third coating film 3 have a high selection ratio with respect to the first conductive film. Further, the first coating film 12 and the third coating film 16 need to have low selection ratios to each other, and are preferably made of the same kind of material. The same applies to the second coating 13 and the first conductive film 11. This makes it possible to simultaneously remove the island-shaped first coating film 12 by etching when forming the recesses on the surface of the first conductive film 11, and similarly to form the third coating film 16. At this time, the first coating film 12 located on the convex portion of the first conductive film 11 can be simultaneously removed by etching, and the process is simplified.

In the structure of the capacitor of the present invention thus constructed, the capacitor electrode 19 formed of the first conductive film 11 has a so-called honeycomb shape in which a large number of cylindrical recesses are formed on the surface thereof. Therefore, unlike the conventional capacitor electrode composed of columnar protrusions, there is no reduction in strength such as breakage of the columns. Therefore, when the HSG silicon film 13 as the second coating has a mixture of large and small grains, well-shaped recesses 18 having a small diameter are only formed at the fine grains.
The strength of the capacitor electrode is not reduced. Also,
Looking at the capacitance of the capacitor, it is the same as the conventional technique in that the inner peripheral surface of the well-shaped recess 18 along the grain diameter of the HSG silicon film is used, and the capacitance can be increased. .

Here, according to the study by the present inventor, HSG
The size of the island pattern 14 made of a silicon film is
Well-shaped recess 18 of capacitor electrode 19 which will be formed later
However, if the diameter is too large, it is difficult to form the capacitance insulating film 20 and the plate electrode 21 on the inner surface of the well-shaped recess 18 if the diameter is too large. Therefore, the diameter dimension is preferably in the range of 0.05 μm to 1 μm, and more preferably in the range of 0.08 μm to 0.2 μm.

In the above embodiment, the present invention is a DRAM.
It shows an example of forming on the capacitor electrode of
The present invention is not limited to M, and the present invention can be similarly applied when forming a capacitor having a fine area in a semiconductor device.

[0024]

As described above, according to the present invention, a plurality of well-shaped recesses are formed in the surface of the first conductive film to a depth that does not reach the lower surface of the first conductive film. The conductive films of No. 1 are connected to each other around each of the recesses , and an HSG silicon film having hemispherical grains is formed on the inner surface of each of the recesses.
Secondly, through a capacitive insulating film on the surface including each inner surface.
Since the capacitor is formed so as to face the conductive film of, the first conductive film is connected around the recess, thereby improving the mechanical strength as the capacitor electrode and the well-like structure. The facing area as a capacitor can be increased by the hemispherical grains on the inner surface of the concave part of
It is possible to secure a sufficient capacitor capacity. Further, in the manufacturing method of the present invention, an HSG silicon film is used to form an island pattern with the first coating, and the island pattern forms a shallow groove on the surface of the first conductive film. Since the second conductive film is embedded in the first conductive film and the second conductive film is used as a mask to etch the first conductive film to form a well-shaped recess, a mask shape is formed when the first conductive film is etched. It is possible to surely form a concave portion having a desired shape without breaking. Furthermore, in the manufacturing method of the present invention,
Since the process provided conventionally can be used, it becomes possible to easily manufacture a high-strength and high-capacity capacitor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a first cross-sectional view showing the manufacturing method of the present invention in the order of steps.

FIG. 3 is a second cross-sectional view showing the manufacturing method of the present invention in the order of steps.

FIG. 4 is a third sectional view showing the manufacturing method of the present invention in the order of steps.

FIG. 5 is a plan view showing a surface structure during a manufacturing process.

FIG. 6 is a first sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 7 is a second cross-sectional view showing the method of manufacturing the conventional semiconductor device in the order of steps.

[Explanation of symbols]

1 Silicon substrate 3 Gate electrode 4 Impurity doped region 5,6,8,9 Insulation film 7 bit line 10 contact holes 11 First conductive film 12 First coating 13 Second coating (HSG silicon film) 14 island pattern 15 shallow groove 16 Third film 17 inversion pattern 18 Well-shaped recess 19 Capacitor electrode 20 HSG silicon film 21 Capacitive insulating film 22 Plate electrode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinya Iwasa               5-7 Shiba 5-chome, Minato-ku, Tokyo NEC               Within the corporation                (56) References JP-A-7-202023 (JP, A)                 Japanese Patent Laid-Open No. 10-275901 (JP, A)

Claims (5)

(57) [Claims] 1. A first conductive film, a capacitive insulating film deposited on the surface of the first conductive film, and a second conductive film deposited on the surface of the capacitive insulating film. In a semiconductor device having a configured capacitor, the surface of the first conductive film has a depth in which a plurality of well-shaped recesses from the surface to the lower surface do not reach the lower surface of the first conductive film. And the first conductive film is connected to each other around each of the recesses, and a hemispherical surface is formed on the surface of the first conductive film including the inner surface of each of the recesses. A semiconductor device having a silicon film formed thereon. 2. The semiconductor device according to claim 1, wherein the plurality of recesses are independently formed on the surface of the first conductive film. 3. A first and a second formed on a semiconductor substrate.
An impurity-doped region and a gate electrode for controlling a current flowing through the first and second impurity-doped regions.
An S transistor and an insulating film covering the surface of the MOS transistor are provided, and the first conductive film extends from the first impurity-doped region to a surface of the insulating film through a hole opened in the insulating film. 3. The first conductive film, the capacitance insulating film, and the second conductive film form a capacitor, and the MOS transistor forms a dynamic transistor of one transistor and one capacitor. The semiconductor device according to. 4. A step of forming a first conductive film on an insulating film formed on a semiconductor substrate, a step of forming a first coating film on a surface of the first conductive film, and the first step. Forming a silicon film having hemispherical grains on the film, forming an island pattern by anisotropically etching the silicon film and the first film, and using the island pattern as a mask. A step of shallowly etching the surface of the first conductive film to form a shallow groove in a region other than the island pattern; a step of forming a second film on the first conductive film; and the island pattern. Etching a part of the second coating to bury the second coating in the shallow groove; etching the surface of the first conductive film using the second coating as a mask; Forming a plurality of well-shaped recesses on the surface of the first conductive film And a step of depositing a capacitive insulating film on the surface of the first conductive film including the inner surfaces of the plurality of recesses, and a step of depositing a second conductive film on the capacitive insulating film. A method for manufacturing a characteristic semiconductor device. 5. After forming a plurality of recesses on the surface of the first conductive film, a second silicon film having hemispherical grains is formed on the surface of the first conductive film including the surfaces of the plurality of recesses. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of forming and depositing the capacitance insulating film and the second conductive film on the surface of the second silicon film.