JPH0878640A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a DRAM which has a COB(Capacitor Over Bitline) structure without increasing the number of processes. CONSTITUTION: A pad polycrystalline silicon film 18 for diffusing impurity on a substrate 12 is provided on a field shield element isolating structure 1 between bit lines 8, and provide a storage contact 5. Thus, film thickness increase or three-dimensional structure of a storage electrode 6 is allowed without influencing the bit lines 8 or a bit contact 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, for example, a COB (capacitor over) in which a storage electrode is formed above a bit line.
It is particularly suitable when applied to a DRAM having a Bit-line structure.

[0002]

2. Description of the Related Art Conventional DR having a stack type cell structure
In the AM, the cell layout as shown in FIG. 9 which is in conformity with the folded bit line method capable of canceling the noise between the bit lines is widely used.

This conventional DRAM is shown in FIGS.
Will be described with reference to. In this example, element isolation is performed by the field shield element isolation method.

FIG. 9 is a schematic plan view showing a cell layout of a DRAM, FIG. 10 is a sectional view taken along line XX of FIG. 9, and FIG. 11 is a sectional view taken along line XI-XI of FIG. Is.

As shown in FIGS. 9 to 11, a field shield element isolation structure 101 is formed on a P-type silicon substrate 112.
And the field shield element isolation structure 10 is formed.
In the element regions separated by 1, the gate electrode wiring 103 of the memory cell forming the word line and the gate electrode 110 of the peripheral transistor are formed via the gate oxide film 113, respectively. Then, the drain diffusion layer 102 and the source diffusion layer 11 are sandwiched with the gate electrode wiring 103 interposed therebetween.
9 are formed respectively, and a pad polycrystalline silicon film 104 used as a diffusion source of impurities of the respective diffusion layers is formed on the surfaces of the drain diffusion layer 102 and the source diffusion layer 119.

As shown in FIGS. 10 and 11, the drain diffusion layer 102 of each memory cell is connected to the storage electrode 106 via the pad polycrystalline silicon film 104 and the storage contact 105, and the storage electrode 106.
Above the capacitor insulating film 111 and the cell plate electrode 109.
Are formed respectively.

On the other hand, as shown in FIG. 10, the source diffusion layer 119 is shared by the two gate electrode wirings 103, that is, two memory cells, and via the pad polycrystalline silicon film 104 and the bit contact 107. , The bit line 108 formed above the cell plate electrode 109
It is connected to the.

As shown in FIG. 9, the bit contact 10
7 is a bit line 10 in the direction along the word line 103.
Every other eight lines are arranged, and in the direction along the bit line 108, every four word lines 103 are arranged.

According to the arrangement of the bit contacts 107, the storage contacts 105 are arranged so as to be aligned in the direction along the word line 103, as shown in FIGS. 9 and 11. On the other hand, in the direction along the bit line 108, as shown in FIGS.
07, storage contact 105, field shield element isolation structure 101 and adjacent storage contact 1
05 are arranged in this order.

In this configuration, the storage contact 10
5, the space for expanding the storage electrode 106 formed immediately above the substrate 5 in plan view and increasing the cell capacity is no longer substantially present.

Therefore, recently, the height of the storage electrode 106 has been increased in order to secure a sufficient cell capacity in accordance with the reduction in cell size. As a result, as shown in FIG.
However, it is becoming difficult to form wiring such as aluminum by the usual sputtering method. Therefore, instead of the aluminum wiring, a polycide structure which is process-stable against heat treatment has been used for the bit line 108.

In particular, when the field shield element separation method is used, compared to the case of the normal LOCOS method,
Since the height of the element isolation region is more than doubled, the bit line 10
The application of the polycide structure to 8 is essential.

[0013]

In the above-mentioned conventional cell layout, the only way to secure a sufficient cell capacity in accordance with the reduction in cell size is to increase the height of the storage electrode 106. It was As a result, the aspect ratio of the bit contact 107 is increased, and in order to maintain the reliability of the connection, a polycide wiring, a buried plug technique using polycrystalline silicon or tungsten has been used.

However, since the polycrystalline silicon layer used for the polycide wiring can be doped with only N-type impurities in general, the polycide wiring is applied only to the wiring connected to the bit contact 107 and the peripheral N-type conductive layer. Can not.

Also, regarding the buried plug, when polycrystalline silicon is used, it is used only for the bit contact 107 and the peripheral N-type conductive layer.

On the other hand, in the case of a buried plug using tungsten that can be connected to both conductive type conductive layers, titanium nitride, which is a barrier metal and is used to enhance the adhesion of CVD of tungsten, is formed by the sputtering method. Therefore, there is a problem that connection reliability is low for a contact having a high aspect ratio.

Further, in the current process, in order to reduce the aspect ratio of the peripheral contact 120 at least, a step is formed at the boundary between the cell array portion and the peripheral portion by using BPSG reflow, and the interlayer insulation of the peripheral portion is performed. Membrane 11
5 is made as thin as possible.

However, due to the recent intensification of the reduction in cell size, the height of the storage electrode 106 becomes remarkable, and the level difference at the boundary between the cell array portion and the peripheral portion tends to become worse. On the other hand, with respect to the bit lines 108 arranged for each cell pitch, the finer the resolution in photolithography, the smaller the margin in the depth of focus. As a result, the problem that the bit line 108 drawn from the cell array portion to the peripheral portion is likely to cause a resolution defect in the step portion between them is becoming apparent.

Therefore, an object of the present invention is that the step between the cell array portion and the peripheral portion does not pose a problem with respect to the bit line,
Moreover, it is an object of the present invention to provide a semiconductor memory device having a cell layout capable of increasing the memory cell capacity and a method of manufacturing the semiconductor memory device.

[0020]

In order to solve the above problems, according to the present invention, in a semiconductor memory device having a memory cell composed of a transistor and a capacitor, two memory cells adjacent to each other in the bit line direction are provided. One impurity diffusion layer of the transistor is shared to form a memory cell pair, each memory cell pair is isolated from the other memory cell pair by a field shield element isolation structure, and each memory cell pair is The second pad formed on the other impurity diffusion layer of the transistor of each memory cell pair is in contact with the bit line immediately above the one impurity diffusion layer via the first pad polycrystalline silicon film. A pad polycrystalline silicon film is formed to extend over the field shield element isolation structure adjacent to the word line direction. Pad polycrystalline silicon film are in contact with the lower electrode of the capacitor of the field shield element memory cells each at a position immediately above the isolation structure,
The lower electrode is formed in a layer above the bit line.

In one aspect of the present invention, in each memory cell pair, the pair of second pad polycrystalline silicon films are opposite to each other in the direction along the word line from the impurity diffusion layer to which they are connected. Is formed to extend.

In one aspect of the present invention, the first pad polycrystalline silicon film forming a bit contact has two second pad polycrystalline silicon films interposed therebetween in a direction along a word line. The bit contacts composed of the first pad polycrystalline silicon film are arranged with four word lines in between in the direction along the bit lines.

A method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming a field shield element isolation structure having a predetermined pattern on a semiconductor substrate, and an element region isolated by the field shield element isolation structure on the semiconductor substrate. A step of forming a gate electrode wiring which is a word line through a gate insulating film, covering the gate electrode wiring with a cap insulating film and a sidewall insulating film, and separating the sidewall insulating film from the field shield element isolation structure. A step of exposing the semiconductor substrate in a portion between and, a step of forming a polycrystalline silicon film on the entire surface, a step of introducing into the polycrystalline silicon film an impurity of a conductivity type opposite to that of the semiconductor substrate, The polycrystalline silicon film is patterned to include a contact portion between the polycrystalline silicon film and the semiconductor substrate. A first pad polycrystalline silicon film,
Forming a second pad polycrystalline silicon film including a contact portion between the polycrystalline silicon film and the semiconductor substrate and extending from the contact portion to a relatively large extent on the field shield element isolation structure; A step of forming an interlayer insulating film on the entire surface; a step of diffusing the impurities from the first and second polycrystalline silicon film portions into the semiconductor substrate; and a portion on the first polycrystalline silicon film. Forming a first opening in the interlayer insulating film, and patterning a bit line connected to the first polycrystalline silicon film through the first opening on the first insulating film. And a step of covering the bit wiring with a cap insulating film and a sidewall insulating film, and a portion immediately above the field shield element isolation structure and above the second polycrystalline silicon film. Forming a second opening in the interlayer insulating film, patterning a capacitor lower electrode connected to the second polycrystalline silicon film through the second opening, and forming a capacitor lower electrode on the capacitor lower electrode. And a step of forming a capacitor insulating film, and a step of forming a capacitor upper electrode facing the capacitor lower electrode via the capacitor insulating film.

In one aspect of the present invention, the sidewall insulating film of the bit line is used as at least a part of an etching mask when forming the second opening.

[0025]

In the present invention, the bit line is formed below the storage electrode which is the lower electrode of the capacitor by forming the storage contact on the field shield element isolation structure between the bit lines. Therefore, with respect to the bit line, a step between the cell array portion and the peripheral portion does not occur, and problems such as poor resolution of the bit line do not occur. Further, since the bit line is formed below the storage electrode, the plane area of the storage electrode can be increased more than before without being obstructed by the bit contact. Further, it is possible to increase the height of the storage electrode and increase the cell capacitance without being bothered by the problem of the step of the bit line, and it is also possible to adopt a fin type three-dimensional structure as the capacitor structure. .

Further, in the manufacturing method of the present invention, a pad polycrystalline silicon film used as a diffusion source of impurities is used to form a storage contact on the field shield element isolation structure.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
2 is a schematic plan view showing the layout of FIG.
-II is a schematic sectional view taken along the line, FIG. 3 is a schematic sectional view taken along the line III-III of FIG. 1, FIG. 4 is a schematic plan view showing the layout of the pad silicon film corresponding to FIG. 1, and FIG. FIG. 2 is a schematic plan view showing a layout of memory cells corresponding to FIG. 1.

As shown in FIG. 2, a P-type silicon substrate 12
A field shield element isolation structure 1 is formed thereon, and in the element regions isolated by the field shield element isolation structure 1, the gate electrode wiring of the memory cell forming the word line 3 and the gate electrode 10 of the peripheral transistor are respectively gate-oxidized. It is formed via the film 13. Then, in each memory cell region, an N-type drain diffusion layer 2 and a source diffusion layer 17 are formed so as to sandwich the word line 3 therebetween, thereby forming an access transistor of the memory cell. In the peripheral transistor region, N-type source / drain diffusion layers 20 of the peripheral transistor are formed so as to sandwich the gate electrode 10 therebetween.

As shown in FIGS. 2 to 4, on the surface of the drain diffusion layer 2 and the source diffusion layer 17 of each memory cell and the source / drain diffusion layer 20 of the peripheral transistor,
Pad polycrystalline silicon films 18, 4 and 19 are formed respectively. These polycrystalline silicon films 18, 4 and 19 are
It is used as a diffusion source of impurities in each of the diffusion layers 2, 17 and 20, and through the opening defined by the AC sidewall 24 of the field shield element isolation structure 1 and the sidewall 27 of the word line 3, P-type silicon is formed. Board 12
Is in direct contact with.

As shown in FIG. 2, each source diffusion layer 17
Is shared by the gate electrodes of the two access transistors arranged in the direction along the bit line 8,
It is connected to the bit line 8 via the pad polycrystalline silicon film 4 and the bit contact 7. That is, each source diffusion layer 17 is shared by two memory cells arranged in the direction along the bit line 8, and these memory cells form a memory cell pair that shares the bit contact 7 (FIG. 5).

As shown in FIGS. 1 and 2, the bit line 8
Are drawn out of the cell array region and are connected to the source / drain diffusion layers 20 of the peripheral transistors forming a column decoder or the like via the pad polycrystalline silicon film 19. At this time, as shown in FIG. 2, since the bit line 8 is formed below the storage electrode 6 of each memory cell, the bit contact 7 in the cell array portion can be formed as shallow as the bit contact 7 in the peripheral portion. With
Since there is no step difference in the bit line 8 between the cell array portion and the peripheral portion, it is possible to prevent the resolution failure of the bit line 8 from occurring when forming the bit line 8.

As shown in FIGS. 2 and 3, the drain diffusion layer 2 of each memory cell has a storage electrode 6 formed above the bit line 8 via the pad polycrystalline silicon film 18 and the storage contact 5. Is connected to the storage electrode 6, and the ONO capacitance insulating film 11 having a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film is formed on the storage electrode 6.
Cell plate electrode 9 made of a polycrystalline silicon film via
Are formed.

As shown in FIGS. 3 and 4, the pad polycrystalline silicon film 18 formed on each drain diffusion layer 2 is
The storage contact 5 is formed so as to extend from above each drain diffusion layer 2 to above the field shield element isolation structure 1 adjacent in the word line direction, and the storage contact 5 is formed immediately above the field shield element isolation structure 1. As a result, as shown in FIGS. 1 and 4, the storage contact 5 is arranged in the gap region formed between the word line 3 and the bit line 8. Also, at this time, FIG. 4 and FIG.
As shown in, the pair of pad polycrystalline silicon films 18 of each memory cell pair are formed so as to extend in directions opposite to each other in the direction along the word line 3. As a result, as shown in FIG. 5, the memory cell pairs can be densely arranged in the direction oblique to the direction of the word lines 3 and the bit lines 8.

As shown in FIGS. 4 and 5, the pad polycrystalline silicon film 4 is formed in the direction of 2 along the word line 3.
The pad polycrystalline silicon films 18 are arranged in between, and in the direction along the bit line 8, four word lines 3 are arranged in between. As a result, as shown in FIG. 1 and FIG. 4, the bit contact 7 in the cell array portion is, in the direction along the bit line 8,
Four word lines are sandwiched in between, and three bit lines 8 are sandwiched in the direction along the word line 3.

In the structure of this embodiment, since the storage electrode 6 of each memory cell can be formed in a layer above the bit line 8 and a so-called COB structure can be formed, the bit line 8 and the bit contact can be formed. The plane area of the storage electrode 6 can be enlarged without being disturbed by 7. This means that conversely, it is possible to narrow the interval between the bit lines 8 without reducing the memory cell capacity, and thereby miniaturization and high integration of the memory cell array are achieved. .

Further, according to the structure of this embodiment, the aspect ratio of the bit contact 7 becomes large in the cell array portion, and the step difference of the bit line 8 becomes large at the boundary portion between the cell array portion and the peripheral portion. The storage electrode 6 can be made three-dimensional without inviting. That is, the effective area of the capacitor can be increased by forming the storage electrode 6 into a three-dimensional structure such as a thick film, a cylinder, a fin, and unevenness.

Further, each bit line 8 is connected to a cell plate electrode 9
Since it has such a structure as to cover, there is also an advantage that interference noise between bit lines can be eliminated.

Next, a method of manufacturing the structure described with reference to FIGS. 1 to 5 will be described with reference to FIGS. 2 and 6 to 8. 6 to 8 are schematic cross-sectional views corresponding to FIG. 3, respectively.

First, as shown in FIG. 6A, the entire surface of the P-type silicon substrate 12 has a thickness of 40 by thermal oxidation.
A pad oxide film 21 of -60 nm is formed. Next, a phosphorus-doped polycrystalline silicon film 22 having a thickness of 150 to 200 nm and a cap oxide film 23 having a thickness of 250 to 300 nm are formed on the pad oxide film 21 by the LPCVD method or the like. Next, an element region and an element isolation region are formed by photolithography and an anisotropic dry etching technique, leaving the polycrystalline silicon film 22 and the cap oxide film 23 only in the portion to be the element isolation region.

Next, as shown in FIG. 6B, LPCV
After depositing a silicon oxide film having a thickness of 250 to 300 nm on the entire surface by the D method or the like, the polysilicon oxide film 22 and the cap oxide film 23 are etched back by using an anisotropic dry etching technique. The AC sidewall 24 is formed on the side wall, and the field shield element isolation structure is formed on the silicon substrate 12.

Next, as shown in FIG. 2, the gate oxide film 13 is formed on the silicon substrate 12 in the element region by the thermal oxidation method.
Then, a polycrystalline silicon film and a cap insulating film made of a silicon oxide film are formed on the entire surface by a CVD method or the like, and these are patterned by photolithography and anisotropic dry etching techniques to form the word line 3.
And its cap insulating film. Next, using the pattern of the word lines 3 and the field shield element isolation structure as a mask, N-type impurities such as arsenic are ion-implanted into the silicon substrate 12 at a low concentration to form an N ⁻ impurity diffusion layer having an LDD structure. Next, a silicon oxide film is deposited on the entire surface by the LPCVD method or the like, and is etched back using the anisotropic dry etching technique to form the sidewall 27 on the side wall of the word line 3. This time,
The gate oxide film 13 between the AC sidewalls 24 of the field shield element isolation structure and between the AC sidewalls 24 and the sidewalls 27 of the word lines 3 is removed,
The silicon substrate 12 in that portion is exposed.

Next, as shown in FIG. 6C, a non-doped polycrystalline silicon film is formed on the entire surface by the CVD method or the like. Next, an N-type impurity such as phosphorus is introduced into this polycrystalline silicon film by an ion implantation method or the like. Note that N-type impurities may be introduced at the same time when the polycrystalline silicon film is deposited. Thereafter, this polycrystalline silicon film is patterned into a shape as shown in FIG. 4 to form pad polycrystalline silicon films 4 and 18, respectively.

At this time, the pad polycrystalline silicon films 4 and 18 are formed.
2 and 6 (c), between the AC sidewalls 24 of the field shield element isolation structure and AC
The sidewall 24 and the sidewall 27 of the word line 3
It is formed in a state of being in direct contact with the silicon substrate 12 through an opening formed in a self-aligned manner. Also, FIG.
As shown in FIG. 6C, the pad polycrystalline silicon film 18 is formed so as to extend onto the cap oxide film 23 of the field shield element isolation structure.

Next, as shown in FIG. 7A, the normal pressure CV
BPSG as the first interlayer insulating film 14 by the D method or the like
A film is formed on the entire surface. Then, a heat treatment at 850 to 900 ° C. is performed to flatten the surface of the BPSG film and, at the same time, N contained in the pad polycrystalline silicon films 4 and 18 is processed.
The type impurities are diffused into the silicon substrate 12 through the contact portion to form a high-concentration N type impurity diffusion layer that is an LD ⁺ structure N ⁺ impurity diffusion layer and a contact implanter at the same time. In this embodiment, the drain diffusion layer 2 and the source diffusion layer 17 of the memory cell and the source / drain diffusion layer 20 of the peripheral transistor are formed by the N ⁻ impurity diffusion layer and the N ⁺ impurity diffusion layer of the LDD structure ( Figure 2
reference). When the source / drain of the memory cell and the peripheral transistor is not of the LDD structure, the low concentration N-type impurity is not ion-implanted into the silicon substrate 12, and the impurity from the pad polycrystalline silicon films 4 and 18 is removed. It is also possible to form each source / drain diffusion layer only by diffusion. In that case, the channel length can be controlled by controlling the lateral diffusion of the impurities.

Next, a portion of the first interlayer insulating film 14 corresponding to the pad polycrystalline silicon film 4 is opened by photolithography and anisotropic dry etching technique to form the bit contact 7.

Next, a polycrystalline silicon film doped with impurities is formed on the entire surface by the CVD method or the like, and then tungsten silicide is formed on the entire surface by the sputtering method or the CVD method, and then by the CVD method or the like. , A cap silicon nitride film 15 is formed on the entire surface. Thereafter, the bit lines 8 having a polycide structure are formed by patterning them by using photolithography and anisotropic dry etching technology.

Next, as shown in FIG. 7B, a silicon nitride film is deposited on the entire surface by a CVD method or the like, and this is etched back to form sidewalls 25 on the sidewalls of the bit lines 8. .

Next, as shown in FIG. 7C, only the region including the bit contact 7 is covered with the photoresist 26 and wet or dry etching is performed to open the first interlayer insulating film 14. The storage contact 5 is formed. At this time, the sidewall 25 of the bit line 8 which is a silicon nitride film acts as an etching mask, and the storage contact 5 is formed in self-alignment with this.

Next, as shown in FIG. 8A, after removing the photoresist 27, a polycrystalline silicon film doped with impurities is deposited on the entire surface by a CVD method or the like, and photolithography and anisotropy are performed. This is patterned by the dry etching technique to form the storage electrode 6.

Next, as shown in FIG. 8B, the ONO capacitance insulating film 11 and the cell plate electrode 9 are formed on the entire surface of the cell array portion.

Thereafter, as shown in FIGS. 2 and 3, a BPSG film which is the second interlayer insulating film 16 is formed on the entire surface.

In the manufacturing method of this embodiment described above,
One pad polycrystalline silicon film 18 which is a diffusion source of impurities into the silicon substrate 12 is extended to above the field shield element isolation structure 1 to thereby store the data directly above the field shield element isolation structure 1 between bit lines. The contact 5 is formed and the storage electrode 6 is formed above the bit line 8.

[0054]

According to the present invention, since the bit line is formed in a layer lower than the storage electrode or cell plate electrode of each memory cell, the height of the storage electrode can be increased or the storage electrode can be made three-dimensional. Even if the cell capacity is increased, the aspect ratio of the bit contact in the cell array portion does not increase, and since no step is formed in the bit line between the cell array portion and the peripheral portion, the resolution failure of the bit line does not occur.

As a means for bringing the storage contact of each memory cell to the position between the bit lines, a pad polycrystalline silicon film which is a diffusion source of impurities into the substrate is used. No components or members of

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a layout of a DRAM according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view taken along the line II-II of FIG.

3 is a schematic cross-sectional view taken along the line III-III in FIG.

FIG. 4 is a schematic plan view corresponding to FIG. 1 in a portion of a pad polycrystalline silicon film.

FIG. 5 is a schematic plan view corresponding to FIG. 1, showing a layout of a memory cell.

FIG. 6 is a schematic cross-sectional view corresponding to FIG. 3, showing a method of manufacturing a DRAM according to an embodiment of the present invention in process order.

FIG. 7 is a schematic cross-sectional view corresponding to FIG. 3, showing a method of manufacturing a DRAM according to an embodiment of the present invention in process order.

FIG. 8 is a schematic cross-sectional view corresponding to FIG. 3, showing a method of manufacturing a DRAM according to an embodiment of the present invention in process order.

FIG. 9 is a schematic plan view showing a cell layout of a conventional DRAM.

10 is a schematic cross-sectional view taken along line XX of FIG.

11 is a schematic cross-sectional view taken along line XI-XI of FIG.

[Explanation of symbols]

 1 field shield element isolation structure 2 drain diffusion layer (N type diffusion layer) 3 word line (gate electrode wiring) 4, 18 pad polycrystalline silicon film 5 storage contact 6 storage electrode 7 bit contact 8 bit line (polycide wiring) 9 cell Plate electrode 10 Peripheral transistor gate electrode 11 ONO capacitance insulating film 12 P-type silicon substrate 13 Gate oxide film 14 First interlayer insulating film (BPSG) 15 Cap nitride film 16 Second interlayer insulating film (BPSG) 17 Source diffusion layer (N type) Diffusion layer 20 Peripheral transistor source / drain diffusion layer 21 Pad oxide film 22 Polycrystalline silicon film 23 Cap oxide film 24 AC sidewall 25 Bit line sidewall (silicon nitride film) 27 Word line sidewall

Claims (5)

[Claims] 1. In a semiconductor memory device having a memory cell including a transistor and a capacitor, two memory cells adjacent in the bit line direction share one impurity diffusion layer of each transistor to form a memory cell pair. Each memory cell pair is element-isolated from the other memory cell pair by the field shield element isolation structure, and each memory cell pair is formed on the first pad polycrystalline silicon film immediately above the one impurity diffusion layer. A second pad polycrystalline silicon film formed on the other impurity diffusion layer of the transistor of each memory cell pair, respectively.
The second pad polycrystalline silicon films formed to extend above the field shield element isolation structure adjacent to each other in the word line direction, and these second pad polycrystalline silicon films are located directly above the field shield element isolation structure and below the capacitors of the respective memory cells. A semiconductor memory device, wherein the semiconductor memory device is in contact with an electrode, and the lower electrode is formed in a layer above the bit line. 2. In each memory cell pair, a pair of the second pad polycrystalline silicon films are formed so as to extend from the impurity diffusion layers connected to each other in the directions opposite to each other in the direction along the word line. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 3. The first pad polycrystalline silicon film forming a bit contact is arranged in a direction along a word line with two second pad polycrystalline silicon films interposed therebetween. 3. The bit contacts formed of the first pad polycrystalline silicon film are arranged with four word lines in between in a direction along the bit lines. Semiconductor memory device. 4. A step of forming a field shield element isolation structure having a predetermined pattern on a semiconductor substrate; and a word on the semiconductor substrate in an element region isolated by the field shield element isolation structure via a gate insulating film. Forming a gate electrode wiring that is a line; covering the gate electrode wiring with a cap insulating film and a sidewall insulating film; and the semiconductor substrate in a portion between the sidewall insulating film and the field shield element isolation structure. Exposing, a step of forming a polycrystalline silicon film on the entire surface, a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the polycrystalline silicon film, and a step of patterning the polycrystalline silicon film. A first pad polycrystalline silicon film including a contact portion between the polycrystalline silicon film and the semiconductor substrate, Forming a second pad polycrystalline silicon film including a contact portion between the polycrystalline silicon film and the semiconductor substrate and extending from the contact portion to a relatively large extent on the field shield element isolation structure; A step of forming an interlayer insulating film on the entire surface; a step of diffusing the impurities into the semiconductor substrate from the first and second polycrystalline silicon film portions; and a portion on the first polycrystalline silicon film. Forming a first opening in the interlayer insulating film, and patterning a bit wiring connected to the first polycrystalline silicon film through the first opening on the first insulating film. And a step of covering the bit line with a cap insulating film and a sidewall insulating film, and a position immediately above the field shield element isolation structure and on the second polycrystalline silicon film. Forming a second opening in a portion of the interlayer insulating film; patterning a capacitor lower electrode connected to the second polycrystalline silicon film through the second opening; A method of manufacturing a semiconductor memory device, comprising: a step of forming a capacitor insulating film on the capacitor; and a step of forming a capacitor upper electrode facing the capacitor lower electrode via the capacitor insulating film. 5. The manufacturing of a semiconductor memory device according to claim 4, wherein the sidewall insulating film of the bit wiring is used as at least a part of an etching mask when forming the second opening. Method.