JP3092254B2 - Dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM of the type in which a connection layer as an intermediate layer is formed at the connection of diffusion layers of bit line MOS transistors.

[0002]

2. Description of the Related Art In general, in a dynamic RAM, a memory cell section in which a plurality of memory cells are arranged in a matrix and a peripheral circuit section for processing input / output and signal timing for the memory cell section are on the same substrate. Formed on top.
In a memory cell having a folded back bit line structure of one cell and one transistor, the contact of the bit line is generally shared by a pair of cells, and between a pair of gate electrodes (word lines) extending substantially in parallel. Regions are used for bit line contacts.

In order to increase the degree of integration of memory cells, the size of the gate electrode is reduced, and the area between the gate electrodes is also reduced. Therefore, the area used for the bit line contact also becomes smaller.

On the other hand, in order to ensure an interlayer breakdown voltage between the gate electrode and the bit line or the stack type capacitor, it is necessary to make the side wall thick, so that a silicon oxide film for offset is formed on the gate electrode. Is formed. In order to planarize the memory cell portion, a low melting point glass layer is also formed as an interlayer insulating film. Therefore, due to these insulating films, a vertical step is large around the gate electrode although the bit line needs to be contacted.

On the other hand, the self-aligned contact method of the bit line is a method of forming a contact hole of the bit line in a region between a pair of gate electrodes without using a vertical alignment, without alignment of a resist layer or the like. . As in the case of the full self-aligned contact method, a polysilicon layer for connection is formed on a diffusion layer connected to a bit line, and the bit line and the diffusion layer are connected via the polysilicon layer.

[0006]

However, the problem of a vertical step similarly occurs not only in the memory cell portion but also in the peripheral circuit portion other than the memory cell portion.

In other words, even when the self-align contact is performed, the vertical step is inevitably increased in order to sufficiently secure the interlayer breakdown voltage of the memory cell portion and to flatten the memory cell portion. An insulating film having the same thickness is also formed on the peripheral circuit portion on the same substrate.

However, when a metal wiring layer such as an aluminum wiring layer is formed on the thick insulating film and connected to a wiring layer below the insulating film, a contact hole having an extremely high aspect ratio is formed. Since an electrical connection is formed by forming the insulating film on the insulating film, disconnection or the like easily occurs, and the coverage of the metal wiring layer is deteriorated.

In view of the above technical problems, an object of the present invention is to provide a dynamic RAM having a structure in which a wiring layer in a region such as a peripheral circuit portion and a wiring layer thereunder are reliably contacted.

[0010]

In order to achieve the above object, the present invention provides a dynamic RAM in which a memory cell section and a peripheral circuit section are formed on a substrate, and a wiring layer and an interlayer insulating film are formed below the wiring layer. The connection layer of the peripheral circuit portion having another wiring layer electrically connected to the wiring layer via the connection layer via the connection layer is electrically connected to the bit line and the diffusion layer constituting the memory cell portion. It is formed in a self-aligned manner by the same conductive layer as the plug layer for making a proper connection.

Here, a contact hole is formed in the interlayer insulating film between the wiring layer and another wiring layer thereunder. The connection layer is formed so as to fill the contact hole. As an example, the connection layer may be left in the contact hole by self-alignment. The wiring layer is a material layer such as an aluminum-based wiring layer, but may be a polysilicon layer or the like, a high melting point metal layer or the like, or a combination thereof.

[0012]

The plug layer at the bit line contact portion is
Although it contributes to alleviation of the step in the memory cell portion, by forming a connection layer also on the peripheral circuit portion side using the same conductive layer as the plug layer, the step by the connection layer can be reduced without increasing the number of steps at all. Is alleviated, and electrical connection between the wiring layer of the peripheral circuit portion and another wiring layer thereunder is ensured.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

[Structure of Dynamic RAM] FIG. 1 shows a sectional structure of a dynamic RAM according to this embodiment. On a main surface of a p-type silicon substrate 1, a field oxide film 2 made of a thick silicon oxide film is formed as an element isolation region. On this silicon substrate 1, a memory cell section M and a peripheral circuit section P are formed.

First, regarding the structure of the memory cell section M,
Each of the nMOS transistors 3 has a structure
The S transistor 3 has a pair of n-type diffusion layers 4 and
5 The diffusion layer 4 is a diffusion layer on the side connected to the bit line, and is commonly used by a pair of memory cells. The diffusion layer 5 is a diffusion layer on the storage node side. The pair of diffusion layers 4 and 5 are separated below the gate electrode 6, and the separated portion becomes a channel region.

In each nMOS transistor 3, a gate electrode 6 is formed on the main surface of the substrate via a gate insulating film. The gate electrode 6 is a word line, and extends so as to pass over the field oxide film 2 near another memory cell adjacent in the extension direction of the word line. The gate electrode 6 has a polycide structure of a polysilicon layer and a tungsten silicide layer. The gate electrode 6 is covered with a silicon oxide film 7 composed of a sidewall and an offset oxide film.

The silicon oxide film 7 and the diffusion layers 4 and 5 are covered with an interlayer insulating film 8. The interlayer insulating film 8 includes a PSG film and a silicon nitride film. On the interlayer insulating film 8, on the diffusion layer 5,
An opening 9 is formed. The polysilicon layer 10 serving as a storage node is connected through the opening 9. The polysilicon layer 10 extends from the opening 9 along the slope of the silicon oxide film 7 and terminates on the gate electrode 6 in the cross section of the figure. On this polysilicon layer 10, a plate electrode layer 12 is formed via a dielectric film 11, and a stacked capacitor is obtained by the polysilicon layer 10, the dielectric film 11, and the plate electrode layer 12.

The polysilicon layer 10, the dielectric film 11, and the plate electrode layer 12 constituting these capacitors are covered with a BPSG film 13 for flattening. Contact hole 1
4 are formed. The contact hole 14 penetrates not only the reflowed BPSG film 13 but also the interlayer insulating film 8,
The diffusion layer 4 faces the bottom.

In the contact hole 14 of this bit line, a plug layer 15 of a relatively thick fourth polysilicon layer is formed. The plug layer 15 is a layer buried to reduce a vertical step inside the contact hole 14 of the bit line, and prevents disconnection of the bit line. In particular, the fourth polysilicon layer constituting the plug layer 15 is also used as a connection layer 20 for connecting a pair of wiring layers in the peripheral circuit portion P and is formed in the same process. Wiring in the peripheral circuit portion P can be achieved without increasing the number of lines.

The bit line 16 is formed so as to be connected to the plug layer 15 and has a pattern extending in a direction substantially perpendicular to the pattern of the gate electrode 6. Bit line 1
6 is electrically connected to the diffusion layer 4 via the plug layer 15. The bit line 16 has a polycide structure of a polysilicon layer and a tungsten silicide layer, but may have a structure shunted by an aluminum wiring layer or the like. The bit line 16 is covered with a BPSG film 17.

Next, with regard to the structure of the peripheral circuit portion P, a wiring layer 18 extending a part of the gate electrode of the MOS transistor of the peripheral circuit on the field oxide film 2 has the same interlayer insulating film as the memory cell portion M. 8 and the silicon oxide film 7, and the BPSG film 13. Then, a contact hole 19 for making a connection with the wiring layer 18 is formed, and the connection layer 20 formed by processing the fourth-layer polysilicon layer is buried in the contact hole 19 as described above. ing.

A wiring layer 21 made of the same layer as the bit line 16 is formed on the connection layer 20 so as to be disposed on the BPSG film 13.
The aluminum-based wiring layer 22 is formed on the BPSG film 17.
Is formed through a contact hole 23 formed in the contact hole.

If the connection layer 20 does not exist, the wiring layer 2
1 and the aluminum-based wiring layer 22 are formed in the contact hole 19 having a high aspect ratio, causing disconnection or the like. However, when the connection layer 20 of this embodiment is embedded in the contact hole 19, the disconnection occurs. Is prevented from occurring.

The formation of the connection layer 20 prevents the disconnection of the wiring layer. In particular, as described below,
The connection layer 20 is formed without increasing the number of steps,
This is particularly effective when high integration is achieved and the diameter of the contact hole 19 is reduced.

[Method of Manufacturing Dynamic RAM of the Embodiment] A method of manufacturing the dynamic RAM of the embodiment will be described in the order of steps with reference to FIGS.

First, a thick field oxide film 2 for element isolation is formed on the surface of a p-type silicon substrate 1 by a selective oxidation method. A region where the field oxide film 2 is not formed is defined as an element formation region. Next, a gate oxide film is formed on the substrate surface to be an element formation region, and after the gate oxide film is formed,
A first polysilicon layer and a tungsten silicide layer are formed on the entire surface, and a silicon oxide film for offset is further formed thereon. The first polysilicon layer and the tungsten silicide layer are patterned to form the gate electrode 6 and the wiring layer 18 of the MOS transistor.
It is said. At the time of this patterning, the silicon oxide film for offset is also cut in the same pattern.

Next, after patterning the gate electrode 6 and the like, ion implantation for obtaining the low concentration diffusion layers 4 and 5 is performed using the gate electrode 6 and the field oxide film 2 as a mask. After the ion implantation, an interlayer insulating film is formed on the entire surface, the interlayer insulating film is etched back to form sidewalls, and an oxide film 7 covering gate electrode 6 and wiring layer 18 is obtained.

After the formation of the silicon oxide film 7, an interlayer insulating film 8 made of a silicon nitride film and a PSG film is formed on the entire surface. This interlayer insulating film 8 has an opening 9 at the node contact portion.
The surface of the diffusion layer 5 is exposed at the bottom of the opening 9.

A second polysilicon layer 10 serving as a capacitor lower electrode is formed on the entire surface of the exposed opening 9, and is separated into patterns for each memory cell by RIE or the like. Subsequently, a dielectric film 11 having a laminated structure of a silicon nitride film and a silicon oxide film or a structure in which a silicon nitride film is sandwiched between silicon oxide films is formed on the surface of the polysilicon layer 10. Then, a plate electrode layer 12 is formed on the dielectric film 11 by using a third polysilicon layer.

After the formation of the stacked capacitor, a BPSG film 13 for flattening is formed on the entire surface.
The membrane 13 is reflowed. Then, after the reflow, as shown in FIG. 2, the contact holes 14 for the bit lines are formed by anisotropic etching using the resist layer 31 as a mask.
A contact hole 19 formed thereon is also formed. That is, the etching using the resist layer 31 removes the BPSG film 13 and the interlayer insulating film 8 in the memory cell portion M while reflecting the mask pattern, and simultaneously removes the BPSG film 13 and the interlayer insulating film 8 in the peripheral circuit portion P. And the silicon oxide film 7 is removed reflecting the mask pattern. As shown in FIG. 2, in the memory cell portion M, a contact hole 14 exposing the surface of the diffusion layer 4 is formed by etching using the resist layer 31, and in the peripheral circuit portion P, a wiring layer 18 is formed in the bottom. The contact hole 19 exposing the upper surface of the substrate is formed.

Next, after the removal of the resist layer 31, as shown in FIG. 3, a fourth polysilicon layer 32 is formed on the entire surface to a relatively large thickness by, for example, a CVD method.
The polysilicon layer 32 fills the contact hole 14 for the bit line and also fills the contact hole 19 in the peripheral circuit portion P. Therefore, even if the vertical step is severe due to the miniaturization of the element by the formation of the next plug, reliable electric connection is made, and the contact hole 19 is buried at the same time as the contact hole 14, so that only the mask change is required. There is no increase in the number of processes.

As shown in FIG. 3, a resist layer 33 is formed on the formed polysilicon layer 32. The formation position of the resist layer 33 is on the contact hole 14 of the bit line. On the other hand, the resist layer 33 is not formed on the contact hole 19 of the peripheral circuit section P.

Next, etching is performed using the resist layer 33 as a mask. In the bit line contact hole 14,
Due to the presence of the resist layer 33, the polysilicon layer 32 below the resist layer 33 is not removed, and the contact hole 1 is not removed.
4 along the pattern of the resist layer 33 from the top of
A plug layer 15 having a pattern extending on the PSG film 13 is obtained. On the other hand, since there is no resist layer in the contact hole 19 of the peripheral circuit portion P, the polysilicon layer 32 is shaved from the surface.
Since 2 is formed with a large thickness, a part thereof remains in the contact hole 19 and becomes the connection layer 20. Since no mask is required for forming the connection layer 20 in a self-aligned manner, the connection layer 20 can be formed in a self-aligned manner even in a portion where mask alignment is difficult.

Subsequently, a bit line 16 and a wiring layer 21 having a polycide structure of a polysilicon layer and a tungsten silicide layer are formed in required patterns. The bit line 16 is in contact with the diffusion layer 4 of each memory cell without being disconnected by the plug layer 15. The wiring layer 2 of the peripheral circuit portion P
1 is also securely connected to the connection layer 20 without disconnection. After the formation of the bit lines 16 and the like, the BPSG film 17 is formed on the entire surface. Further, the opening 23 of the aluminum-based wiring layer is formed in the BPSG film 17 and then the aluminum-based wiring layer 22 is formed.
Are formed in a required pattern, and a dynamic RAM is completed according to a normal process.

The dynamic RAM of the present embodiment as described above
In the manufacturing method of (1), simultaneously with the formation of the contact hole 14 of the bit line, the contact hole 19 of the peripheral circuit portion P is also formed.
1, electrical connection between the aluminum-based wiring layer 22 is made. Moreover, reliable contact in the peripheral circuit portion P does not involve any increase in the number of steps. For this reason, the process is convenient and the cost can be reduced. Further, since the connection layer 20 in the contact hole 19 can be formed by self-aligned etch-back, the connection layer 20 can be obtained even in a portion where formation of a resist layer is difficult. This is extremely effective in achieving the goal.

[0036]

According to the dynamic RAM of the present invention, a connection layer is formed also in a peripheral circuit portion and the like using the same conductive layer as a plug layer in a bit line contact portion. Therefore, the step is reduced by the connection layer without any increase in the number of steps, and electrical connection between the wiring layer in the peripheral circuit section and the other wiring layers thereunder is ensured.

Further, when the connection layer is formed in a self-aligned manner, the connection layer can be formed even for a fine contact hole.
This is advantageous when producing

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing a structure of an example of a dynamic RAM according to the present invention.

FIG. 2 is a process cross-sectional view up to the step of forming a contact hole in the manufacturing method of the example.

FIG. 3 is a process cross-sectional view up to the step of forming a resist layer in the manufacturing method of the example.

FIG. 4 is a process cross-sectional view up to the step of forming an aluminum-based wiring layer in the above-described example manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Field oxide film 3 ... nMOS transistor 4, 5 ... Diffusion layer 6 ... Gate electrode 7 ... Silicon oxide film 8 ... Interlayer insulating film 9 ... Opening 10 ... Polysilicon layer 11 ... Dielectric film 12 ... Plate Electrode layer 13 BPSG film 14 Contact hole 15 Plug layer 16 Bit line 17 BPSG film 18 Wiring layer 19 Contact hole 20 Connection layer 21 Wiring layer 22 Aluminum wiring layer 23 Opening

Claims (1)

(57) [Claims] 1. A dynamic RAM in which a memory cell portion and a peripheral circuit portion are formed on a substrate, wherein the peripheral circuit portion is disposed on a wiring layer and a layer therebelow via an interlayer insulating film, and is formed on the interlayer insulating film. And another wiring layer electrically connected to the wiring layer via a connection layer formed so as to fill the formed contact hole, wherein the connection layer is diffused with a bit line constituting the memory cell portion. A dynamic RAM formed in a self-aligned manner by the same conductive layer as a plug layer for electrically connecting layers.