JPH10289984A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which realizes flattening when forming a storage capacitor, and its manufacturing method. SOLUTION: In the storage device, a capacitor for storage which is constituted of a first conductor film 25, a first insulation film 27 formed on the first conductor film and a second conductor film 28 formed on the first insulation film is formed in a main surface side of a semiconductor board. The capacitor is formed in a first hole part 26 of the second insulation film 23, second holes 29a, 29b are formed in the second insulation film, and a third conductor films 30a, 30b are buried in the first hole and the second hole. According to this constitution, a distance between an upper surface of a third conductor film 30a buried in the first hole and an upper surface of a semiconductor board is approximately equal to a distance between an upper surface of the third conductor film 30b buried in the second hole and an upper surface of a semiconductor board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art When manufacturing a semiconductor memory device such as a DRAM having high reliability, it is necessary to reduce the number of steps in order to reduce the resistance of capacitor electrodes and wiring and to provide an inexpensive device. In particular, there are various demands for flattening the surface when performing lithography in order to widen a process margin for lithography.

A DRA having a conventional stacked capacitor
As a method of manufacturing M, a method of forming a wiring such as a bit line, forming a contact and a storage electrode for a storage electrode of a capacitor, then forming a capacitor insulating film and a counter electrode, and forming an upper layer wiring. (Eg, IEDM 95-907).

However, when the above-described manufacturing method is used, even if the counter electrode material is devised to reduce the resistance of the capacitor electrode, planarization during lithography has not been realized. Therefore, 1GDR
It is not easy to manufacture devices having fine patterns such as AM.

On the other hand, as another example of a conventional stacked capacitor, for example, “PY. Lesaicherre et al.,“ A Gbit
-scale DRAM stacked capacitor technology with ECR
MOCVD SrTiO3 and RIE patterned RuO2 / TiN storage no
des ", IEDM Technical Digest, pp. 831-834, 1994".

Hereinafter, this conventional technique will be briefly described with reference to FIG.

First, a silicon substrate 161 having a thickness of 600
A thermal oxide film 162 of nm is formed, and a contact hole is opened in the thermal oxide film 162. Subsequently, a polycrystalline silicon plug 163 is formed inside the contact hole (FIG. 35A). Next, a TiN film 164 and a RuO ₂ film 165 having a thickness of 500 nm are formed on the entire surface by sputtering (FIG. 35B). Next, RuO ₂ film 1 the island-shaped resist mask 166 using a lithography process
65, and using this as a mask, a RuO ₂ film 165 is formed.
Then, the TiN film 164 is patterned by the RIE method (FIG. 35C). Next, after subjecting the RuO ₂ film 165 to a surface treatment, the SrTiO ₃ film 1 is formed by ECRMOCVD.
67 is deposited at 450 ° C. Finally, TiN film and Al
A film 168 is formed on the entire surface by sputtering, Al is used for the plate electrode 168, SrTiO _{3 is used} for the capacitor insulating film 167,
The RuO ₂ film is used as the storage electrode 165 (Al / TiN / S
A capacitor having a laminated structure of rTiO ₃ / RuO ₂ / TiN / poly-Si) is completed (FIG. 35D).

In the above-mentioned prior art, the manufacturing process of only the storage electrode contact and the capacitor is shown, and when applied to an actual DRAM, a MOSF
A step of forming an ET, a step of forming a bit line, and the like are added, and the polycrystalline silicon plug may be considered to be connected not to the silicon substrate but to the source or drain of the MOSFET.

However, in the above-described conventional technique, the storage node conductive film is patterned using the island-shaped resist pattern as a mask to separate the storage nodes. Therefore, there is a problem that the storage nodes adjacent to each other cannot be brought closer than the limit of lithography and the effective storage node electrode area cannot be increased much.

In the prior art, when a plurality of storage node electrodes 165 are arranged in a matrix as shown in FIG. 36A, a cross-sectional view along AA 'of FIG. As shown in B), when the storage node electrode 165 is misaligned with respect to the storage node contact 163, the plate electrode 168 and the storage node contact 163 are connected to the capacitor insulating film 167.
Are formed directly opposite to each other with the capacitor interposed therebetween, and the capacitor insulating film 167 is formed by a combination of both materials.
However, there is a problem that this leads to deterioration of the capacitor characteristics, such as deterioration of the insulation property of the semiconductor device.

[0011]

As described above, there has been a problem in the prior art that flattening during lithography is difficult and that it is not easy to form a fine pattern.

In addition, it is difficult to increase the area of the storage node electrode because the distance between the storage nodes cannot be made closer than the limit of lithography, and the capacitor characteristics due to misalignment of the storage node electrode and the storage node contact. There is a problem that deterioration is likely to occur.

A first object of the present invention is to provide a semiconductor memory device capable of achieving planarization when forming a storage capacitor and a method of manufacturing the same.

A second object of the present invention is to provide a semiconductor memory device capable of achieving a large capacitor area, and having excellent electrical characteristics and reliability, and a method of manufacturing the same.

[0015]

SUMMARY OF THE INVENTION According to the present invention, there is provided a first conductive film, a first insulating film formed on the first conductive film, and a first insulating film formed on the first insulating film. In a semiconductor memory device in which a storage capacitor constituted by two conductive films is formed on a main surface side of a semiconductor substrate, the capacitor is formed in a first concave portion of a second insulating film. A second recess is formed in the second insulating film, a third conductor film is buried in the first and second recesses, and is buried in the first recess. The distance between the upper surface of the third conductive film and the upper surface of the semiconductor substrate is substantially equal to the distance between the upper surface of the third conductive film embedded in the second recess and the upper surface of the semiconductor substrate. And

Further, according to the present invention, there is provided a first conductive film, a first insulating film formed on the first conductive film, and a second conductive film formed on the first insulating film. In a semiconductor memory device in which a storage capacitor constituted by a film and a main surface of a semiconductor substrate is formed, the capacitor is formed in a first concave portion of a second insulating film. A second concave portion is formed in the film, and a third conductor film is embedded in the first concave portion and the second concave portion,
The distance between the upper surface of the second conductive film of the capacitor formed in the first concave portion and the upper surface of the semiconductor substrate is equal to the upper surface of the third conductive film embedded in the second concave portion and the semiconductor. It is characterized by being less than the distance from the upper surface of the substrate.

According to the semiconductor memory device, the resistance can be reduced by the third conductive film, and the region in which the first concave portion is formed (corresponding to the region having the capacitor) and the second conductive film are formed. Since the height of the third conductor film can be made substantially equal to the region where the concave portion is formed (corresponding to the region having no capacitor), planarization can be achieved.

Further, the present invention provides a first conductive film, a first insulating film formed on the first conductive film, and a second conductive film formed on the first insulating film. In a method for manufacturing a semiconductor memory device in which a storage capacitor composed of a film and a storage capacitor is formed on a main surface side of a semiconductor substrate, a second insulating film having a first concave portion and the second insulating film provided in the first concave portion are provided. Forming a first conductive film, forming a second concave portion in the second insulating film, forming the first conductive film,
Simultaneously embedding a third conductor film in the first concave portion and the second concave portion in which the insulating film and the second conductor film are formed. Do).

Further, the present invention provides a first conductive film, a first insulating film formed on the first conductive film, and a second conductive film formed on the first insulating film. Forming a second insulating film in a method of manufacturing a semiconductor memory device in which a storage capacitor constituted by a film is formed on a main surface side of a semiconductor substrate; Removing, burying the first conductive film in a portion where the second insulating film is selectively removed, and removing the first insulating film further selectively to remove the first conductive film. Forming a first concave portion for projecting the conductive film, forming a second concave portion in the second insulating film, and forming the first conductive film;
A first insulating film and a second conductor film formed on the first insulating film;
And a step of burying a third conductive film in the concave portion and the second concave portion at the same time (hereinafter referred to as a manufacturing method B).

In this case, another insulating film is provided below the second insulating film, and the second insulating film is selectively removed (etched).
Then, it may be used as a stopper for etching when forming the first concave portion.

According to the semiconductor memory device manufacturing methods A and B, the third conductor film is buried in the first concave portion and the second concave portion at the same time, so that the resistance can be reduced without increasing the number of manufacturing steps. And a region where the first concave portion is formed (corresponding to a region having a capacitor) and a region where the second concave portion is formed (corresponding to a region having no capacitor)
Since the heights of the third conductor film can be made substantially equal in the cases (1) and (2), planarization can be achieved, and
A process margin in lithography can be increased.

In the above-described manufacturing methods A and B, in the manufacturing method A, after the step of forming the second insulating film having the first concave portion and the first conductor film provided in the first concave portion, In the manufacturing method B, after the step of forming the first concave portion for projecting the first conductor film by further selectively removing the second insulating film, the first insulating film and the second Forming a second conductive film, and selectively removing the second conductive film, the first insulating film, and the second insulating film to form a second concave portion in the second insulating film. Forming the third conductor film, removing the third conductor film, the second conductor film, and the first insulating film by a predetermined thickness after forming the third conductor film. The first conductive film, the first insulating film, and the second conductive film on which the first conductive film is formed. Parts and may be a step of filling the second recess and at the same time the third conductive film.

Further, in the above-mentioned manufacturing method A, the second
Is formed of an insulating film X and an insulating film Y on the insulating film X to form a second insulating film having the first concave portion and the first conductor film provided in the first concave portion. Forming the insulating film X, selectively removing the insulating film X, and burying the first conductor film in a portion where the insulating film X is selectively removed. A step of forming the insulating layer Y on the insulating film X and the first conductor film; and selectively removing the insulating film X and the insulating film Y to form the first conductor. Forming the first concave portion having the film formed thereon.

In the above-mentioned manufacturing method A, the first
Forming the second insulating film having the first concave portion and the first conductive film provided in the first concave portion by forming the first conductive film; and forming the first conductive film. Forming the second insulating film so as to cover the first insulating film; and selectively forming the first concave portion in which the first conductive film is formed by selectively removing the second insulating film. May be performed.

In the above-mentioned manufacturing method A, the first
Forming the second insulating film having the concave portion and the first conductor film provided in the first concave portion by the first conductive film, the first insulating film, and the second conductive film. Forming a body film, forming the second insulating film so as to cover the second conductive film, and selectively removing the second insulating film to form the first conductive film. Forming a first concave portion on which a film, the first insulating film, and the second conductor film are formed. The present invention also provides a third insulating film formed on the main surface side of the semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, A fourth conductive film formed on an insulating film and in contact with the first contact, and a region on the third insulating film where the fourth conductive film is not formed are selectively formed with a uniform thickness. And a fourth insulating film covering the first insulating film.

Further, according to the present invention, there is provided a third insulating film formed on a main surface side of a semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, A fourth conductive film formed on a third insulating film and in contact with the first contact; and a fourth conductive film on the third insulating film.
A fourth insulating film selectively covering a region where the conductive film is not formed with a uniform thickness, and a fifth insulating film formed on the fourth conductive film and the fourth insulating film. Membrane and this fifth
And a fifth conductive film formed on the insulating film.

In the above invention, the semiconductor device may further include a MOS transistor formed on the main surface side of the semiconductor substrate and surrounded by an element isolation film, wherein the first contact is connected to one of a source and a drain of the MOS transistor. It is preferred that

In the invention, a second contact formed in the third insulating film and connected to the other of the source and the drain of the MOS transistor, and a bit line connected to the second contact It is preferable to further have

The present invention also relates to a MOS transistor formed on a semiconductor substrate and surrounded by an element isolation film.
A sixth insulating film formed on the main surface of the semiconductor substrate on which the OS transistor is formed, and a sixth insulating film formed in the sixth insulating film and connected to one of a source and a drain of the MOS transistor. A second contact, a bit line formed on the sixth insulating film and connected to the second contact, and a seventh insulating film formed on the sixth insulating film on which the bit line is formed. A first contact formed through the sixth insulating film and the seventh insulating film and connected to the other of the source and the drain of the MOS transistor; A fourth conductor film formed and in contact with the first contact;
A fourth insulating film selectively covering a region of the insulating film on which the fourth conductive film is not formed with a uniform thickness, and a fourth insulating film and a fourth insulating film on the fourth insulating film. The fifth formed in
And a fifth conductor film formed on the fifth insulating film.

According to the semiconductor device, the fourth conductor film (generally, a storage node electrode) on the third insulating film
Since the fourth insulating film (generally, a stopper insulating film in an etching step) is formed in a region where no is formed, the first contact (generally, a storage node contact) and the fourth conductor are formed. Even if there is a difference between the film and the film, a fourth insulating film other than the fifth insulating film (generally, a capacitor insulating film) is also formed in the shifted region. Caused by the formed capacitor (formed between the fourth conductive film and the fifth conductive film (generally, a plate electrode) with the fourth insulating film and the fifth insulating film interposed therebetween) Degradation of the insulation property, etc. can be suppressed. Therefore, performance deterioration of the entire capacitor can be prevented, and a highly reliable semiconductor device (such as a DRAM) can be obtained.

Further, according to the present invention, a step of forming a third insulating film on the main surface side of a semiconductor substrate and a step of forming a first contact connected to the semiconductor substrate in the third insulating film Forming a fourth insulating film on the third insulating film; forming an eighth insulating film on the fourth insulating film; and forming the fourth insulating film and the eighth insulating film on the fourth insulating film. Forming a groove that penetrates through the insulating film and exposing the surface of the first contact; forming a fourth conductor film in the groove; and removing the eighth insulating film. It is characterized by having.

Further, according to the present invention, a step of forming a third insulating film on the main surface side of the semiconductor substrate and a step of forming a first contact connected to the semiconductor substrate in the third insulating film Forming a fourth insulating film on the third insulating film; forming an eighth insulating film on the fourth insulating film; and forming the fourth insulating film and the eighth insulating film on the fourth insulating film. Forming a groove that penetrates through the insulating film and exposing the surface of the first contact; forming a fourth conductor film in the groove; removing the eighth insulating film to remove the insulating film; A step of exposing a surface of the fourth insulating film, a step of forming a fifth insulating film on the exposed fourth insulating film and the fourth conductor film, and a step of forming a fifth insulating film on the fourth insulating film. Forming a fifth conductor film.

In the above invention, a step of forming a MOS transistor surrounded by an element isolation film on the main surface side of the semiconductor substrate is further provided, and the first contact is formed by the M type transistor.
It is preferable to connect to one of the source and the drain of the OS transistor.

In the above invention, a step of forming a second contact connected to the other of the source and the drain of the MOS transistor in the third insulating film; and forming the second contact in the third insulating film. Forming a bit line connected to the second contact.

Further, according to the present invention, there is provided a step of forming a MOS transistor surrounded by an element isolation film on a main surface side of a semiconductor substrate, and forming a sixth transistor on the main surface side of the semiconductor substrate on which the MOS transistor is formed. Forming a second contact connected to one of a source and a drain of the MOS transistor in the sixth insulating film; and forming the second contact on the sixth insulating film. Forming a bit line connected to the second contact, forming a seventh insulating film on the sixth insulating film on which the bit line is formed, forming the sixth insulating film and the seventh Forming a first contact that penetrates through the insulating film and connects to the other of the source and the drain of the MOS transistor; forming a fourth insulating film on the seventh insulating film; On the insulating film of No.4 Eighth forming an insulating film, the fourth insulating film and the through the eighth insulating film said first
Forming a groove where the surface of the contact is exposed,
A step of forming a fourth conductor film in the groove, a step of removing the eighth insulating film to expose a surface of the fourth insulating film, a step of exposing the exposed fourth insulating film and Forming a fifth insulating film on the fourth conductor film;
Forming a fifth conductor film on the insulating film.

In the above invention, the step of forming the groove includes the step of vertically anisotropically etching the eighth insulating film using the fourth insulating film as a stopper, and the step of forming the fourth insulating film after the step. Etching the eighth insulating film isotropically in the lateral direction using the insulating film as a stopper;
And etching the exposed fourth insulating film after this step.

In the above invention, it is preferable that the eighth insulating film is used as a mask when etching the fourth insulating film.

According to the method of manufacturing a semiconductor device, the first contact (generally, a storage node contact) and the fourth conductive film (generally, a storage node electrode) are caused by misalignment or the like. Even if a shift occurs, a fourth insulating film (generally, a stopper insulating film in an etching process) is formed in the shifted area in addition to the fifth insulating film (generally, a capacitor insulating film). The capacitors (the fourth conductor film and the fifth
Of the conductive film (generally formed with the fourth insulating film and the fifth insulating film sandwiched between the conductive film and the plate electrode) can be suppressed. Therefore, performance degradation of the entire capacitor can be prevented,
A highly reliable semiconductor device (such as a DRAM) can be manufactured. Further, since the fourth conductive film is embedded in the groove, if the groove is expanded by isotropic etching such as wet etching, the area of the fourth conductive film embedded in the groove is reduced by that amount. Can be bigger. Therefore, the area of the capacitor can be increased, that is, the capacitance of the capacitor can be increased.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described with reference to a dynamic RAM equipped with a stacked capacitor.
The case where the present invention is applied to will be described with reference to the drawings.

First, the first embodiment of the present invention will be described with reference to the manufacturing steps shown in FIGS. 1 (A1) to 4 (A8). In each of the process diagrams (A1) to (A8), the portion shown on the left side mainly shows a region having a capacitor (memory array region), and the portion shown on the right side shows a region mainly having no capacitor ( Peripheral circuit area), both of which are formed on the same semiconductor substrate (the same applies to the drawings according to other embodiments).

First, a gate insulating film (not shown) and a gate wiring 14 (not shown) are formed on a silicon substrate 11 (semiconductor substrate) on which an insulating film 12 for element isolation is formed, and a source / drain diffusion layer (not shown) is formed on the surface of the silicon substrate 11. And a plurality of transistors are arranged. Further, an insulating film 15 is formed around the gate wiring 14, and an interlayer insulating film 13 is buried between the gate wirings 14. Subsequently, a contact hole is formed in a predetermined region of the interlayer insulating film 13 by RIE. Subsequently, after depositing a conductive film such as polysilicon, the conductive layer is etched back to form a plug 16 made of the conductive film in the contact hole (A
1).

Next, an interlayer insulating film 17 is deposited, and the interlayer insulating film 17 and the interlayer insulating film 13 are selectively removed by RIE or the like to form contact holes and wiring trenches 18a, 1a, 1b.
8b is formed. Subsequently, after depositing a conductive film such as W,
This conductive film is flattened by a method such as RIE or CMP to form a wiring 19 (A2).

Although the wiring 19 is not shown, it functions as a bit line in the DRAM cell array region in FIG. 1A2. Therefore, in the step of A2, the bit lines of the memory cell array must be formed simultaneously. Can be. That is, in the contact hole forming step, a bit line contact hole and a bit line wiring groove can be simultaneously formed. Further, a bit line plug and a bit line can be formed in the same step as the formation of the wiring 19. This bit line is connected to one of the source / drain diffusion layers of the transistor, and the other is connected to a capacitor described later.

Next, an interlayer insulating film 20 is deposited, the interlayer insulating film 20 and the interlayer insulating film 17 are selectively removed by RIE or the like to form a contact hole 21, and a plug 16 is formed in the contact hole 21. The plug 22 to be connected is formed (A3).

Next, an interlayer insulating film 23 is deposited, a predetermined region of the interlayer insulating film 23 is removed, and a hole 24 is formed.
The surface of the plug 22 is exposed. Subsequently, after a conductive film is buried in the hole 24, the upper surface of the conductive film is made lower than the upper surface of the interlayer insulating film 23 by RIE or the like, and the lower electrode layer 2 for the capacitor connected to the plug 22 is formed.
5 is formed. Note that as a constituent material of the conductive film to be the lower electrode layer 25, Pt (platinum), Ru (ruthenium), RuO _2, or the like can be used (A4).

Next, the region having no capacitor is covered with a resist, and the interlayer insulating film 23 in the region having the capacitor is covered.
Is removed by CDE (Chemical Dry Etching) or wet etching to expose the interlayer insulating film 20 and form a hole 26 having the capacitor lower electrode layer 25 (A5).

Next, the capacitor insulating film 27 and the capacitor upper electrode layer 28 are deposited, the region having the capacitor is covered with a resist, and the capacitor insulating film 27 and the capacitor upper electrode layer 28 in the region having no capacitor are deposited.
Is removed by etching to form a capacitor. Note that, as the capacitor insulating film 27, SrTiO ₃ , Ba _x
A high dielectric thin film such as Sr _1-x TiO can be used. The material of the conductive film serving as the capacitor upper electrode layer 28 may be Pt or Ru as in the case of the lower electrode layer 25.
Alternatively, RuO ₂ or the like can be used (A6).

Next, the interlayer insulating film 23 and the interlayer insulating film 2
0 is selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, exposing the surface of the wiring 19 (A7).

Subsequently, after depositing a conductive film such as W, the conductive film is flattened by a method such as etch back or CMP (chemical mechanical polishing), and in a region having a capacitor, a capacitor upper electrode layer is formed. 2
8 is formed in the hole 26, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor (A8).

In the one manufactured by the above steps,
Upper surface of capacitor upper electrode layer 28 and silicon substrate 11
Distance between the upper surface of the wiring 30b and the silicon substrate 11
(In FIG. 4, the distance between the upper surface of the capacitor upper electrode layer 28 and the upper surface of the silicon substrate 11 is smaller than the distance between the upper surface of the wiring 30b and the upper surface of the silicon substrate 11). And the upper surfaces of the plate wiring 30a, the wiring 30b and the interlayer insulating film 23 and the silicon substrate 1
1 are all equal to the upper surface. Therefore, planarization between a region having a capacitor and a region having no capacitor can be realized.

In the above-described steps, the plate wiring 30a and the wiring 30b are formed simultaneously by burying the conductive film in the holes 26 and the holes 29a and 29b at the same time, so that the manufacturing process can be shortened. .

Next, a second embodiment of the present invention will be described.
The description will be given according to the manufacturing steps shown in FIGS. 5 (B1) to 7 (B5). Basic components are almost the same as those in the first embodiment, and there are also manufacturing steps common to the first embodiment. Will be referred to, and the description will be omitted.

Step (A3) of FIG. 2 in the first embodiment
After that, an insulating film 31 and an interlayer insulating film 23 are formed. The insulating film 31 serves as an etching stopper when a hole is formed in the interlayer insulating film 23 in a later step (B1).

Next, a predetermined region of the interlayer insulating film 23 and the insulating film 31 is removed to form a hole 24, and the surface of the plug 22 is exposed. Subsequently, after a conductive film is embedded in the hole 24, the upper surface of the conductive film is made lower than the upper surface of the interlayer insulating film 23 by RIE or the like, and the lower electrode layer 25 for the capacitor is formed (B2). .

Next, the region having no capacitor is covered with a resist, and the interlayer insulating film 23 in the region having the capacitor is covered.
Is removed by CDE or wet etching, etc.
A hole 26 having a lower electrode layer 25 for a capacitor is formed. At this time, since the insulating film 31 serving as an etching stopper is formed below the interlayer insulating film 23, the etching of the interlayer insulating film 23 can be stopped by the insulating film 31 (B3).

Next, a capacitor insulating film 27 and a capacitor upper electrode layer 28 are deposited, a region having a capacitor is covered with a resist, and a capacitor insulating film 27 and a capacitor upper electrode layer 28 in a region not having a capacitor are deposited.
Is removed by etching to form a capacitor. Next,
The interlayer insulating film 23, the insulating film 31, and the interlayer insulating film 20 are formed by RI
E and the like are selectively removed to form contact holes and wiring grooves 29a and 29b, and the surface of the wiring 19 is exposed (B4).

Thereafter, step (A8) in the first embodiment
Similarly, in the region having the capacitor, the plate wiring 3 lining the upper electrode layer 28 for the capacitor is formed.
0a is formed in the hole 26, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor (B5).

The same operation and effect as in the first embodiment can be obtained in the device manufactured by the above steps.

Next, a third embodiment of the present invention will be described.
The description will be given according to the manufacturing process shown in FIGS. 8 (C1) to 10 (C6). Basic components are almost the same as those in the first embodiment, and there are also manufacturing steps common to the first embodiment. Will be referred to, and the description will be omitted.

Step (A3) of FIG. 2 in the first embodiment
Thereafter, an interlayer insulating film 32 is deposited, and a predetermined region of the interlayer insulating film 32 is removed to form a hole. Subsequently, a conductive film is deposited and planarized by using a method such as CMP to bury the conductive film in the hole formed earlier to form the lower electrode layer 25 for the capacitor (C1).

Next, an interlayer insulating film 33 is further deposited on the interlayer insulating film 32 and the capacitor lower electrode layer 25 (C2).

Next, the region having no capacitor is covered with a resist, and the interlayer insulating film 32 in the region having the capacitor is covered.
And 33 are removed by CDE or wet etching to expose the interlayer insulating film 20 and form a hole 26 having the capacitor lower electrode layer 25 (C3).

Subsequent steps (C4) to (C6) are almost the same as steps (A6) to (A8) in the first embodiment, and as shown in FIG. A plate wiring 30a that lines the capacitor upper electrode layer 28 is formed in the hole 26, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor.

The same effect as that of the first embodiment can be obtained in the device manufactured by the above steps.

Next, a fourth embodiment of the present invention will be described.
The description will be given according to the manufacturing process shown in FIGS. 11 (D1) to 12 (D4). The basic components are the first
The manufacturing steps are almost the same as those of the first embodiment, and there are also manufacturing steps common to the first embodiment. Unless otherwise indicated, these are referred to the corresponding drawings and corresponding description of the first embodiment, and the description is omitted. I do.

Step (A3) of FIG. 2 in the first embodiment
Thereafter, a conductive film is deposited and patterned into a predetermined shape to form the lower electrode layer 25 of the capacitor (D
1).

Next, an interlayer insulating film 34 is deposited on the interlayer insulating film 20 and the capacitor lower electrode layer 25 such that the upper surface thereof is higher than the upper surface of the capacitor lower electrode layer 25 (D2). .

Next, the region having no capacitor is covered with a resist, and the interlayer insulating film 34 in the region having the capacitor is covered.
Is removed by CDE or wet etching to expose the interlayer insulating film 20, and the lower electrode layer 2 for the capacitor is removed.
5 is formed (D3).

Thereafter, the step (A6) in the first embodiment
As shown in FIG. 12 (D4), a plate wiring 30a to be a lining of the capacitor upper electrode layer 28 is formed in the hole 26 in the region having the capacitor by the same steps as (A8) to (A8). In a region having no, the wiring 30b is formed in the holes 29a and 29b (D4).

The same effect as that of the first embodiment can be obtained in the device manufactured by the above steps.

Next, a fifth embodiment of the present invention will be described.
The description will be given in accordance with the manufacturing process shown in FIGS. 13 (E1) to 15 (E5). The basic components are the first
The manufacturing steps are almost the same as those of the first embodiment, and there are also manufacturing steps common to the first embodiment. Unless otherwise indicated, these are referred to the corresponding drawings and corresponding description of the first embodiment, and the description is omitted. I do.

Step (A1) of FIG. 1 in the first embodiment
3 to form a hole 26 having the capacitor lower electrode layer 25 (E1). In addition,
By the method used in each embodiment other than the first embodiment,
A shape as shown in FIG. 13 (E1) may be configured.

Next, an insulating film and a conductive film for forming the capacitor insulating film 27 and the capacitor upper electrode layer 28 are sequentially deposited (E2).

Next, the capacitor upper electrode layer 28, the capacitor insulating film 27, the interlayer insulating film 23, and the interlayer insulating film 20 are selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b. Then, the surface of the wiring 19 is exposed (E3).

Next, a conductive film 30 of W or the like is deposited (E
4).

Subsequently, the conductive film 30, the capacitor upper electrode layer 28 and the capacitor insulating film 27 are
Planarization is performed by removing by a method such as MP, and in a region having a capacitor, a plate wiring 30a serving as a backing of the capacitor upper electrode layer 28 is formed in a hole 2
6, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor (E5).

The same operation and effect as in the first embodiment can be obtained in the device manufactured by the above steps.

Next, a sixth embodiment of the present invention will be described.
Description will be given according to the manufacturing process shown in FIGS. 16 (F1) to 18 (F6). The basic components are the first
The manufacturing steps are almost the same as those of the first embodiment, and there are also manufacturing steps common to the first embodiment. Unless otherwise indicated, these are referred to the corresponding drawings and corresponding description of the first embodiment, and the description is omitted. I do.

Step (A3) in FIG. 2 in the first embodiment
After that, a conductive film is deposited and patterned into a predetermined shape to form the capacitor lower electrode layer 25 (F
1).

Next, a capacitor insulating film 27 and a capacitor upper electrode layer 28 are sequentially deposited, and are patterned into a predetermined shape to form a capacitor (F).
2).

Next, an interlayer insulating film 35 is deposited on the interlayer insulating film 20 and the capacitor (F3).

Next, the region having no capacitor is covered with a resist, and the interlayer insulating film 35 in the region having the capacitor is covered.
Is removed by CDE or wet etching, etc.
A hole 26 having a capacitor is formed (F4).

Next, the interlayer insulating film 35 and the interlayer insulating film 2
0 is selectively removed by RIE or the like to form contact holes and wiring grooves 29a and 29b, and the surface of the wiring 19 is exposed (F5).

Subsequently, after depositing a conductive film such as W, the conductive film is flattened by a method such as etch-back or CMP, and a plate wiring serving as a backing for the capacitor upper electrode layer 28 is formed in a region having a capacitor. A hole 30a is formed in the hole 26, and a wiring 30b is formed in the holes 29a and 29b in a region having no capacitor (F6).

The same operation and effect as in the first embodiment can be obtained in the device manufactured by the above steps.

Hereinafter, a seventh embodiment of the present invention will be described in detail with reference to FIGS.

Note that each figure (a) is the same as each figure (c) (a figure corresponding to a plane pattern when performing photolithography).
-A 'section, each figure (b) shows the BB' section of each figure (c).

First, a semiconductor substrate 101 using silicon
Next, an element isolation region 102 is formed by STI (Shallow Trench Isolation), and a P well region is formed by impurity ion implantation (FIG. 19).

Next, a gate oxide film (not shown) of, eg, 6 nm is formed on the semiconductor substrate 101 to form a transistor.
m polycrystalline silicon film 103a, about 100 nm tungsten silicide (WSi) or tungsten (W) film 103b, about 100 nm silicon nitride (SiN) 10
3c film is deposited. After patterning the gate electrode 103, an N-type impurity such as P or As is ion-implanted to form a source / drain diffusion layer 104. Subsequently, for example, a silicon nitride film 105 of 30 nm is deposited, and a sidewall is formed on the gate electrode 103 by etching back. After transistor formation, about 250-300n
m insulating film 106 (for example, BPSG or plasma SiO
₂ etc.) (FIG. 20).

Next, the insulating film 106 is subjected to CMP (Chemical Mechanical Polishing) using the SiN film 103c as a stopper.
ng), the resist mask 107 is flattened.
The insulating film 106 is patterned using the (opening pattern), and a contact hole is formed in a self-aligned manner with respect to the gate electrode 103 (FIG. 21).

Next, the resist is removed, and a conductive film 108 for forming a plug, for example, a poly-Si film doped with P or As is deposited (FIG. 22).

Next, a conductive film 1 for forming a plug
08 is flattened by the CMP method using the SiN film 103c as a stopper. Subsequently, an insulating film 109 (for example, BPSG or plasma SiO ₂ ) of about 100 to 200 nm is deposited, planarized by a CMP method, and a bit line contact 110 reaching the plug 108 formed previously is formed. Subsequently, a conductive film 111a made of, for example, about 20 nm of Ti / TiN and about 100 nm of W is deposited on the insulating film 109, and an about 150 nm SiN film 111b is deposited thereon, and these are patterned to form a bit. A line 111 is formed. Further, after depositing a SiN film 112 of about 30 nm, this is etched to form a sidewall on the side wall of the bit line.

Next, 400 is applied so as to cover the bit line 111.
nm insulating film 113 (for example, BPSG or plasma S
iO _2, etc.), and flatten this using a CMP method. Subsequently, using a resist mask, the insulating film 113 is etched in a self-aligned manner with respect to the bit line 111, and a contact opening is formed so as to reach the plug 108 formed earlier. Subsequently, after removing the resist, in order to form the storage node contact 114, the contact opening is buried with a conductive material, for example, a barrier metal (Ti / TiN) and W or P-doped poly-Si or the like, and planarized. (FIG. 23).

Next, a film having a high etching selectivity with respect to the oxide film, for example, a 50 nm-thick SiN film 115 having a uniform thickness is formed over the entire surface, followed by an insulating film 116 having a thickness of about 300 nm (eg, BPSG or plasma SiO ₂ ) Is deposited on the entire surface, and the insulating film 116 and the SiN film 115 are etched by RIE using the resist mask 121 having a hole-shaped pattern to form a groove 117. (FIG. 24).

Next, a storage node electrode material 118, for example, 200 nm of tungsten nitride (W / N), ruthenium (Ru), or ruthenium oxide (RuO _x ) is deposited by sputtering to fill the trench 117 (FIG. 25). .

Next, the storage node electrode material 118 is polished and flattened to the upper surface of the insulating film 116 by the CMP method to form a storage node electrode. Ruthenium or a ruthenium compound used as the storage node electrode 118 is suitable as an electrode of a capacitor using a high dielectric film such as barium strontium titanate (BSTO), but is difficult to etch using RIE or the like. Therefore, by embedding ruthenium or the like in the trench as in this example, the storage node electrode 118 can be easily formed.
Can be formed (FIG. 26).

Next, insulating film 116 is completely removed by wet etching so that the side surface of storage node electrode 118 is exposed. At this time, since the SiN film 115 functions as a wet etching stopper, the insulating film 113 is not etched. At this time, the exposed SiN film 115 selectively covers a region where the storage node electrode 118 is not formed with a uniform thickness.
That is, the SiN on the side surface of the storage node electrode 118
The SiN film 115 is not formed on the region above the thickness of the film 115 and on the upper surface of the storage node electrode 118 (FIG. 27).

Next, as the capacitor dielectric film 119,
For example, barium strontium titanate (BSTO) or the like is deposited by a CVD method or a sputtering method. Subsequently, a tungsten nitride film, a ruthenium film or a ruthenium oxide film of, for example, about 100 nm is deposited as the plate electrode 120 and planarized by a CMP method to form a capacitor (FIG. 28).

Thereafter, wirings and the like are formed by using a usual method, thereby completing the DRAM.

FIG. 29 shows storage node contact 1
14 shows a state in which the storage node electrode 14 and the storage node electrode 118 are displaced. In the present embodiment, since the stopper film 115 is formed below the capacitor dielectric film 119, even if such a shift occurs, deterioration of the capacitor characteristics can be prevented.

Next, an eighth embodiment of the present invention will be described in detail with reference to FIGS.

Since the eighth embodiment is a modification of the steps of the seventh embodiment shown in FIGS. 19 to 28, only the necessary description will be given here, and the other portions will be described in the seventh embodiment. And the corresponding drawings.

The first half of the process is the same as that of the seventh embodiment (FIG. 19).
23 to FIG. 23), and the subsequent steps will be described below. The following steps in FIGS. 30 to 34 substantially correspond to the steps in FIGS. 24 to 28 in the seventh embodiment.

After the step of FIG. 23, a film having a high etching selectivity to an oxide film, for example, a 50 nm SiN film 115
Is deposited over the entire surface with a uniform thickness, and then an insulating film 116 (for example, BPSG or plasma SiO ₂ ) of about 300 nm is deposited.
Is deposited on the entire surface. Subsequently, the insulating film 116 is vertically anisotropically etched by RIE using a resist mask having a hole-shaped pattern to form a groove 117. At this time, the SiN film 115 is used as an etching stopper.
Subsequently, wet etching is performed using the SiN film 115 as a stopper, and the insulating film 116 is isotropically etched in the lateral direction by about 20 nm. Subsequently, using the patterned insulating film 116 as a mask, the SiN film 115 remaining at the bottom of the groove is removed by etching using RIE. As described above, by etching the insulating film 116 isotropically, the width of the groove 117 is increased (the width L2 is wider than the width L1 in the seventh embodiment (FIG. 24)), and the bottom area of the capacitor is increased ( (FIG. 30).

Next, tungsten nitride (W / N), ruthenium (Ru), or ruthenium oxide (RuO _x ) of, for example, about 200 nm is deposited as a storage node electrode material 118 by a sputtering method so as to fill the trench 117 (FIG. 31). ).

Next, the storage node electrode material 118 is polished and planarized by the CMP method up to the upper surface of the insulating film 116 to form a storage node electrode (FIG. 32).

Next, the insulating film 116 is completely removed by wet etching so that the side surface of the storage node electrode 118 is exposed. At this time, since the SiN film 115 functions as a wet etching stopper, the insulating film 113 is not etched. At this time, the exposed SiN film 115 selectively covers a region where the storage node electrode 118 is not formed with a uniform thickness (FIG. 33).

Next, as the capacitor dielectric film 119,
For example, barium strontium titanate (BSTO) or the like is deposited by a CVD method or a sputtering method. Subsequently, a tungsten nitride film, ruthenium film or ruthenium oxide film of, for example, about 100 nm is deposited as the plate electrode 120, and is flattened by a CMP method to form a capacitor (FIG. 34).

Thereafter, wirings and the like are formed by using a usual method, thereby completing the DRAM.

In the eighth embodiment, the same effects as in the seventh embodiment can be obtained, and the bottom area of the groove can be increased, so that the capacitance of the capacitor can be increased.

The present invention is not limited to the above embodiments, but can be implemented with various modifications without departing from the spirit thereof.

[0112]

According to the semiconductor memory device of the present invention, the resistance can be reduced, and the region where the first hole is formed and the region where the second hole is formed have a third resistance. Since the heights of the conductor films can be made substantially equal, planarization can be achieved.

In the method of manufacturing a semiconductor memory device according to the present invention, since the third conductor film is buried in the first hole and the second hole at the same time, the resistance can be reduced without increasing the number of manufacturing steps. And a region in which the first hole is formed and a region in which the second hole is formed,
Since the height of the third conductor film can be made substantially equal, planarization can be achieved, and the process margin in lithography can be increased.

In the semiconductor memory device according to the present invention, there is a shift between the first contact (generally, a storage node contact) and the fourth conductor film (generally, a storage node electrode). However, since the fourth insulating film (generally, a stopper insulating film in an etching process) is also formed in the shifted region in addition to the fifth insulating film (generally, a capacitor insulating film), It is possible to suppress the deterioration of insulation and the like due to the capacitor formed in the region where the capacitor is formed, and to prevent the performance of the entire capacitor from being deteriorated.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, even if a shift occurs between the first contact and the fourth conductive film, the insulating property caused by the capacitor formed in the shifted area is obtained. Deterioration and the like can be suppressed, and the fourth conductor film is embedded in the groove,
If the groove is expanded by isotropic etching, the area of the fourth conductive film embedded in the groove can be increased, and the capacitor area, that is, the capacitance of the capacitor can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a part of the manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a part of the manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a part of the manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a part of a manufacturing process according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a part of the manufacturing process according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a part of a manufacturing process according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing a part of a manufacturing process according to a third embodiment of the present invention.

FIG. 10 is a sectional view showing a part of a manufacturing process according to a third embodiment of the present invention.

FIG. 11 is a sectional view showing a part of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view showing a part of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view showing a part of a manufacturing process according to a fifth embodiment of the present invention.

FIG. 14 is a sectional view showing a part of a manufacturing process according to a fifth embodiment of the present invention.

FIG. 15 is a sectional view showing a part of a manufacturing process according to a fifth embodiment of the present invention.

FIG. 16 is a sectional view showing a part of the manufacturing process according to the sixth embodiment of the present invention.

FIG. 17 is a sectional view showing a part of the manufacturing process according to the sixth embodiment of the present invention.

FIG. 18 is a sectional view showing a part of the manufacturing process according to the sixth embodiment of the present invention.

FIG. 19 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 20 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 21 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 22 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 23 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 24 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 25 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 26 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 27 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 28 is a sectional view showing a part of the manufacturing process according to the seventh embodiment of the present invention.

FIG. 29 is a sectional view showing a state in which the pattern is shifted in FIG. 28;

FIG. 30 is a sectional view showing a part of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 31 is a sectional view showing a part of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 32 is a sectional view showing a part of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 33 is a sectional view showing a part of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 34 is a sectional view showing a part of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 35 is a cross-sectional view showing a manufacturing process according to the related art.

FIG. 36 is a diagram showing a problem of the related art.

[Explanation of symbols]

 11, 101 ... semiconductor substrate 23, 32, 33, 34, 35 ... second insulating film 25 ... first conductive film 26 ... first hole 27 ... first insulating film 28 ... second conductive film 29a, 29b: second holes 30a, 30b: third conductor film 109: third insulating film, sixth insulating film 110: second contact 111: bit line 113: third insulating film, third 7 insulating film 114 ... first contact 115 ... fourth insulating film 116 ... eighth insulating film 118 ... fourth conductive film 119 ... fifth insulating film 120 ... fifth conductive film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Keiji Hosoya 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside Toshiba Yokohama Office

Claims (17)

[Claims] 1. A semiconductor device comprising a first conductor film, a first insulation film formed on the first conductor film, and a second conductor film formed on the first insulation film. In a semiconductor memory device in which a storage capacitor to be formed is formed on a main surface side of a semiconductor substrate, the capacitor is formed in a first concave portion of a second insulating film, and the second insulating film has Two recesses are formed, a third conductor film is buried in the first recess and the second recess, and an upper surface of the third conductor film buried in the first recess And a distance between the semiconductor substrate and a top surface of the semiconductor substrate, wherein a distance between the top surface of the semiconductor substrate and a top surface of the semiconductor substrate is substantially equal to a distance between the top surface of the semiconductor substrate and the top surface of the semiconductor substrate. 2. A semiconductor device comprising: a first conductor film; a first insulation film formed on the first conductor film; and a second conductor film formed on the first insulation film. In a semiconductor memory device in which a storage capacitor to be formed is formed on a main surface side of a semiconductor substrate, the capacitor is formed in a first concave portion of a second insulating film, and the second insulating film has Two recesses are formed, a third conductor film is embedded in the first recess and the second recess, and a second conductor of the capacitor formed in the first recess is formed. A semiconductor memory device, wherein a distance between an upper surface of a film and an upper surface of the semiconductor substrate is equal to or less than a distance between an upper surface of a third conductive film embedded in the second recess and an upper surface of the semiconductor substrate. . 3. A semiconductor device comprising a first conductor film, a first insulation film formed on the first conductor film, and a second conductor film formed on the first insulation film. A method for manufacturing a semiconductor memory device in which a storage capacitor to be formed is formed on a main surface side of a semiconductor substrate, wherein a second insulating film having a first concave portion and the first conductor provided in the first concave portion Forming a film;
Forming a second concave portion in the insulating film, and forming the first concave portion and the second concave portion in which the first conductive film, the first insulating film, and the second conductive film are formed. And a step of burying a third conductor film at the same time. 4. A semiconductor device comprising: a first conductor film; a first insulation film formed on the first conductor film; and a second conductor film formed on the first insulation film. A method of manufacturing a semiconductor memory device in which a storage capacitor to be formed is formed on a main surface side of a semiconductor substrate, wherein: a step of forming a second insulating film; and a step of selectively removing the second insulating film. Embedding the first conductive film in a portion where the second insulating film is selectively removed, and further selectively removing the second insulating film to form the first conductive film. Forming a first concave portion for projecting the second insulating film; forming a second concave portion in the second insulating film;
Embedding a third conductive film in the first concave portion and the second concave portion where the first conductive film, the first insulating film, and the second conductive film are formed, respectively. Manufacturing method of a semiconductor memory device. 5. The second insulating film according to claim 3, wherein the second insulating film has the first concave portion and the first insulating film provided in the first concave portion.
Forming the first insulating film and the second conductive film after the step of forming the second conductive film, and forming the second conductive film, the first insulating film, and the second conductive film. Forming a second recess in the second insulating film by selectively removing the insulating film; and forming the third conductor film,
The third conductor film, the second conductor film, and the first
The first conductive film, the first insulating film and the second conductive film are formed on the first concave portion and the second concave portion by removing the insulating film by a predetermined thickness. Simultaneously embedding the third conductor film. 6. A third insulating film formed on a main surface side of a semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, and a third insulating film. A fourth conductive film formed on the film and in contact with the first contact, and a region on the third insulating film where the fourth conductive film is not formed is selectively formed with a uniform thickness. And a fourth insulating film that covers the semiconductor memory device. 7. A third insulating film formed on a main surface side of a semiconductor substrate, a first contact formed in the third insulating film and connected to the semiconductor substrate, and a third insulating film. A fourth conductive film formed on the film and in contact with the first contact, and a region on the third insulating film where the fourth conductive film is not formed is selectively formed with a uniform thickness. A covering fourth insulating film, the fourth conductive film, a fifth insulating film formed on the fourth insulating film, and a fifth conductive film formed on the fifth insulating film; And a film. 8. The semiconductor memory device according to claim 7, further comprising a MOS transistor formed on a main surface side of said semiconductor substrate and surrounded by an element isolation film, wherein said first contact is formed of said MOS transistor. A semiconductor memory device which is connected to one of a source and a drain of a transistor. 9. The semiconductor memory device according to claim 8, wherein: a second contact formed in said third insulating film and connected to the other of a source and a drain of said MOS transistor; And a bit line connected to the contact. 10. A MOS transistor formed on a semiconductor substrate and surrounded by an element isolation film, a sixth insulating film formed on a main surface side of the semiconductor substrate on which the MOS transistor is formed, and A second contact formed in a sixth insulating film and connected to one of a source and a drain of the MOS transistor; and a bit line formed on the sixth insulating film and connected to the second contact. When,
A seventh insulating film formed on the sixth insulating film on which the bit line is formed, and a source of the MOS transistor formed through the sixth insulating film and the seventh insulating film. Or a first contact connected to the other of the drain, a fourth conductor film formed on the seventh insulating film and in contact with the first contact, and a fourth conductor film on the seventh insulating film. A fourth insulating film selectively covering a region where the conductive film is not formed with a uniform thickness, and a fifth insulating film formed on the fourth conductive film and the fourth insulating film. Membrane and
And a fifth conductor film formed on the fifth insulating film. 11. A step of forming a third insulating film on a main surface side of a semiconductor substrate, a step of forming a first contact connected to the semiconductor substrate in the third insulating film, Forming a fourth insulating film on the third insulating film, forming an eighth insulating film on the fourth insulating film, and forming the fourth insulating film and the eighth insulating film on the fourth insulating film. Forming a groove through which the surface of the first contact is exposed; forming a fourth conductor film in the groove;
Removing the insulating film. 12. A step of forming a third insulating film on the main surface side of the semiconductor substrate, a step of forming a first contact connected to the semiconductor substrate in the third insulating film, Forming a fourth insulating film on the third insulating film, forming an eighth insulating film on the fourth insulating film, and forming the fourth insulating film and the eighth insulating film on the fourth insulating film. Forming a groove through which the surface of the first contact is exposed; forming a fourth conductor film in the groove;
Removing the insulating film and exposing the surface of the fourth insulating film; and forming a fifth insulating film on the exposed fourth insulating film and the fourth conductor film. Forming a fifth conductor film on the fifth insulating film. 13. The method of manufacturing a semiconductor memory device according to claim 12, further comprising a step of forming a MOS transistor surrounded by an element isolation film on a main surface side of said semiconductor substrate, 13. The method according to claim 12, wherein a contact is connected to one of a source and a drain of the MOS transistor. 14. A method of manufacturing a semiconductor memory device according to claim 13, wherein a second contact connected to the other of the source and the drain of the MOS transistor is formed in the third insulating film. Forming a bit line connected to the second contact in the third insulating film. 15. A step of forming a MOS transistor surrounded by an element isolation film on a main surface side of a semiconductor substrate;
Forming a sixth insulating film on the main surface side of the semiconductor substrate on which the OS-type transistor is formed, and forming a second insulating film in the sixth insulating film to be connected to one of a source and a drain of the MOS-type transistor Forming a contact, forming a bit line connected to the second contact on the sixth insulating film, and forming a seventh insulating film on the sixth insulating film on which the bit line is formed. Forming a film, and the MO film penetrating the sixth insulating film and the seventh insulating film.
Forming a first contact connected to the other of the source and the drain of the S-type transistor, forming a fourth insulating film on the seventh insulating film, and forming a fourth contact on the fourth insulating film. Forming a groove through which the surface of the first contact is exposed through the fourth insulating film and the eighth insulating film; and forming a fourth groove in the groove. Forming a conductor film; removing the eighth insulating film to expose a surface of the fourth insulating film;
Forming a fifth insulating film on the exposed fourth insulating film and the fourth conductive film; and forming a fifth conductive film on the fifth insulating film. A method for manufacturing a semiconductor memory device, comprising: 16. The method according to claim 16, wherein the step of forming the groove is performed by the fourth step.
Etching the eighth insulating film anisotropically in the vertical direction using the insulating film as a stopper, and, after this step, isotropically etching the eighth insulating film in the horizontal direction using the fourth insulating film as a stopper 16. The method according to claim 15, further comprising the steps of: performing a selective etching step; and etching the fourth insulating film exposed after this step. 17. The method according to claim 16, wherein the etching of the fourth insulating film uses the eighth insulating film as a mask.