JPH098252A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To microminiaturize a DRAM having a COB(Capacitor Over Bit-line) structure by solving the DOF(Depth Of Focus) problem of the DRAM caused by the level difference between word-line conductor films and cell array sections and peripheral circuit sections of the DRAM and, at the same time, by eliminating the need of alignment margins from storage node contact holes. SOLUTION: A DRAM is constructed in a COW(Capacitor Over Word-line) structure in which the lower electrodes 10 of capacitors are formed above word- line conductor films 14 and, at the same time, storage node contact holes 5a are formed in self-matching ways by utilizing the patterns of bit-line conductor films 6 and word-line conductor films 14 as etching makes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as DRAM and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory such as a one-transistor / one-capacitor type DRAM, when increasing the cell capacity, there is a restriction on the memory cell size in order to increase the surface area of the capacitor portion. As in the cell structure (hereinafter, referred to as “STC structure”), there is a tendency to adopt a technique of increasing the storage node in the height direction of the memory cell. This trend is
It becomes more remarkable as the integration degree of M increases. The memory cell structure of such a stacked DRAM is, for example, NIKKE.
I MICRODEVICES August 1994 Issue 3
Some examples are given on pages 2-37.

However, if the height of the memory cell portion is increased with the STC structure, the step difference between the cell array portion and the peripheral portion is further increased, and metal wiring such as a bit line extending between the cell array portion and the peripheral portion. When patterning
Depth of focus (DOF)
us) Due to the margin, it has become difficult to resolve fine wiring. This has become a particularly serious problem because the pitch between the bit lines tends to become narrower as the cell pitch becomes finer. NIKKEIMICR above
The ODEVICES document does not discuss anything about the depth of focus margin of this photolithography.

Therefore, as a method for solving this problem, the present inventor has proposed a COB (Capacitor) as shown in FIGS.
The prototype of the tor Over Bit-line) structure was examined.

FIG. 5A is a schematic plan view showing the layout of the bit line 106 of the cell array portion of the COB structure and the portion below it, and FIG. 5B is above the bit line 106. It is a schematic plan view which shows the layout of a part. In addition, FIG. 6A is a VIA of FIG.
6B is a schematic cross-sectional view taken along line VIA, and the left part of FIG. 6B is a schematic cross-sectional view taken along line VIB-VIB of FIG. 5A. , The selection transistor portion in the peripheral portion is also shown.

As shown in FIGS. 5A and 6A and 6B, a plurality of gate electrode wirings 103 made of an N-type polycrystalline silicon layer are formed in a vertical direction on a P-type silicon substrate 101, Each gate electrode wiring 103 and element isolation oxide film 102
N-type diffusion layers 104 and 105 are formed in the silicon substrate 101 in the regions defined by and, respectively. A plurality of bit lines 106, which are stacked wirings of tungsten silicide and an N-type polycrystalline silicon layer, are formed in the lateral direction on the silicon substrate 101, and each bit line 106 is one N-type diffusion via a bit contact 104a. It is connected to the layer 104. The other N-type diffusion layer 105 is connected to the storage node electrode 110 of the capacitor via the storage node contact 105a.

As shown in FIGS. 5B and 6A and 6B, an N-type polycrystalline silicon layer is formed on the storage node electrode 110 via a capacitive insulating film 111 made of an ONO film. A cell plate electrode 112 is formed, and a cell plate electrode 112 is formed on the cell plate electrode 112 via a second interlayer insulating film 113 made of BPSG.
A word line (lining word line) 114 mainly made of low-resistance wiring such as aluminum or tungsten is formed. Each of these word lines 114 is in contact with the gate electrode wiring 103 immediately below it at a predetermined position outside the drawing.

In each figure, 107 is a gate oxide film and 1 is a gate oxide film.
Reference numeral 08 is a sidewall oxide film, and 109 is a first interlayer insulating film made of BPSG.

In the structure described above, as shown in FIG. 7, each gate electrode wiring 103 serves as a gate electrode, and a pair of N-type diffusion layers 104 and 105 sandwiching the gate electrode serve as a source / drain transfer gate. There is M
OS transistor T and storage node electrode 1 connected to one N-type diffusion layer 105 of the MOS transistor
A 1-bit memory cell is composed of the capacitor C formed of the capacitor insulating film 111 and the cell plate electrode 112. That is, the N-type diffusion layers 104 of two memory cells adjacent to each other in the direction of the bit line 106 are
The memory cells are shared by one memory cell, and the pair of N-type diffusion layers 104 and 105 of each memory cell are formed so as to be offset from each other in the direction along the gate electrode wiring 103, that is, in the direction of the word line 114. There is.

The so-called COB in which the capacitor C of each memory cell is formed above the bit line 106.
It has a structure.

When such a COB structure is adopted, FIG.
As shown in (b), since the bit line 106 can be formed in a relatively lower layer, the bit line 106 can be formed.
With regard to (2), it is possible to almost eliminate the step between the cell array portion and the peripheral portion, and the problem of the fine processing described above is solved.

[0012]

However, in the above-mentioned conventional COB structure, the word line 114 still has a problem of a step between the cell array portion and the peripheral portion. That is, as shown in FIG. 6B, it was found that there was a large step d between the cell array portion and the peripheral portion.

Generally, even if the cell size is miniaturized, the cell capacity is not scaled, and due to consideration of soft error, the capacity is always the same (for example, 64M or more).
It is necessary to secure 25 to 30 fF) in 256 MDRAM. Therefore, since the cell size is two-dimensionally restricted, the height of the storage node electrode 110 tends to be increased to increase the capacity. As a result, the step d between the cell array portion and the peripheral portion becomes larger and the word line 11
The problem of defocus in the photolithography of No. 4 has not been completely solved. In addition, the pitch (Line & Space) between the gate electrode wirings 103, and hence between the word lines 114, has become smaller with the demand for miniaturization in recent years.
The depth of focus margin of 4 is being lost.

In the conventional COB structure described above, the storage node contact 105a is formed by using the bit line 106 as a mask as shown in FIGS. The size of the contact 105a is defined in a direction perpendicular to the bit line 106 in a self-aligned manner, but in the direction perpendicular to the gate electrode wiring 103, a distance x including an alignment margin during photolithography (see FIG. 5A). It was necessary to provide (see) outside the gate electrode wiring 103. However, when the pitch between the gate electrode wirings 103 is getting smaller as in recent years, this becomes one constraint condition for miniaturization.

Therefore, an object of the present invention is to provide a D of COB structure.
It is an object of the present invention to provide a semiconductor memory device and a method of manufacturing the same that solve the problems of a step between the cell array portion and the peripheral portion with respect to a word line and the alignment margin with respect to a storage node contact in a RAM or the like.

[0016]

In order to solve the above-mentioned problems, according to the present invention, a 1-bit memory cell is constituted by a transistor structure and a capacitor structure formed on a semiconductor substrate, and a plurality of the memories are formed. The cells are arranged substantially in a matrix to form a memory cell array, and the gate electrodes of the transistor structures of a predetermined number of the memory cells arranged in one direction of the memory cell array are formed integrally and continuously. In a semiconductor memory device having an electrode wiring, it is formed on the gate electrode wiring via a first insulating layer, extends in a direction orthogonal to the gate electrode wiring, and is arranged in a direction orthogonal to the gate electrode wiring. A bit line conductor film that contacts one active region of the transistor structure of the memory cell, and a second insulating layer, Is formed on the Ttorain conductor film,
A word line conductor film extending in parallel with the gate electrode wiring and contacting the gate electrode wiring at a predetermined position;
A lower electrode film of the capacitor structure of each memory cell formed on the word line conductor film via a third insulating layer and contacting the other active region of the transistor structure of each memory cell; And an upper electrode film of the capacitor structure formed on the lower electrode film via a capacitive insulating film of the capacitor structure.

According to the method of manufacturing a semiconductor memory device of the present invention, a semiconductor substrate is used to form a gate electrode and a source / source of a transistor structure which becomes a transfer gate of each memory cell.
Forming active regions to serve as drains, and forming a first insulating layer on the entire surface, and then forming a first insulating layer on the first insulating layer to reach one of the active regions of the transistor structure of each memory cell; A step of forming a contact hole of 1;
Patterning a bit line that contacts the one active region through the first contact hole on the first insulating layer; forming a second insulating layer on the entire surface; A conductive layer to be a word line, a third insulating layer, and a low-resistance polycrystalline silicon layer are sequentially formed on the insulating layer of the above, and these are processed into a word line pattern, and the polycrystalline silicon layer is etched. Forming a second contact hole reaching the other active region of the transistor structure of each memory cell in the second insulating layer and the first insulating layer by using as a mask; Forming a silicon oxide film on the substrate, and then anisotropically etching the silicon oxide film to form a contact sidewall insulating film on the sidewall of the second contact hole;
After forming a low resistance polycrystalline silicon layer on the entire surface, patterning this to form a lower electrode film of the capacitor structure of each memory cell that contacts the other active region through the second contact hole. And a step of forming a capacitor insulating film of the capacitor structure on the lower electrode, and a step of forming an upper electrode film of the capacitor structure on the capacitor insulating film.

[0018]

In the present invention, a so-called C in which a word line conductor film is formed under the capacitor structure of each memory cell is used.
By adopting the OW (Capacitor Over Wordline) structure, the word line conductor film can be formed in a relatively low layer, and the problem of the step between the cell array portion and the peripheral portion with respect to the word line conductor film can be solved.

Further, the pattern of the word line conductor film is
By using it as an etching mask for the storage node contact of the capacitor structure formed after the word line conductor film, the storage node contact can be formed in self alignment with the word line conductor film. , There is no need for alignment margins outside them.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1A shows a DR in this embodiment.
FIG. 1B is a schematic plan view showing the layout of a portion below the bit line 6 of the AM cell array portion, and FIG. 1B is a schematic plan view showing the layout of the portion above the bit line 6. 2A is a schematic cross-sectional view taken along the line IIA-IIA of FIG. 1A, and the left side portion of FIG.
2A is a schematic cross-sectional view taken along line IIB-IIB of FIG.
The right side portion of (b) also shows the peripheral portion of the select transistor.

As shown in FIGS. 1 (a) and 2 (a) (b), a plurality of gate electrode films formed of an N-type polycrystalline silicon layer in a first direction on a P-type silicon substrate 1, That is, the gate electrode wiring 3 is formed, and a pair of active regions, such as N-type diffusion layers 4 and 5, are formed on the surface of the silicon substrate 1 in each region defined by each gate electrode wiring 3 and the element isolation oxide film 2. ing. The gate electrode wiring 3 and the diffusion layers 4 and 5 form a transistor structure T ′. A plurality of bit line conductor films 6 which are stacked wirings of a tungsten silicide and an N-type polycrystalline silicon layer are formed on a silicon substrate 1 in a second direction intersecting the first direction, and each bit line conductor film is formed. 6 is connected to one N-type diffusion layer 4 via a bit contact 4a. The other N-type diffusion layer 5 is connected to the storage node electrode 10 of the capacitor structure C ′ via the storage node contact 5a.

In the present embodiment, as shown in the figure, a word mainly composed of a low resistance wiring such as aluminum or tungsten is provided on a layer immediately above the bit line conductor film 6 via a first interlayer insulating film 9 made of BPSG. Line (lined word line)
Conductor film 14 is formed, and storage node electrode 1 is formed.
0 is formed in a layer above the word line conductor film 14. The word line conductor film 14 is
The gate electrode wiring 3 immediately below is electrically connected and in contact with the gate electrode wiring 3 immediately below at a predetermined position outside the drawing.

As shown in FIGS. 1B and 2A and 2B, on the storage node electrode 10, a capacitive insulating film (ONO film or a ferroelectric film such as Ta ₂ O ₅₎ ( A cell plate electrode 12 made of an N-type polycrystalline silicon layer is formed with a dielectric film 11 interposed therebetween.

In each figure, 7 is a gate oxide film, 8 is a sidewall oxide film, and 13 is a second interlayer insulating film made of BPSG.

In the structure described above, each gate electrode wiring (gate electrode film) 3 serves as a gate electrode, and a pair of N type diffusion layers 4 and 5 sandwiching the gate electrode serve as a source / drain transfer gate. A MOS transistor structure T ′ and a storage node electrode 10 connected to one N-type diffusion layer 5 of the MOS transistor structure T ′,
A 1-bit memory cell is constituted by the capacitor structure C ′ including the capacitive insulating film 11 and the cell plate electrode 12 thereon. Then, the N-type diffusion layers 5 of the two memory cells adjacent to each other in the direction of the bit line conductor film 6 are shared by the two memory cells. The pair of N-type diffusion layers 4 and 5 of each memory cell are formed so as to be offset from each other in the direction along the gate electrode wiring 3, that is, in the direction of the word line conductor film 14. The capacitor structure T ′ of each memory cell has a so-called COB structure formed above the bit line conductor film 6, and as shown in FIG. Since it can be formed in a lower layer, the bit line conductor film 6 can have almost no step difference between the cell array portion and the peripheral portion, and the problem of fine processing of the bit line conductor film 6 can be solved.

Further, in the present embodiment, the COW structure in which the capacitor structure C ′ of each memory cell is formed in the layer above the word line conductor film 14 is as follows:
Since the word line conductor film 14 is disposed in the layer below the capacitor structure C ′, the word line conductor film 14 can be formed in a relatively lower layer as shown in FIG. 2B. Also, with respect to the word line conductor film 14, the step difference between the cell array portion and the peripheral circuit portion can be almost eliminated, and the problem of fine processing of the word line conductor film 14 can be solved.

Therefore, in the structure of the present embodiment, the storage node electrode 10 can be three-dimensionalized without substantially affecting the focal depth margin of either the bit line conductor film 6 or the word line 14. it can.
That is, it is possible to increase the effective area of the capacitor structure C ′ by forming the storage node electrode 10 as a three-dimensional structure such as a thick film, a cylinder, a fin, and unevenness.

Next, a method of manufacturing the structure of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a thickness of about 40 is formed on the surface of the P-type silicon substrate 1 by the LOCOS method.
An element isolation oxide film 2 of 00Å is formed. Then, a gate oxide film 7 having a thickness of about 100 to 150Å is formed on the silicon substrate 1 in the active region defined by the element isolation oxide film 2 in a steam atmosphere at 800 to 900 ° C. next,
By the LPCVD method, PH ₃ + SiH ₄ (or SiH ₂
Cl ₂ ) in a gas atmosphere at 550 to 600 ° C., and a non-doped silicon oxide film (not shown) is sequentially deposited on the N-type polycrystalline silicon layer 3 and similarly the N-type polycrystalline silicon layer 3 by the LPCVD method. Then, this is patterned to form a gate electrode wiring (gate electrode film) 3. Next, phosphorus (P) is introduced into the silicon substrate 1 by an ion implantation method at an acceleration energy of 40 to 60 KeV and a dose amount of 1 × 10 ^{13 to} 3 × 10 ¹³ cm ^-2 , and an LDD layer (not shown) is introduced. ) Is formed. Next, after forming a silicon oxide film 8 on the entire surface, this is anisotropically etched to form a sidewall oxide film 8 having a thickness of about 0.15 to 0.20 μm on the side wall of the gate electrode wiring 3. Next, by the ion implantation method,
Acceleration energy of 50 to 70 KeV-5 × 10 ¹⁵ cm ^-2
Arsenic (As) is introduced into the silicon substrate 1 at a dose of 2 to form N-type diffusion layers (active regions) 4 and 5.

Next, as shown in FIG. 3B, a non-doped silicon oxide film 17 is formed on the entire surface of the substrate by LPCVD in order to cover the surfaces of the diffusion layers 4 and 5, and photolithography using a photoresist 18 is performed. By the technique, the opening 4a is formed only on the N-type diffusion layer 4 of the silicon oxide film 17.
To form

Next, as shown in FIG. 3C, after removing the photoresist 18, an N-type polycrystalline silicon layer having a thickness of about 500 Å is formed by the LPCVD method and a tungsten silicide having a thickness of about 2000 Å is formed by the sputtering method. Bit lines 6 are formed by sequentially depositing and patterning them. Next, a BPSG film is formed on the entire surface by atmospheric pressure CVD to a thickness of about 4000 to 5000Å, and a first interlayer insulating film 9 is formed.

Next, as shown in FIG. 3D, a thickness of about 1000 to 15 is formed on the first interlayer insulating film 9 by the CVD method.
After depositing titanium nitride of 00Å and tungsten of about 4000Å on it to form a conductive film which becomes the word line conductor film 14, BPSG is performed by the atmospheric pressure CVD method.
The second interlayer insulating film 13 made of a film, N by the LPCVD method
The type polycrystalline silicon layers 10 ′ are deposited respectively, and these are patterned to form the word line conductor film 14. Here, the N-type polycrystalline silicon layer 10 ′ is made of a material having an etching rate sufficiently smaller than those of the first interlayer insulating film 9 and the non-doped silicon oxide film 17. For example, the etching rate ratio of the N-type polycrystalline silicon layer 10 ′ to the first interlayer insulating film 9 and the non-doped silicon oxide film 17 may be 1:50.

Next, as shown in FIG. 4A, a photolithography technique using a photoresist 19 is used to remove N.
A storage node contact hole 5a is formed on the mold diffusion layer 5. Although the opening formed in the photoresist 19 is larger than the size of the storage node contact hole 5a,
The N-type polycrystalline silicon layer 10 ′ formed in the same pattern as the word line conductor film 14 by patterning for forming the word line conductor film 14 is used as a stop mask for etching, and the first interlayer insulating film 9 and silicon are used. The oxide film 17 and the sidewall oxide film 8 are each etched to form the storage node contact hole 5a reaching the N-type diffusion layer 5 in a desired size.

Next, as shown in FIG. 4B, after removing the photoresist 19, a silicon oxide film 16 is formed on the entire surface by the LPCVD method and anisotropically etched to form the storage node contact 5a. The contact sidewall insulating film 16 is formed only on the side wall of the.

Next, as shown in FIG. 4C, LPCV
The N-type polycrystalline silicon layer 10 is deposited on the entire surface by the D method and is patterned to form the storage node electrode 1
Form 0. At this time, the portion of the N-type polycrystalline silicon layer 10 'formed on the word line conductor film 14 where the storage node electrode is not provided is also removed by etching.

After that, an ONO film having a thickness of about 50Å is formed on the entire surface to form a capacitive insulating film 11, and further, a thickness of about 1 is formed on the ONO film.
A cell plate electrode 12 composed of a 000Å N-type polycrystalline silicon layer is formed to obtain the structure shown in FIG.

In the manufacturing method described above, when the storage node contact hole 5a is opened, the N-type polycrystalline silicon layer 10 'formed on the word line 14 in the same pattern as that is used as a stop mask for etching. As shown in FIGS. 1B and 4A, the size of the holes 5a ′ defined by the photoresist 19 for the storage node contact holes 5a is determined by the distance between the word line conductor films 14 as shown in FIGS. The alignment margin x can be set to be larger than the above. Therefore, the contact diameter becomes large in photolithography, and a process margin can be provided. Although not shown in the drawings, the bit line 6 substantially acts as an etching stop mask in the direction perpendicular to the bit line conductor film 6, and as a result, the storage node contact 5a becomes a word line conductor film. 14 and the bit line conductor film 6 are formed in a self-aligned manner. Then, the contact sidewall insulating film 16 formed later electrically insulates them from both lines. Further, since tungsten, which is a refractory metal, is used as the material of the word line conductor film 14, a high-temperature heat treatment (about 800 ° C.) such as the formation of the capacitive insulating film, which is a process after forming the word line conductor film 14, and BPSG reflow. Up to now).

Further, in the manufacturing method described above, the contact hole is formed on the N type diffusion layers 4 and 5, the activation process after the ion implantation is performed, and the reflow process of the BPSG film 9 and the like. Since the capacitor portion of each memory cell is formed after that, there is also an advantage that a ferroelectric film that cannot be subjected to high-temperature heat treatment can be used as the capacitor insulating film of the capacitor structure C ′.

[0040]

According to the present invention, the word line conductor film can be formed in a layer lower than the capacitor structure of the memory cell, and the word line conductor film has almost no step between the cell array portion and the peripheral portion. As a result, the depth of focus margin at the time of microfabrication for the word line conductor film is secured, which enables miniaturization.

Further, the storage contact of each memory cell can be formed in both the bit line conductor film and the word line conductor film in a self-aligned manner, and an alignment margin on the outside of them can be eliminated, resulting in a device. Can be achieved.

[Brief description of drawings]

FIG. 1 is a plan view of a DRAM memory cell array according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a DRAM memory cell according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method of manufacturing a DRAM memory cell according to an embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a method of manufacturing a DRAM memory cell according to an embodiment of the present invention in the order of steps.

FIG. 5 is a plan view of a conventional DRAM memory cell array.

FIG. 6 is a cross-sectional view of a conventional DRAM memory cell array.

FIG. 7 is a circuit diagram showing an equivalent circuit of a conventional DRAM memory cell array.

[Explanation of symbols]

 1 P-type silicon substrate 2 Element isolation oxide film 3 Gate electrode wiring 4, 5 N-type diffusion layer (source / drain) 4a Bit contact 5a Storage node contact hole 6 Bit line 10 Capacitor lower electrode (storage node) 10 'Polycrystalline silicon Film 11 Capacitance insulating film 12 Capacitor upper electrode (cell plate) 14 Word line conductor film T'Transistor structure C'Capacitor structure

Claims (26)

[Claims] 1. A plurality of word line conductor films, a plurality of bit line conductor films intersecting the word line conductor films, and one word line conductor film and one bit line conductor film, respectively. What is claimed is: 1. A semiconductor memory device having a plurality of memory cells provided at intersections, comprising one transistor structure and one capacitor structure, wherein the transistor structure of each memory cell is formed on a surface portion of a semiconductor substrate. A gate formed between the pair of active regions and the pair of active regions above the semiconductor substrate.
A capacitor structure of each memory cell includes first and second electrode films and a dielectric film disposed between the first and second electrode films, and the first electrode film includes the pair of active films. A word line conductor layer is formed between the capacitor structure and the semiconductor substrate, the word line conductor film being formed between the capacitor structure and the semiconductor substrate; The contact hole of the first electrode film extends between the plurality of word line conductor films to the first active region of the transistor structure of the memory cell, and the second active layer is one of the bit line conductive films. A semiconductor memory device electrically connected to. 2. The semiconductor memory device according to claim 1, wherein the bit line conductive film is formed below the word line conductive film. 3. An insulating film for separating the word line conductor film from the first electrode film of a capacitor structure located above the word line conductor film, the first electrode film of the capacitor structure and the insulating film. The semiconductor memory device according to claim 1, further comprising a conductor film formed between the insulating film and the insulating film. 4. The semiconductor memory device according to claim 3, wherein the material of the conductor film and the material of the first electrode film of the capacitor structure are the same. 5. The semiconductor memory device according to claim 1, wherein the pair of active regions of each transistor structure of the memory cell are displaced from each other in the length direction of the word line conductor film. 6. A semiconductor substrate is prepared, and a pair of active regions formed on the surface of the semiconductor substrate and a gate formed between the pair of active regions above the semiconductor substrate. Forming a transistor structure including an electrode film, forming a first insulating film covering a surface of the semiconductor substrate including exposed portions of the pair of active regions, and forming a first insulating film on the first insulating film. Forming a bit line conductive film on the second insulating film, forming a second insulating film covering the bit line conductive film, forming a word line conductive film on the second insulating film, and forming the word line conductive film on the second insulating film. A method of manufacturing a semiconductor memory device, comprising forming a capacitor structure above and insulating from a line conductor film. 7. The step of forming the word line conductor film includes forming a first conductor film on the second insulating film, and forming a third insulating film on the first conductor film. Forming a second conductor film made of a material having an etching rate lower than that of the first conductor film and the second insulator film on the third insulator film; Patterning the second conductor film, the third insulating film and the first conductor film at the same time to form the word line conductor film, and the step of forming the capacitor structure is patterned. The second conductive film is used as an etching stop mask that defines the width of the contact hole measured in the width direction of the word line conductive film, and the second insulating film is etched through the first insulating film and the second insulating film. The first activity of the transistor structure A contact hole reaching the conductive layer, forming an inner wall insulating film in each of the contact holes, and forming a first conductor film on the patterned second conductor film and the inner wall insulator film. A first plate is formed by forming a plate film.
Patterning the coating film to obtain a first electrode film, forming a dielectric film on the patterned first electrode film, and forming a dielectric film on the dielectric film. 7. The method of manufacturing a semiconductor memory device according to claim 6, further comprising: forming a second electrode film on. 8. A memory cell comprising a transistor structure formed on a semiconductor substrate and a capacitor structure formed above the semiconductor substrate, wherein a plurality of the memory cells are arranged substantially in a matrix to form a memory. In a semiconductor memory device that constitutes a cell array, and a gate electrode wiring is formed by continuously and integrally forming gate electrodes of the transistors of a predetermined number of the memory cells arranged in one direction of the memory cell array, the first insulation A first active region of the transistor structure of the memory cell, which is formed on the gate electrode wiring via a layer, extends in a direction intersecting the gate electrode wiring, and is arranged in a direction intersecting the gate electrode wiring. A bit line conductor film which is in contact with the bit line conductor film, and the gate line is formed on the bit line conductor film through a second insulating layer. The word line conductor film extending in parallel with the pole wire and contacting the gate electrode wire at a predetermined position, and the transistor of each memory cell formed on the word line conductor film via a third insulating layer. A lower electrode film of the capacitor structure of each of the memory cells contacting the other active region of the structure, and the capacitor structure formed on the lower electrode film via the capacitive insulating film of the capacitor structure. And a semiconductor memory device having an upper electrode film. 9. A step of forming a gate electrode of a transistor that becomes a transfer gate of each memory cell and an active region that becomes a source / drain using a semiconductor substrate, and after forming a first insulating layer on the entire surface, Forming a first contact hole in the first insulating layer, the first contact hole reaching one active region of the transistor of each memory cell; and forming a first contact hole on the first insulating layer through the first contact hole. Patterning a bit line conductor film in contact with the one active region; forming a second insulating layer over the entire surface; and forming a word line conductive layer on the second insulating layer,
A step of sequentially forming a third insulating layer and a low-resistance polycrystalline silicon layer and processing them into a word line pattern; and using the polycrystalline silicon layer as an etching mask, the second insulating layer and the A step of forming a second contact hole in the first insulating layer, which reaches the other active region of the transistor of each memory cell, and a step of forming a silicon oxide film over the entire surface of the obtained substrate and then changing Isotropically etched to form a contact sidewall insulating film on the sidewall of the second contact hole; and a low resistance polycrystalline silicon layer is formed on the entire surface, which is then patterned to form the second contact Forming a lower electrode of the capacitor structure of each memory cell in contact with the other active region through a hole; and the capacitor on the lower electrode. A method of manufacturing a semiconductor memory device, comprising: forming a capacitive insulating film of a capacitor structure; and forming an upper electrode of the capacitor structure on the capacitive insulating film. 10. A semiconductor memory device comprising a wordline conductor film, a bitline conductor film intersecting one wordline conductor film, a transistor structure and a capacitor structure, wherein the wordline conductor film comprises: A semiconductor memory device, wherein the bit line conductor film is formed between the capacitor structure and the capacitor structure, and the bit line conductor film is formed in an upper layer than the transistor structure. 11. The transistor structure comprises a pair of active regions formed on a surface portion of a semiconductor substrate and a gate electrode film formed between the pair of active regions on an upper portion of the semiconductor substrate. The bit line conductor film is formed on a first insulating film covering the surface of the semiconductor substrate including at least the exposed portion of the active region, and the capacitor structure is insulated from the word line conductor film above the word line conductor film. 11. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is formed by forming. 12. A memory cell is formed of a transistor structure and a capacitor structure formed on a semiconductor substrate, and a plurality of the memory cells are arranged in a matrix to form a memory cell array. In a semiconductor memory device in which the gate electrodes of the transistors of a predetermined number of the memory cells arranged in the same direction are continuously and integrally formed to form a gate electrode wiring, the gate is provided via a first insulating film. Bit line conductor film formed on the gate electrode wiring, the word line conductor film formed on the bit line conductor film via the second insulating film, and the word line formed on the third insulating film. A semiconductor memory device having a lower electrode of the capacitor structure formed on a line conductor film. 13. A step of forming a transistor on a semiconductor substrate, the method comprising: forming a first insulating film on the entire surface; and forming a first contact hole in the first insulating film to reach one active region of the transistor. A step of forming, a step of patterning a bit line conductor film on the first insulating film, the bit line conductor film being in contact with the one active region through the contact hole, and a second insulating film formed on the entire surface. A step of forming a word line on the second insulating film,
A step of sequentially forming a third insulating film and a first conductive film and processing them into a pattern of word lines; and using the first conductive film as an etching mask, A step of forming a second contact hole reaching the other active region of the transistor in the insulating film and the first insulating film; and after forming a fourth insulating film on the entire surface of the obtained semiconductor substrate, Is anisotropically etched to form a contact side wall insulating film on the side wall of the second contact hole, and a second conductor film is formed on the entire surface of the obtained semiconductor substrate. And forming a lower electrode of the capacitor of the memory cell that contacts the other active region through the second contact hole. 14. A step of forming a transistor on a semiconductor substrate, the method comprising: forming a first insulating film over the entire surface; and forming a first contact hole in the first insulating film to reach one active region of the transistor. A step of forming, a step of patterning a bit line conductor film contacting the one active region through the contact hole on the first insulating film, and a second insulating film formed on the entire surface A step of forming a word line on the second insulating film,
A step of sequentially forming a third insulating film and processing them into a pattern of word lines; a second insulating film reaching the other active region of the transistor in the second insulating film and the first insulating film; Forming a contact hole, forming a contact side wall insulating film on the side wall of the second contact hole, forming a conductor layer on the entire surface of the obtained semiconductor substrate, and then patterning the conductor layer. Forming a lower electrode of the capacitor of the memory cell that contacts the other active region through the second contact hole. 15. A capacitor structure for storing information of a memory cell, a first conductive layer formed below the capacitor structure, and a first conductive layer intersecting the first conductive layer. A semiconductor memory device having a second conductive layer and a gate electrode of a field effect transistor connected to one of the first and second conductive layers. 16. A capacitor structure for storing information of a memory cell, a first conductive layer formed below the capacitor structure, and a first conductive layer intersecting with the first conductive layer. A semiconductor memory device having a second conductive layer and a transistor structure connected to one of the first and second conductive layers. 17. A semiconductor memory device comprising: a word line conductive film; a bit line conductive film intersecting with the word line conductive film; and a memory cell having a transistor structure and a capacitor structure. The word line conductive film and the bit line conductive film are formed in a lower layer than the capacitor structure, and the transistor structure is formed in a lower layer than the word line conductive film and the bit line conductive film. Semiconductor memory device. 18. The bit line conductive film is formed on the gate electrode wiring of the transistor structure, extends in a direction intersecting with the gate electrode wiring, and intersects with the gate electrode wiring. Arranged in a direction, contacting one active region of the transistor structure of the memory cell, the word line conductive film extending in parallel with the gate electrode wiring, and the gate electrode wiring. 18. The semiconductor memory device according to claim 17, wherein the lower electrode of the capacitor structure is contacted with the other active region of the transistor structure of the memory cell. 19. The semiconductor memory device according to claim 15, wherein one of the first and second conductive layers is a word line conductive film. 20. The semiconductor memory device according to claim 15, wherein one of the first and second conductive layers is a bit line conductive film. 21. The semiconductor memory device according to claim 16, wherein one of the first and second conductive layers is a word line conductive film. 22. The semiconductor memory device according to claim 16, wherein one of the first and second conductive layers is a bit line conductive film. 23. The semiconductor memory device according to claim 19, wherein the word line conductive film is connected to a gate electrode of the field effect transistor formed below the word line conductive film. 24. The semiconductor memory device according to claim 13, wherein the first conductor film is made of a material containing silicon. 25. The semiconductor memory device according to claim 13, wherein the second conductor film is made of a material containing silicon. 26. The semiconductor memory device according to claim 14, wherein the conductor layer is made of a material containing silicon.