JPH1050950A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bring the source region and the drain region of a micronized MISFET and wiring into a continuity without fail by etching a conductive film, with photoresist as a mask, and making the wiring which is electrically connected with either the source region or the drain region through a plug. SOLUTION: A polycrystalline silicon film is stacked on a semiconductor substrate 1 by CVD method. Next, a photoresist 11 which has island-shaped patterns to cover the top of each of n-type semiconductor regions 8 and 8 (source region and drain region) is made on the polycrystalline silicon film. Next, a plug A, which has island-shaped patterns on top of each of the n-type semiconductor regions 8 and 8 (source region and drain region), is made by self alignment by etching the polycrystalline silicon film until the surface of the silicon oxide film 7 on the gate electrode 6 and the surface of a field oxide film 2 are exposed, using the photoresist 11 for a mask. Hereby, the source region and the drain region and the wiring can be brought into a continuity without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to a miniaturized MISFET.
(Metal Insulator Semiconductor Field Effect Transi
The present invention relates to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a stor).

[0002]

2. Description of the Related Art In recent years, LSIs manufactured according to the design rule of deep submicron are approaching the limit of the alignment accuracy of an exposure apparatus. Therefore, a connection for connecting wiring to a source region and a drain region of a MISFET is required. When forming a hole (contact hole), it is difficult to secure a margin for mask alignment with a gate electrode.

As a countermeasure, a self-aligned (SAC) self-aligned contact hole is formed by using a silicon nitride film having a high selectivity of about 10 to 20 with respect to a silicon oxide film as an etching stopper. ) Technology is attracting attention. This is because an insulating film (cap insulating film) and a side wall insulating film (sidewall spacer) over the gate electrode are formed of a silicon nitride film, and a silicon oxide film deposited over the gate electrode is etched to form a source region, When forming a connection hole above the drain region, the cap insulating film of silicon nitride and the sidewall spacer are used as etching stoppers to prevent the gate electrode from being scraped, so that there is no need for a margin for alignment between the gate electrode and the connection hole. Technology.

A SAC using the above silicon nitride film
The technology is described in JP-A-4-342164.

[0005]

According to studies made by the present inventor, when a fine connection hole is to be formed above a source region and a drain region by using the above-described SAC technique, the following problem is to be solved. Problems arise.

That is, since the diameter of the bottom of the connection hole formed above the source region and the drain region using the SAC technique is smaller than the processing limit of lithography, the etching rate of the silicon oxide film is reduced. At the bottom of the silicon oxide film, and in some cases, the silicon oxide film cannot be removed. Further, when the etching rate of the silicon oxide film is reduced, even the cap insulating film of silicon nitride and the sidewall spacer, which are etching stoppers, are etched, and the gate electrode may be exposed inside the connection hole.

Further, even if the silicon oxide film can be removed, the source region exposed at the bottom of the connection hole,
Since the area of the drain region is small, the contact resistance between the wiring electrically connected through the connection hole and the source region and the drain region increases.

An object of the present invention is to provide a fine MISFE.
It is an object of the present invention to provide a technique for ensuring conduction between a source region and a drain region of T and a wiring.

Another object of the present invention is to provide a miniaturized MIS.
An object of the present invention is to provide a technique for reducing contact resistance between a source region and a drain region of a FET and a wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a MISFET, wherein (a) forming an element isolation region and an active region on a semiconductor substrate, and forming a gate insulating film on a surface of the active region. Depositing a first conductive film on the gate insulating film, and then depositing a first insulating film on the first conductive film, and (b) forming the first conductive film on a photoresist as a mask. Forming a gate electrode by etching the first insulating film and the first conductive film, and then implanting impurities into the semiconductor substrate to form a source region and a drain region; and (c) forming the gate electrode. Forming a sidewall spacer on the side wall of the gate electrode and the first insulating film by depositing a second insulating film on top of the gate electrode and etching the second insulating film; (d) After removing the gate insulating film on the surfaces of the source region and the drain region, a second conductive film is deposited on the semiconductor substrate, and then the source region and the drain region are formed on the second conductive film. Forming a photoresist having an island pattern covering each upper part, (e) using the photoresist having the island pattern as a mask, the surface of the first insulating film above the gate electrode and Forming plugs on each of the source region and the drain region by etching the second conductive film until the surface of the element isolation region is exposed; and (f) forming a third plug on the plug. After depositing an insulating film, etching back or polishing the third insulating film to expose the surface of the plug; (g)
After depositing a third conductive film on the third insulating film,
Forming a wiring that is electrically connected to one of the source region and the drain region through the plug by etching the third conductive film using a photoresist as a mask.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

In this embodiment, a memory cell selecting MIS
The present invention is applied to a method of manufacturing a DRAM including a memory cell having a stacked capacitor structure in which an information storage capacitor (capacitor) is arranged above an FET.

In order to form a memory cell of this DRAM, first, FIG. 1A (a plan view of about two memory cells) and FIG. 1B (a cross-sectional view of about two memory cells) are shown. As described above, after the field oxide film 2 is formed on the surface of the semiconductor substrate 1 made of, for example, p ⁻ -type single crystal silicon by the selective oxidation (LOCOS) method, a p-type impurity (for example, boron (B)) is added to the semiconductor substrate 1. The p-type well 3 is formed by ion implantation. Subsequently, a p-type impurity (for example, B) is ion-implanted into the p-type well 2 to form a p-type channel stopper layer 4, and then the surface of the active region of the p-type well 3 defined by the field oxide film 2. Then, a gate oxide film 5 is formed by a thermal oxidation method.

Next, as shown in FIGS. 2A and 2B, the gate electrode 6 of the MISFET for selecting a memory cell is formed.
(Word line WL) is formed. The gate electrode 6 (word line WL) is formed by depositing a polycrystalline silicon film (or a composite film obtained by laminating a high melting point metal film or a high melting point metal silicide film on the polycrystalline silicon film) on the semiconductor substrate 1 by a CVD method. Then, after depositing a silicon oxide film 7 thereon by a CVD method, these films are patterned and formed by etching using a photoresist as a mask. Gate electrode 6
The polycrystalline silicon film constituting the (word line WL) is doped with an n-type impurity (for example, phosphorus (P)) in order to reduce the resistance value.

Next, as shown in FIGS. 3A and 3B, an n-type impurity (for example, P) is ion-implanted into the p-type well 2 to form a gate electrode 6 (word line WL) on both sides. The n-type semiconductor regions 8 and 8 (source region and drain region) of the memory cell selection MISFET are formed in the p-type well 2.

Next, as shown in FIGS. 4A and 4B, a sidewall spacer 9 is formed on the side wall of the gate electrode 6 (word line WL). Sidewall spacers 9 are formed on the gate electrodes 6 (word lines WL) by CVD.
The silicon oxide film deposited by the method is processed by anisotropic etching.

Next, as shown in FIG. 5, the n-type semiconductor regions 8 and 8 (source region,
After the gate oxide film 6 on the surface of the (drain region) is removed by etching, as shown in FIG.
A polycrystalline silicon film 10 is deposited by the VD method. This polycrystalline silicon film 10 is doped with an n-type impurity (for example, P) in order to reduce its resistance value.

Next, as shown in FIGS. 7A and 7B, the upper portions of the n-type semiconductor regions 8 and 8 (source region, drain region) are covered on the polycrystalline silicon film 10. A photoresist 11 having an island pattern is formed.

Next, as shown in FIG. 8, using the photoresist 11 having the island pattern as a mask, the surface of the silicon oxide film 7 above the gate electrode 6 (word line WL) and the field oxide film 2 are formed. Is etched until the surface is exposed. This gives n
A plug 10A having an island pattern is formed on each of the type semiconductor regions 8 and 8 (source region and drain region) by self-alignment (self-alignment).

Next, after removing the photoresist 11,
As shown in FIG. 9, a silicon oxide film 12 covering the plug 10A is deposited on the semiconductor substrate 1 by a CVD method. Alternatively, instead of the silicon oxide film 12, a BPSG (Boron-doped Pho
A spo silicate glass (Spho) film or an SOG (spin on glass) film may be deposited.

Next, as shown in FIGS. 10 (a) and 10 (b), the silicon oxide film 12 is polished by etch-back or chemical mechanical polishing (CMP).
The surface of the plug 10A is exposed and the surface of the silicon oxide film 12 is flattened.

Next, as shown in FIG. 11, a silicon oxide film 13 is deposited on the silicon oxide film 12 by a CVD method, and then etched using a photoresist as a mask to form an n-type semiconductor region of a memory cell selecting MISFET. 8, 8
After exposing the surface of the plug 10A formed on one upper portion of the (source region, drain region), a bit line BL is formed on the plug 10A as shown in FIG. For the bit line BL, for example, a TiN film and a W film are deposited on the silicon oxide film 13 by a sputtering method, and a silicon nitride film 14 serving as a cap insulating film is deposited by a CVD method, and then the photoresist is used as a mask. These films are formed by patterning by etching.

Next, as shown in FIG.
Side wall spacers 15 are formed on the side walls. The side wall spacer 15 has a CV above the bit line BL.
The silicon nitride film deposited by the method D is formed by processing by anisotropic etching.

Next, as shown in FIG.
After the silicon oxide film 16 deposited on the upper surface of the silicon oxide film 16 is polished by a chemical mechanical polishing (CMP) method to planarize the surface, the silicon oxide film 1 is
6 and the silicon oxide film 13 are etched to form a connection hole 17 above the plug 10A formed on the other upper part of the n-type semiconductor regions 8, 8 (source region, drain region) of the memory cell selecting MISFET. I do.
At this time, since the silicon nitride film 14 above the bit line BL and the sidewall spacers 15 on the side walls serve as etching stoppers, the connection holes 17 are formed by self-alignment (self-alignment).

Next, as shown in FIG. 15, after a plug 21 is embedded in the connection hole 17, a storage electrode (lower electrode) 22 is formed above the connection hole 17. Plug 21
For example, a TiN film and a W film are deposited on the silicon oxide film 16 by a sputtering method, and then these films are formed by etching back. The storage electrode 22 is formed, for example, by depositing a W film on the silicon oxide film 16 by a sputtering method and then etching the W film using a photoresist as a mask.
The film is formed by patterning.

Next, as shown in FIG.
Insulating film 23 and plate electrode (upper electrode) 2
4 is formed. The capacitor insulating film 23 and the plate electrode (upper electrode) 24 are, for example,
After depositing a Ta ₂ O ₅ (tantalum oxide) film by the VD method, and then depositing a TiN film on the Ta ₂ O ₅ film by a sputtering method, these films are patterned by etching using a photoresist as a mask. At the same time. As a result, an information storage capacitance element C composed of the storage electrode 22, the capacitance insulating film 23, and the plate electrode 24 is formed. Through the above steps, the memory cell of the DRAM of the present embodiment is substantially completed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

The plug formed above the source region and the drain region can be made of a metal material such as a W film in addition to the polycrystalline silicon film. Further, the present invention can be applied not only to the case where a field oxide film is formed by a selective oxidation (LOCOS) method but also to a semiconductor integrated circuit device which performs element isolation by a groove formed in a semiconductor substrate.

In the above embodiment, the case where the present invention is applied to a method of manufacturing a memory cell of a DRAM has been described.
The present invention can be widely applied to a method of manufacturing a semiconductor integrated circuit device including a step of connecting a wiring to one of a source region and a drain region of an FET.

[0032]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the manufacturing method of the present invention, a plug for connecting a source region and a drain region of a MISFET to a wiring is formed in a self-aligned manner without forming a connection hole. The region, the drain region, and the wiring can be reliably conducted.

(2) According to the manufacturing method of the present invention, the source region and the drain region can be brought into contact with the plug over a wide area, so that the contact resistance between the source region and the drain region and the wiring can be reduced. it can.

(3) According to the manufacturing method of the present invention, the cap insulating film on the gate electrode and the sidewall spacers on the side walls are not undesirably etched, so that the short-circuit between the gate electrode and the plug is ensured. Can be prevented.

(4) According to the manufacturing method of the present invention, a process for forming a connection hole by etching the insulating film above the source region and the drain region is not used, so that the semiconductor substrate (source region, drain region ) Damage can be avoided.

(5) Manufacturing of the present invention in which a conductive film is etched using a photoresist having an island pattern as a mask to form a self-aligned (self-aligned) plug above the source region and the drain region. According to the method, a large area to be etched can be ensured as compared with the SAC technique in which a connection hole having a size equal to or smaller than the processing limit of lithography is formed above the source region and the drain region.
The end point of the etching can be detected by a plasma emission monitor or the like, which is difficult with the AC technique, and the end point of the etching can be reliably determined.

(6) According to the manufacturing method of the present invention, the cap insulating film above the gate electrode and the sidewall spacer on the side wall can be formed of a silicon oxide film having a lower dielectric constant than the silicon nitride film. In addition, the parasitic capacitance of the gate electrode can be reduced as compared with the case where the SAC technique in which the cap insulating film and the sidewall spacer are formed of the silicon nitride film is used.

[Brief description of the drawings]

FIGS. 1A and 1B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention; FIGS.

FIGS. 2A and 2B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention; FIGS.

3A and 3B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention;

FIGS. 4A and 4B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention; FIGS.

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIGS. 7A and 7B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention; FIGS.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

10A and 10B are a main part plan view and a cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field oxide film 3 p-type well 4 p-type channel stopper layer 5 gate oxide film 6 gate electrode 7 silicon oxide film 8 n-type semiconductor region 9 sidewall spacer 10 polycrystalline silicon film 10A plug 11 photoresist 12 silicon oxide Film 13 Silicon oxide film 14 Silicon nitride film 15 Sidewall spacer 16 Silicon oxide film 17 Connection hole 21 Plug 22 Storage electrode (lower electrode) 23 Capacitive insulating film 24 Plate electrode (upper electrode) C Information storage capacitor BL Bit line WL Word line

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising: (a) forming an element isolation region and an active region on a semiconductor substrate and forming a gate insulating film on a surface of the active region; A first layer on the gate insulating film;
Depositing a conductive film, and then depositing a first insulating film on top of the first conductive film, (b) forming the first insulating film and the first conductive film using a photoresist as a mask; Forming a source electrode and a drain region by ion-implanting impurities into the semiconductor substrate after etching a gate electrode by etching the semiconductor substrate; and (c) depositing a second insulating film on the gate electrode. Forming sidewall spacers on side walls of the gate electrode and the first insulating film by etching the second insulating film; and (d) forming the gate insulating film on the surface of the source region and the drain region. After removing the film, a second conductive film is deposited on the semiconductor substrate, and then, an upper surface of the second conductive film has an island-shaped pattern covering each of the source region and the drain region. Forming a photoresist,
(E) using the photoresist having the island pattern as a mask, etching the second conductive film until the surface of the first insulating film above the gate electrode and the surface of the element isolation region are exposed; Forming a plug on each of the source region and the drain region, and (f) etching back or polishing the third insulating film after depositing a third insulating film on the plug. (G) depositing a third conductive film on the third insulating film, and then etching the third conductive film using a photoresist as a mask. The source region through the plug,
Forming a wiring electrically connected to one of the drain regions. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second conductive film is a polycrystalline silicon film. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second conductive film is a tungsten film. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first and second insulating films are silicon oxide films. Production method. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said third insulating film is polished by a chemical mechanical polishing method. A method for manufacturing an integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said MISFE
A method for manufacturing a semiconductor integrated circuit device, wherein T is a memory cell selecting MISFET constituting a memory cell of a DRAM. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said wiring is a bit line.