JP2680376B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a contact structure in a MOSFET, a DRAM, or the like.

(Prior Art) In recent years, with the advance of semiconductor technology, particularly the advance of microfabrication technology, the so-called MOS type DRAM has been rapidly advanced in integration and capacity.

With this high integration, the area of a capacitor for storing information (charge) has been reduced, and as a result, a memory error has been read out erroneously, or a memory error such as the destruction of the memory content due to α rays has become a problem. Has become. Further, the gate length of the transistor is shortened, and the reliability of the transistor is also a problem.

As one method for solving such a problem and achieving higher integration and higher capacity, a storage node formed of polycrystalline silicon or the like is formed on a silicon substrate to increase the area occupied by a capacitor. , Increase the capacitance of the capacitor,
Various methods have been proposed to increase the amount of accumulated charge.

One of them is that a MOS capacitor is stacked on a memory cell region, and one electrode of the capacitor is electrically connected to one electrode of a switching transistor formed on a semiconductor substrate. There has been proposed a memory cell structure called a stacked memory cell in which the capacitance is increased.

As shown in FIGS. 5 (a) and 5 (b), this stacked type memory cell has one memory cell region which is element-isolated by an element isolation insulating film 102 formed in a p-type silicon substrate 101. Source / drain regions 104a and 104b and n-type diffusion layers and source / drain regions 104a and 104
A gate electrode 106 is formed between the gate insulating film 105 between b to form a MOSFET as a switching transistor, and a gate electrode 106 of the MOSFET and an adjacent memory cell of the MOSFET are formed on the upper layer so as to contact the source region 104a of the MOSFET. Insulating film 107 on the gate electrode (word line) of MOSFET
The lower capacitor electrode 110 and the upper capacitor electrode 112, which are formed through the above, sandwich the capacitor insulating film 111 to form a capacitor.

This stacked memory cell is formed as follows.

That is, this stacked memory cell has a p-type silicon substrate 101 and source-drain regions 104a and 104b made of n-type diffusion layers and a gate insulating film 105 between the source-drain regions 104a and 104b. The gate electrode 106 is formed to form a MOSFET as a switching transistor.

Next, after forming a silicon oxide film as the insulating film 107 over the entire surface of the substrate, a storage node contact 108 for making contact with the drain region 104b is formed, and a lower portion made of a heavily doped polycrystalline silicon layer is formed. A pattern of the capacitor electrode 110 is formed.

Then, a capacitor insulating film 111 made of a silicon oxide film and a polycrystalline silicon layer are sequentially deposited on the lower capacitor electrode 110.

After that, ions such as phosphorus are ion-implanted into the polycrystalline silicon layer, and heat treatment is performed at 900 ° C. for about 120 minutes to form a polycrystalline silicon layer which is highly doped to have a desired conductivity.

Finally, by patterning the heavily doped polycrystalline silicon layer, a MOS capacitor sandwiching the capacitor insulating film 111 is formed by the upper capacitor electrode 112 and the lower capacitor electrode 110. A memory cell is obtained.

In such a configuration, the storage node electrode can be expanded to above the element isolation region, and the step of the storage electrode can be used, so that the capacitance of the capacitor can be increased several times to several tens times that of the planar structure. .

However, with such a structure, there has been a limit in maintaining the capacitance of the capacitor due to high integration.

By the way, in such a multilayer capacitor, the substantial area of the capacitor is assumed to be a lower capacitor electrode having a constant thickness, which is composed of the area of the upper surface of the lower capacitor electrode located on the lower layer side and the side surface portion after pattern formation. In this case, as the occupied area of the memory cell decreases, the ratio of the side surface portion to the actual area increases.

The present applicant pays attention to this point, and forms a base film such as a conductor film outside the contact hole formed in the insulating film below the storage node electrode (lower capacitor electrode) to determine the area of the side surface portion of the storage node electrode. Has been proposed (Japanese Patent Application No. 63-119201).

According to this structure, the decrease in the capacitor capacitance due to the decrease in the occupied area of the memory cell is compensated by forming the base film such as the conductor film outside the contact hole and increasing the area of the side surface portion of the storage node electrode. It is possible to achieve high integration.

However, even in such a structure, there is a great demand for the reduction of the area around the contact hole due to the design rule accompanying the high integration, and the contact hole for contacting the storage node electrode to the source / drain region of the switching transistor is formed. Even when a slight displacement occurred during the formation, a short circuit often occurred between the gate of the switching transistor and the storage node electrode of the capacitor.

(Problems to be Solved by the Invention) As described above, even in the DRAM having the stacked memory cell structure, the memory cell occupation area is reduced as the miniaturization of elements accompanying the higher integration advances, and the conventional stacked memory In the cell structure, the area of the flat portion of the storage node electrode has been increasingly reduced, and it has become difficult to secure sufficient capacitor capacitance.

On the other hand, a short circuit between the gate of the switching transistor and the storage node electrode of the capacitor due to the reduction of the occupied area of the memory cell has been a serious problem.

The present invention has been made in view of the above circumstances, and provides a highly reliable memory cell structure capable of ensuring a sufficient capacitor capacity, regardless of the reduction of the occupied area of the memory cell, and a manufacturing method thereof. The purpose is to do.

[Configuration of the invention]

(Means for Solving the Problems) In the present invention, a MOSFET formed on a semiconductor substrate,
The lower capacitor electrode is laminated on the upper layer through the first insulating film, and the lower capacitor electrode contacts one of the source and drain regions of the MOSFET through the first contact hole formed in the first insulating film. A memory cell including the formed capacitor is formed, a second insulating film is formed on the upper layer of the capacitor, and the second insulating film is formed on the upper layer.
Through the second contact hole formed in the insulating film of
In a semiconductor memory device in which a bit line that contacts the other of the source and drain regions of an SFET is formed, in a first contact hole formed in the first insulating film, a sidewall of the lower capacitor electrode and the MOSFET is formed. A sidewall insulating film is provided to insulate the gate electrode, and the lower capacitor electrode is deposited so as to be located on a periphery of the first contact hole and on the first insulating film. A conductor layer and a second conductor layer formed so as to cover the side wall surface and the bottom surface of the first conductor layer and the first contact hole in which the side wall insulating film is formed. Is characterized by.

Further, in the method of the present invention, after forming an interlayer insulating film on the surface of a switching transistor, a conductor layer is deposited prior to the formation of a storage node contact and a capacitor, and a sidewall insulating film is formed on the sidewall of the contact after the storage node contact is formed. To form.

(Operation) According to the above configuration, the lower capacitor electrode is the first capacitor.
A first conductor layer deposited so as to be located on the first insulating film at the peripheral edge of the contact hole, and the first contact on which the first conductor layer and the sidewall insulating film are formed. Second formed so as to cover the side wall surface and the bottom surface of the hole
Since it has a two-layer structure with the conductor layer of
The area of the side surface portion of the lower capacitor electrode increases due to the thickness of the conductor layer, and it is possible to compensate for the decrease in the capacitor capacitance due to the decrease in the occupied area of the memory cell.

Further, due to the presence of the side wall insulating film formed on the side wall of the contact hole, even when the distance between the gate electrode and the storage node contact is small, it is possible to prevent a short circuit between the gate electrode and the storage node electrode, and to improve reliability. Can be improved.

According to the method of the present invention, after the interlayer insulating film is formed on the surface of the switching transistor, the conductor layer is deposited before the formation of the storage node contact and the formation of the capacitor. In the etching process for forming the contact, the interlayer insulating film is protected by the conductor layer without being damaged, and the presence of the sidewall insulating film can prevent the gate electrode and the storage node electrode from being short-circuited. , Reliability is improved.

Further, the side wall insulating film can be easily formed by anisotropic etching without depositing a mask after the deposition, and if the underlying conductor layer is composed of a conductor layer made of the same material as the storage node electrode, the same etching can be performed. It can be easily patterned in the process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 (a) and 1 (b) are adjacent to each other in the bit line direction of the DRAM having the stacked memory cell structure according to the embodiment of the present invention.
It is the top view which shows a bit part, and its AA 'sectional view.

This DRAM has an interlayer insulating film 6a formed on the surface of the MOSFET.
A base conductor layer 7a made of a polycrystalline silicon film is formed on the surface of the storage node contact 11 around the storage node contact 11, and a lower capacitor electrode 7b, that is, a storage node electrode is formed on the base conductor layer 7a. It is characterized in that a side wall insulating film made of a silicon nitride film is formed. Other parts are the same as those of the DRAM of the conventional stacked memory cell structure.

That is, in the active region isolated by the element isolation insulating film 2 formed in the p-type silicon substrate 1 having the impurity concentration of about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ , the n − type which forms the source / drain region is formed. A gate electrode 4 is formed between the diffusion layers 5 ₁ and 5 ₂ and the source / drain regions via the gate insulating film 3 to form a MOSFET, and is formed in the interlayer insulating film 6a formed on the upper layer. Storage node contact
11 through, and contact the n- form diffusion layers 5 _1, an interlayer insulating film 6 so as to cover the (via the base conductor layer 7a) lower capacitor electrode 7b is formed, is further laminated on the upper layer A capacitor is formed by the capacitor insulating film 8 and the upper capacitor electrode 9.

The gate electrodes 4 are continuously arranged in one direction of the memory array to form a word line.

Further, a contact hole 12 for bit line contact is formed in a silicon oxide film as an interlayer insulating film 6b covering the upper layer, and is composed of a composite film of a highly doped polycrystalline silicon layer and an aluminum silicide film. Bit line 13 is connected.

Next, a method of manufacturing the DRAM will be described with reference to the drawings.

First, as shown in FIG. 2 (a), the impurity concentration of 10 ¹⁵ ~
In a p-type silicon substrate 1 of about 10 ¹⁶ cm ^-3 , a normal LOCO
The element isolation insulating film 2 is formed by the S method.

Then, a 10 nm-thickness silicon oxide layer and a 300 nm-thick polycrystalline silicon layer are deposited by a thermal oxidation method, and these are patterned by a photolithography method and a reactive ion etching method to form a gate insulating film 3 and a gate electrode 4.

Then, as shown in FIG. 2 (b), As ions are ion-implanted by using the gate electrode 4 as a mask to form source / drain regions composed of n − type diffusion layers 5 ₁ and 5 ₂ to form a switching transistor. Is formed, and a silicon oxide film as the interlayer insulating film 6a and a polycrystalline silicon film 7a are sequentially deposited on the upper layer by the CVD method.

Furthermore, as shown in FIG. 2 (c), this storage
The polycrystalline silicon film on the node contact 11 is selectively removed to form the underlying conductor layer 7a and the storage node contact 11.

After that, as shown in FIG. 2D, a silicon nitride film 14 having a thickness of 1500 Å is deposited by the CVD method.

Then, as shown in FIG. 2 (e), the storage / storage is performed by the reactive ion etching (anisotropic etching) method.
The side wall insulating film 14 is formed by leaving the side wall of the node contact 11 only.

After that, as shown in FIG. 2 (f), after cleaning the contact surface by dilute hydrofluoric acid treatment or the like, a polycrystalline silicon film having a film thickness of 3000 Å is deposited and doped on the entire surface.

Further, as shown in FIG. 2G, the lower capacitor electrode 7b as the storage node electrode is formed and the underlying conductor layer 7a is patterned by the photolithography method and the anisotropic etching method. Here, the area of the side surface of the lower capacitor electrode 7b is increased by the film thickness of the base conductor layer 7a formed around the contact 11.

Then, as shown in FIG. 2 (h), CV
A silicon nitride film is deposited on the entire surface by D method to a thickness of about 10 nm, and then oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 8 having a two-layer structure of a silicon oxide film and a silicon nitride film. Then, a polycrystalline silicon film having a film thickness of 3000 Å is further deposited on the entire surface, doped, and then patterned by photolithography and reactive ion etching to form an upper capacitor electrode 9.

Further, as shown in FIG. 2 (i), by using this upper capacitor electrode 9 as a mask, an unnecessary portion of the capacitor insulating film 8
Is removed, and an interlayer insulating film made of a silicon oxide film is formed on the entire surface.
Deposit 6b.

After that, the bit line contact 12 is opened by a photolithography method and a reactive ion etching method, an aluminum layer is deposited, and further patterned by a photolithography method and a reactive ion etching method to form a bit line 13, and The basic structure of the cell portion as shown in FIG. 1A and FIG. 1B is completed.

According to the above configuration, the underlying conductor layer 7a which becomes a part of the lower capacitor electrode 7 before the storage node contact 11 is opened in the interlayer insulating film 6a on the surface of the switching transistor.
To form a polycrystalline silicon layer.

Therefore, even if the surface is cleaned by treatment with dilute hydrofluoric acid after the storage node contact opening, the polycrystalline silicon film serves as a mask to prevent the silicon oxide film 6a from being etched and prevent the generation of pinholes. It

Further, since the sidewall insulating film made of a silicon oxide film is formed on the sidewall of the storage node contact,
Even if a part of the gate electrode is exposed by the smoothing process at the time of contact opening, this side wall insulating film covers the gate electrode, and a short circuit between the gate electrode and the storage node electrode can be avoided.

Further, since the polycrystalline silicon film as the underlying conductor layer is formed under the lower capacitor electrode as the storage node electrode, the capacitor electrode area can be increased by the thickness, and the capacitor capacitance is maintained. be able to. Therefore, the area of the side surface of the lower capacitor electrode is doubled as compared with the case where the underlying conductor layer is not provided, and the overall cell capacitance can be increased to about 1.3 to 1.4 times.

In this example, the conductor layer made of polycrystalline silicon was formed as the base of the lower capacitor electrode, but an insulating film was formed and the lower capacitor electrode was formed so as to cover the insulating film, and only the side surface of the insulating film was formed. Since the side area of the lower capacitor electrode can be increased, the capacitance of the capacitor can be increased.

Next, another embodiment of the present invention will be described in detail with reference to the drawings.

This DRAM has the structure shown in FIG.
As shown in FIG. 3B, a groove V is formed at the bottom of the storage node contact 11, and the lower capacitor electrode as the storage node electrode is deeply inserted by the depth of this groove. The capacitor area is further increased. The same parts are designated by the same reference numerals.

In forming this DRAM, as shown in FIGS. 2 (a) to 2 (e) in the first embodiment, a polycrystalline silicon film as a base conductor layer is deposited and the storage node contact 11 is formed. And the side wall insulating film 14 are formed up to the step of forming the same.

Thereafter, as shown in FIG. 4A, etching is performed to form a groove V on the surface of the substrate exposed in the storage node contact 11, and thereafter, the same steps as those in the first embodiment are performed again. Is formed by continuing.

That is, after this, as shown in FIG. 4B, after cleaning the contact surface by dilute hydrofluoric acid treatment or the like, a polycrystalline silicon film 7b having a film thickness of 3000 Å is deposited and doped on the entire surface.

At this time, even if trench V formed at the bottom of storage node contact 11 is formed so as to penetrate deeper than the source / drain region, impurity region 5'is formed by diffusing the impurity from storage node electrode 7b. Therefore, it is not necessary to form an offset.

Further, as shown in FIG. 4C, the lower capacitor electrode 7b as the storage node electrode is formed and the underlying conductor layer 7a is patterned by the photolithography method and the anisotropic etching method. Here, the side area of the lower capacitor electrode 7b is increased by the film thickness of the base conductor layer 7a formed around the contact 11.

Then, as shown in FIG. 4 (d), CV
A silicon nitride film is deposited on the entire surface by D method to a thickness of about 10 nm, and then oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 8 having a two-layer structure of a silicon oxide film and a silicon nitride film. Then, a polycrystalline silicon film having a film thickness of 3000 Å is further deposited on the entire surface, doped, and then patterned by photolithography and reactive ion etching to form an upper capacitor electrode 9.

Further, as shown in FIG. 4 (e), the capacitor insulating film 8 of the unnecessary portion is formed by using the upper capacitor electrode 9 as a mask.
Is removed, and an interlayer insulating film made of a silicon oxide film is formed on the entire surface.
Deposit 6b.

After that, the bit line contact 12 is opened by a photolithography method and a reactive ion etching method, an aluminum layer is deposited, and further patterned by a photolithography method and a reactive ion etching method to form a bit line 13, and a third line is formed. The basic structure of the cell portion as shown in FIGS. 3A and 3B is completed.

According to this structure, in addition to the effect of the first embodiment, the capacitor area is further increased by the amount that the lower capacitor electrode enters the trench.

In these examples, as the capacitor insulating film, in addition to a two-layer structure film of a silicon oxide film and a silicon nitride film, a metal oxide film such as a silicon oxide film or tantalum pentoxide (Ta ₂ O ₅ ) is used. Is also good.

Further, although the polycrystalline silicon film is used as the lower capacitor electrode, the lower capacitor electrode is not necessarily limited to the polycrystalline silicon film, and can be appropriately changed.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the base conductor layer is formed around the storage node contact on the surface of the interlayer film formed on the surface of the MOSFET to increase the side area of the storage node electrode. However, since the reduction of the capacitor area due to the reduction of the cell area is compensated, the reliability can be improved while maintaining a sufficient capacitor capacitance even when the integration is increased.

[Brief description of the drawings]

1 (a) and 1 (b) are diagrams showing a DRAM having a stacked memory cell structure according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (i) are the same stacked memory cell structure. 3A to 3D are views showing a DRAM having a stacked memory cell structure according to another embodiment of the present invention, and FIGS. 4A to 4C. (E) DR of the same stacked memory cell structure
FIG. 5 is a diagram showing an AM manufacturing process, and FIG. 5 is a diagram showing a conventional DRAM. 1 ... p-type silicon substrate, 2 ... element isolation insulating film, 3
...... Gate insulation film, 4 ...... Gate electrode, 5 …… N-type diffusion layer, 6,6a, 6b …… Interlayer insulation film, 7a …… Base conductor layer, 7b…
... Lower capacitor electrode, 8 ... Capacitor insulating film, 9 ...
… Upper capacitor electrode, 11 …… Storage node contact, 12 …… Bit line contact, 13 …… Bit line, 14
…… Sidewall insulating film, 101 …… p-type silicon substrate, 102 ……
Element isolation insulating film, 103 ... 104a, 104b ... n-type diffusion layer, 10
5 ... Gate insulating film, 106 ... Gate electrode, 107 ... Insulating film, 108 ... Storage node contact, 110 ... Lower capacitor electrode, 111 ... Capacitor insulating film, 112 ... Upper capacitor electrode.

Claims (3)

(57) [Claims] 1. A lower capacitor electrode formed by stacking a MOSFET formed on a semiconductor substrate and a first insulating film formed on the upper layer of the MOSFET via a first contact hole formed in the first insulating film. And a capacitor formed so as to contact one of the source and drain regions of the MOSFET, a second insulating film is formed on the upper layer of the capacitor, and the second insulating film is formed on the second insulating film. A semiconductor memory device in which a bit line that contacts the other of the source and drain regions of the MOSFET is formed through a second contact hole formed in an insulating film, the first memory film being formed in the first insulating film. A sidewall insulating film that insulates the lower capacitor electrode and the gate electrode of the MOSFET from each other is provided on the sidewall of the contact hole, and the lower capacitor electrode is A first conductor layer deposited so as to be located on the first insulating film on the periphery of the first contact hole; and the first conductor layer and the sidewall insulating film on which the first conductor layer is formed. And a second conductor layer formed so as to cover the side wall surface and the bottom surface of the contact hole, the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the first and second conductor layers are made of the same material. 3. A cell is formed by a MOSFET and a capacitor, and the MO is formed through a storage node contact opened in a first insulating film covering the surface of the substrate on which the MOSFET is formed.
In a method of manufacturing a semiconductor memory device having a stacked capacitor structure in which a capacitor is stacked on an insulating film so that a storage node electrode of the capacitor is connected to a source or drain region of an SFET, a MOSFET forming step of forming a MOSFET on a semiconductor substrate. An interlayer insulating film depositing step of depositing a first insulating film as an interlayer insulating film, a base conductor layer depositing step of depositing a conductor layer serving as a base layer on the surface of the interlayer insulating film, A contact forming step of opening a storage node contact in the underlying conductor layer, and a sidewall insulating film for depositing a second insulating film on the surface and etching by anisotropic etching to form an insulating film on the sidewall of the storage node contact. In the forming process, the lower capacitor electrode is deposited and patterned on the upper layer of the interlayer insulating film and the underlying conductor layer. Together, a lower capacitor electrode forming step of similarly patterning the underlying conductor layer, a capacitor insulating film forming step of forming a capacitor insulating film on the surface of this lower capacitor electrode, and an upper capacitor electrode forming on the surface of this capacitor insulating film A method of manufacturing a semiconductor memory device, comprising: an upper capacitor electrode forming step.