JP2739983B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly, to a structure and a manufacturing method of a dynamic RAM (DRAM) having a stacked capacitor cell structure.

(Prior Art) High integration of DRAM (Dynamic Random Access Memory), one of the semiconductor memory devices, has been achieved by miniaturization of the element size. For this reason, the S / N ratio has been reduced, and adverse effects such as erroneous reading of memory contents and data destruction easily due to incidence of α-rays have become apparent.

For this reason, various types of memory cells have been proposed for the purpose of increasing the storage capacity. For example, a trench capacitor is formed by digging a groove perpendicular to a substrate and using a side wall thereof. Since the capacitance of the trench capacitor is determined by the depth of the groove, a large capacitance can be obtained with a very small area. However, this method has a problem such as a leak current between adjacent grooves. In addition to the trench capacitor, there is a stacked capacitor having a stacked capacitor cell structure. As this type of stacked capacitor memory cell, for example, the one disclosed in JP-A-62-179759 is known. This is because, as shown in FIG. 5, P-type semiconductor substrate 21 n ⁺ -type high-concentration source which impurities are introduced on top, drain regions 22 _1, 22 ₂ are formed. Further, for example, an element isolation oxide film 23 is formed by a selective oxidation method. The gate oxide film 24 is formed by thermal oxidation, and further depositing a first layer polycrystalline silicon film, a gate electrode 25 _1, 25 ₂ is formed by patterning. Thus, a MOS transistor of the memory cell is obtained. Further, a first interlayer insulating film 26 is formed so as to cover the gate electrode 25. Source or on the drain region 22 _2, the contact hole 28 for making contact with the lower capacitor electrode 27 made of polycrystalline silicon film is provided. The lower capacitor electrode 27 is connected from the source or drain region 22 ₂ to the gate electrode 25 ₁
It is formed on the surface of the first interlayer insulating film 26 up to a predetermined position. Further, a dielectric film 28 is formed over the lower capacitor electrode 27 and over the first interlayer insulating film 26. Upper capacitor electrode made of polycrystalline silicon film
29 is a lower capacitor electrode 27 on the dielectric film 28.
And a predetermined distance between the bit line and the second interlayer insulating film 30 formed on the surface of the upper capacitor electrode 29.
It is separated from the contact hole 31. Further, the drain or source regions 22 ₁ on the provided bit line contact hole 31, for example, a bit line 32 made of Al is formed.

In such a laminated capacitor cell structure, the area occupied by the memory cell increases in plan view. By increasing the surface area of the lower capacitor electrode 27 and guaranteeing a substantial area of the capacitor, a large storage capacity can be obtained. However, the conventional multilayer cell structure has the following problems. That is, when forming the bit line contact hole 31, the bit line 32 and the gate electrode 25 ₁ is required to prevent the short circuit by etching using photolithography. However, in the multilayer capacitor cell, due to its structure, an opening is formed by etching from the second interlayer insulating film 30 to the semiconductor substrate 21 through the first interlayer insulating film 26, so that the etching depth becomes large. Due to the large unevenness of the surface, sufficient drilling accuracy cannot be obtained. In contrast, release the bit line contact hole 31 from the gate electrode 25 ₁ and Kitashi lowering the degree of integration, also lead to contact failure Smaller bit line contact hole.

(Problems to be Solved by the Invention) As described above, the DR of the conventional multilayer capacitor cell structure
In AM, since the bit line contact hole to be opened by photolithography is deep and the surface roughness is large, trying to prevent a short circuit between the bit line and the gate electrode of the MOS transistor reduces the degree of integration and leads to contact failure There was a problem of doing.

An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same that solve such problems.

[Constitution of the Invention] (Means for Solving the Problems) The present invention has been made in view of the above circumstances, and a first invention is a MOS transistor formed on a semiconductor substrate,
A first interlayer insulating film provided on the semiconductor substrate on which the MOS transistor is formed, and a source or drain region of the MOS transistor through a first opening provided in the first interlayer insulating film; And a lower capacitor electrode formed so as to extend over the gate region, a dielectric film formed on the surface of the lower capacitor electrode, and a lower capacitor electrode provided through the dielectric film to cover the lower capacitor electrode. An upper capacitor electrode, a second interlayer insulating film provided on the upper capacitor electrode,
A second opening provided from the interlayer insulating film to the depth of the upper capacitor electrode, and a second opening provided to reach the drain or source region of the MOS transistor from the upper capacitor electrode in the second opening. A third opening having a smaller opening width than the second opening, an insulating layer formed at a portion of the upper capacitor electrode located at the second and third openings, And a bit line provided in contact with the drain or source region via a contact hole formed by a third opening.

In a second aspect, a step of forming a MOS transistor on a semiconductor substrate substrate, and a step of providing a first interlayer insulating film on the semiconductor on which the MOS transistor is formed,
Contacting the source or drain region of the MOS transistor through a first opening provided in the first interlayer insulating film and extending over the gate region to form a lower capacitor electrode; Forming a dielectric film on the surface of the capacitor electrode; forming an upper capacitor electrode covering the lower capacitor electrode via the dielectric film; and forming an opening in the upper capacitor electrode in advance corresponding to the bit line contact hole. Forming a second interlayer insulating film on the upper capacitor electrode; and forming an opening in the second interlayer insulating film larger than the opening formed in the upper capacitor electrode so as to reach the upper capacitor electrode. Forming a drain or source region of the MOS transistor using the opening formed in the upper capacitor electrode as a mask. Etching the first interlayer insulating film so as to reach the upper limit, converting the exposed portion of the upper capacitor electrode into an insulating film, and forming a contact hole including the second and third openings. Forming a bit line by contacting the drain or source region via the semiconductor memory device.

According to a third aspect of the present invention, there is provided a MOS transistor formed on a semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate on which the MOS transistor is formed, and a MOS transistor formed on the first interlayer insulating film. Through the first opening provided
A lower capacitor electrode formed in contact with the source or drain region of the MOS transistor and extending over the gate region; a dielectric film formed on the surface of the lower capacitor electrode; and a lower capacitor interposed through the dielectric film. An upper capacitor electrode provided over the electrode, a second interlayer insulating film provided on the upper capacitor electrode,
A second opening provided to penetrate the upper capacitor electrode from the second interlayer insulating film to reach the drain or source region of the MOS transistor; and a second opening formed in the upper capacitor electrode. An insulating layer formed on an exposed portion and a bit line provided in contact with the drain or source region through a contact hole formed by the second opening are provided. Provided is a semiconductor memory device.

In a fourth aspect, a step of forming a MOS transistor on a semiconductor substrate, and a step of providing a first interlayer insulating film on the semiconductor substrate on which the MOS transistor is formed,
Contacting the source or drain region of the MOS transistor through a first opening provided in the first interlayer insulating film and extending over the gate region to form a lower capacitor electrode; Forming a dielectric film on the surface of the capacitor electrode, forming an upper capacitor electrode covering the lower capacitor electrode via the dielectric film, and forming a second interlayer insulating film on the upper capacitor electrode Forming a second opening from the second interlayer insulating film through the capacitor electrode to reach the drain or source region of the MOS transistor; and forming the second opening in the upper capacitor electrode. Forming an insulating layer on a portion exposed in the opening;
Forming a bit line by contacting the drain or source region through a contact hole formed by the second opening.

(Operation) As described above, in the semiconductor memory devices of the first and second inventions and the method of manufacturing the same, the bit line contact hole is formed using the upper capacitor electrode as a mask so that the gate electrode and the bit line are not short-circuited. The etching depth is relatively shallow, and sufficient drilling accuracy can be obtained. Further, according to the semiconductor memory devices of the third and fourth inventions and the method of manufacturing the same, sufficient drilling accuracy can be obtained because the surface near the bit line contact is relatively flat.

Therefore, even in the case of high integration, a bit line can be easily formed with high reliability and in a given small section.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIGS. 1 (a) and 1 (b) are plan views showing a DRAM having a multilayer capacitor cell structure according to a first embodiment of the present invention, and FIGS.
It is A 'sectional drawing.

An element isolation oxide film 2 is formed on a P-type silicon substrate 1 by, for example, a selective oxidation method. Further, a gate oxide film 3 having a thickness of about 150 A is formed by thermal oxidation, and gate electrodes 4 ₁ and 4 are formed by depositing and patterning a polycrystalline silicon film.
₂ are formed. The source of arsenic is ion-implanted, n-type layer 5 ₁ a drain region, 5 ₂ are formed as an impurity. Thus, a MOS transistor of the memory cell is obtained. The gate electrode 4 ₁ constitute a arranged in one direction of the memory cell array word line. Further, a first interlayer insulating film 6 is formed so as to cover the gate electrode 4. On the drain region 5 _1, the contact hole 8 for making contact with the lower capacitor electrode 7 made of polycrystalline silicon film is provided. The lower capacitor electrode 7, a source or drain region 5 ₁ to a predetermined position on the gate electrode 4 is formed on the surface of the first layer insulating film 6. Further, a dielectric film 9 is formed over the lower capacitor electrode 7 and over the first interlayer insulating film 6. Upper capacitor electrode 10 made of polycrystalline silicon film
On the dielectric film 9, the lower capacitor electrode 7
And the bit line contact hole 11 is formed.
It is provided up to the position where it contacts. Further, the second interlayer insulating film 12 is formed on the upper capacitor electrode 10 so that the upper capacitor electrode 10 is exposed. The exposed upper capacitor electrode 10 is oxidized to form the third insulating film 13 up to the portion shown by the dotted line. Furthermore, on the drain or source regions 5 _2, self-aligned manner the bit line contact hole 12 is provided for the upper capacitor electrode 10,
A bit line 14 is formed.

In the semiconductor memory device having the above-described structure, the bit line contact hole 11 is formed in a self-aligned manner with respect to the upper capacitor electrode 10 provided so as to cover the gate electrode 4. It is possible to prevent 14 shorts.

FIG. 2 is a structural process diagram of the DRAM having the multilayer capacitor structure shown in the first embodiment of the present invention.

An element isolation oxide film 2 is formed on a P-type silicon substrate 1 by, for example, a selective oxidation method. Next, 150A thickness by thermal oxidation
The gate electrodes 4 ₁ and 4 ₂ are formed by depositing and patterning a gate oxide film 3 of about the same degree and depositing and patterning a polycrystalline silicon film. The addition ion implantation of arsenic as an impurity source, n-type layer 5 ₁ a drain region, 5 ₂ forms a. Thereby, a MOS transistor of a memory cell is obtained. Then, for example, a first interlayer insulating film 6 is deposited on the entire surface, further source or contact holes for the lower capacitor electrode 7 contacts on the drain region 5 ₁ 8 made of CVD-SiO ₂ film
Are opened by an etching method. Next, the contact hole on the source or drain region 5 _1, to a predetermined position on the gate electrode 4, the lower capacitor electrode 7 is deposited a polycrystalline silicon added with phosphorus or the like in the first interlayer insulating film 6 surface Form. Next, a dielectric film 9 is formed from the lower capacitor electrode 7 to the first interlayer insulating film 6. The dielectric film 9 may be a laminated film of SiO ₂ / Si ₃ N ₄ / SiO ₂ other than the thermal oxide film. (FIG. 2A) Next, the lower capacitor electrode 7 is formed on the dielectric film 9.
, Polycrystalline silicon doped with phosphorus or the like is deposited on the entire surface of the substrate to form an upper capacitor electrode 10. And
A bit line contact hole 11 is formed. Next, a second interlayer insulating film 12 made of a PSG film doped with phosphorus or the like is formed over the entire surface of the substrate so as to cover the upper capacitor electrode 10 and the bit line contact hole 11. (FIG. 2 (b)) Next, a first opening is formed by anisotropic etching so as to have a width wider than the bit line contact hole 11 and reach the upper capacitor electrode 10 from the second interlayer insulating film 12. . Continue upper capacitor electrode 10 is formed a second opening by anisotropic etching so as to reach the upper capacitor electrode 10 to the drain or source regions 5 ₂ as a mask. Next, the first
The upper capacitor electrode 10 exposed at the bottom of the opening is thermally oxidized at a temperature of about 850 ° C. in a water vapor atmosphere to form a third insulating film 13 up to the portion shown by the dotted line. In this case, the oxidation of the upper capacitor electrode 10 having a high impurity concentration proceeds easily,
thick oxide film from the oxide film 14 formed on the drain or source regions 5 ₂ on an n-type layer is formed. (FIG. 2 (c)) Next, remove the oxide film of the drain or source regions 5 on ₂ by etching. Further, a bit line material, from the second interlayer insulating film 12 to the first opening and the second opening,
For example, Al or polycide (MoSi / polySi) is deposited and processed to form the bit line 14. In the production method (FIG. 2 (d)) or more such semiconductor memory device, a self-aligned manner the bit line contact hole gate electrode 4 ₁ and the bit line 14 to the upper capacitor electrode 10 so as not to short-circuit a mask Since 11 is formed, the etching depth is shallower than in the past, and sufficient drilling accuracy can be obtained. Therefore, the bit lines 14 can be reliably and easily provided in a given small section.
Can be formed.

FIG. 3 is a sectional view of a DRAM having a multilayer capacitor structure according to a second embodiment of the present invention.

As in the first embodiment, a MOS transistor, a first interlayer insulating film 6, a lower capacitor electrode 7, a dielectric film 9, and an upper capacitor electrode 10 are formed. Further, a second interlayer insulating film 12 is provided on the upper capacitor electrode 10 to a position where the second interlayer insulating film 12 contacts the bit line contact hole 11. The portion of the upper capacitor electrode 10 that is in contact with the bit line contact hole 11 is oxidized to form the insulating line film 13 up to the portion shown by the dotted line.

In the semiconductor memory device having the above structure, since the upper capacitor electrode 10 is provided up to the position in contact with the bit line contact hole 11, the semiconductor memory device has a flat structure as compared with the conventional one, and sufficient drilling accuracy is achieved. can get.

FIG. 4 is a manufacturing process diagram of a DRAM having a multilayer capacitor cell structure according to a second embodiment of the present invention.

As shown in FIG. 2 (a), a MOS transistor, CVD-Si
After forming a first interlayer insulating film 6 made of an O ₂ film, a lower capacitor electrode 7 made of polycrystalline silicon doped with phosphorus and the like, and a dielectric film 9, a polycrystalline silicon doped with phosphorus etc. over the entire surface of the dielectric film 9 is formed. Deposit crystalline silicon, upper capacitor electrode
Then, a second interlayer insulating film 12 made of a PSG film to which phosphorus or the like is added is provided thereon. The dielectric film 9 may have a SiO ₂ / Si ₃ N ₄ / SiO ₂ structure other than the thermal oxide film. (FIG. 4 (a)) Next, using photolithography, the drain through the upper capacitor electrode 10 from the second interlayer insulating film 12 or forming a such openings reaching the source regions 5 _2, bit The line contact hole 11 is used. Next, the portion of the upper capacitor electrode 10 exposed to the bit line contact hole 11 is thermally oxidized at a temperature of about 850 ° C. in a steam atmosphere. At this time, the drain or source regions 5 ₂ above are partially oxidized. (FIG. 4 (b)) Next, oxide film is removed which is formed on the drain or source regions 5 ₂ by etching, consisting more Al or polycide to this bit line contact hole 11 (MoSi / poly-Si) bit A line material is deposited to form bit lines 14. (FIG. 4 (c)) In the method of manufacturing the semiconductor memory device having the above-described structure, the upper capacitor electrode 10 is formed on the entire surface. Unlike the case where the second interlayer insulating film 12 is provided between the semiconductor memory device and the semiconductor device, the semiconductor memory device can be flattened.
Therefore, it is possible to provide a memory cell to reliably cubicle than conventional to provide a sufficient accuracy when drilling from the second interlayer insulating film 12 to the source regions 5 _2.

[Effects of the Invention] As described above, according to the semiconductor memory device of the present invention,
Even when high integration is performed, a short circuit between the bit line and the gate electrode can be prevented, so that the bit line can be formed reliably and in a given small section.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention, FIG. 2 is a sectional view showing steps of the first embodiment of the present invention, and FIG. 3 is a sectional view showing a second embodiment of the present invention. FIG. 4 is a sectional view showing a process of the second embodiment of the present invention, and FIG. 5 is a sectional view showing a conventional example. In the figure, 1 ... P-type silicon substrate, 2 ... Element isolation oxide film, 3 ...
... gate oxide film, 4 ... gate electrode, 5 ₁ ... source or drain region, 5 ₂ ... source or drain region, 6 ...
1st interlayer insulating film, 7 ... lower capacitor electrode, 8 ...
Contact hole, 9: dielectric film, 10: upper capacitor electrode, 11: bit line contact hole, 12: second interlayer insulating film, 13: third insulating film, 14: bit line, twenty one……
P-type silicon substrate, 22 ₁ ... drain or source region, 2
2 ₂ ... source or drain region, 23 ... element isolation oxide film, 24 ... gate oxide film, 25 ... gate electrode, 26 ... first interlayer insulating film, 27 ... lower capacitor electrode, 28 ... Dielectric film, 29 upper capacitor electrode, 30 second interlayer insulating film, 31 bit line contact hole, 32 bit line.

Continuing on the front page (72) Kagezawa Kurosawa, Inventor 1 Toshiba, Komukai Toshiba-cho, Saitama-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Shizuo Sawada 1 Toshiba-cho, Komukai Toshiba-cho, Saiyuki-ku, Kawasaki, Kanagawa, Japan (56) References JP-A-61-723181 (JP, A) JP-A-63-253661 (JP, A) JP-A-63-278368 (JP, A)

Claims (4)

(57) [Claims] A MOS transistor formed on a semiconductor substrate; a first interlayer insulating film provided on the semiconductor substrate on which the MOS transistor is formed; and a first interlayer insulating film provided on the first interlayer insulating film. A lower capacitor electrode formed in contact with the source or drain region of the MOS transistor through the first opening and extending over the gate region; a dielectric film formed on the surface of the lower capacitor electrode; An upper capacitor electrode provided to cover the lower capacitor electrode with the dielectric film interposed therebetween, a second interlayer insulating film provided on the upper capacitor electrode, and an upper capacitor formed from the second interlayer insulating film. A second opening provided to a depth of the electrode; and a drain or source region of the MOS transistor from the upper capacitor electrode in the second opening. A third opening having a smaller opening width than the second opening, and an insulating layer formed in a portion of the upper capacitor electrode located in the second and third openings. And a bit line provided in contact with the drain or source region through a contact hole formed by the second and third openings. 2. A step of forming a MOS transistor on a semiconductor substrate; a step of providing a first interlayer insulating film on the semiconductor substrate on which the MOS transistor is formed;
Through the first opening provided in the interlayer insulating film of
Forming a lower capacitor electrode extending over the gate region while contacting the source or drain region of the S transistor; forming a dielectric film on the surface of the lower capacitor electrode; Forming an upper capacitor electrode covering the lower capacitor electrode and forming an opening in the upper capacitor electrode in advance corresponding to the bit line contact hole, and forming a second interlayer insulating film on the upper capacitor electrode Forming an opening larger than the opening formed in the upper capacitor electrode in the second interlayer insulating film so as to reach the upper capacitor electrode; and forming the MOS transistor using the opening formed in the upper capacitor electrode as a mask. Etching the first interlayer insulating film to reach the drain or source region of Converting the exposed portion of the upper capacitor electrode into an insulating film; and forming a bit line by contacting the drain or source region through the contact hole including the second and third openings. And a method of manufacturing a semiconductor memory device. 3. A MOS transistor formed on a semiconductor substrate, a first interlayer insulating film provided on the semiconductor substrate on which the MOS transistor is formed, and a MOS transistor provided on the first interlayer insulating film. A lower capacitor electrode formed in contact with the source or drain region of the MOS transistor through the first opening and extending over the gate region; a dielectric film formed on the surface of the lower capacitor electrode; An upper capacitor electrode provided over the lower capacitor electrode with the dielectric film interposed therebetween, a second interlayer insulating film provided on the upper capacitor electrode,
A second opening provided so as to penetrate the upper capacitor electrode from the interlayer insulating film to reach the drain or source region of the MOS transistor; and a second opening of the upper capacitor electrode exposed in the second opening. And a bit line provided in contact with the drain or source region through a contact hole formed by the second opening. . 4. A step of forming a MOS transistor on a semiconductor substrate; a step of providing a first interlayer insulating film on the semiconductor substrate on which the MOS transistor is formed;
Through the first opening provided in the interlayer insulating film of
A step of forming a lower capacitor electrode by contacting a source of the S transistor with the drain region and extending over the gate region; a step of forming a dielectric film on the surface of the lower capacitor electrode; Forming an upper capacitor electrode covering the lower capacitor electrode;
Forming a second interlayer insulating film on the upper capacitor electrode; and forming a second opening from the second interlayer insulating film through the upper capacitor electrode to reach the drain or source region of the MOS transistor. Forming an insulating layer on a portion of the upper capacitor electrode exposed in the second opening;
Forming a bit line by contacting said drain or source region through a contact hole formed by said opening.