JPH1022471A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a capacitor of a three-dimensional structure with high reliability and high density, such as, a DRAM (dynamic random access memory) cell. SOLUTION: Trench capacitors 3, 4 are provided in a substrate, and a thin- film silicon layer 8 is formed on an insulating film 5 on the upper part of the trench capacitors by bonding and film thinning steps. A switch transistor is provided in the thin-film silicon layer, and a conductor 6 for connecting a high- concentration impurity region 12 of a source or drain of the trench capacitor with a storage electrode 4 of the switch transistor is provided in the insulating film 5. Thus, in the case where a DRAM cell is constituted, since a capacitor having a large occupied area and a large storage capacitance may be easily formed on a memory cell, an inexpensive, high-density semiconductor memory device may be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit having a charge storage capacitor such as a dynamic random access memory (hereinafter abbreviated as DRAM). The present invention relates to a circuit device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a DRAM, a switch transistor for writing and reading is connected to a charge storage capacitor for storing information, and the number of constituent elements of a memory cell is small. It is widely and generally used as an apparatus.

In order to increase the storage capacity of the DRAM, it is necessary to reduce the area of the memory cell and improve the integration of the memory cell. However, the effective area of the charge storage capacitor of the memory cell is reduced due to the miniaturization of the memory cell area, and the storage capacity is reduced, so that the S / N ratio is reduced and the information of the memory cell caused by α-ray irradiation is inverted. This causes a so-called soft error phenomenon, which becomes a serious problem in reliability. For this purpose, several memory cell structures that can provide a large storage capacity without increasing the area occupied by the memory cells have been devised so far. One of them is a capacitor formed in a trench formed deep inside the substrate. There is a memory cell having a three-dimensional capacitor using a vertical surface as a capacitor electrode (hereinafter abbreviated as a trench capacitor type memory cell).

A conventional trench capacitor type memory cell will be described with reference to FIG. Note that this type of memory cell is provided by the IE International Electron Devices Meeting Technical Digest (IEEE Int., Electron Devices Meetin).
g, Technical Digest), pp. 627-63, Dec. (1993). FIG. 20 is a sectional view of a conventional trench capacitor type memory cell. In the figure, a switching transistor in a memory cell is an insulated gate field effect transistor (MISF) formed in a p-type well 102 on an n-type impurity region 101 formed in a silicon substrate.
ET), and is insulated from adjacent transistors by a shallow trench isolation 106.
The gate electrode 108 is connected to a word line of the memory. The metal wiring 115 is a data line of the memory, and is connected to the high concentration n-type impurity region 111 of the source or drain of the switching transistor via a contact hole. Further, the charge storage capacitor is formed in a trench provided in the silicon substrate, and the high-concentration n-type impurity region 112 of the source or drain of the switching transistor is connected to the self-aligned contact 11.
In 3, it is connected by self-alignment to polycrystalline silicon to which the n-type impurity which becomes the storage electrode 105 of the storage capacitor is added at a high concentration. Further, the n-type impurity region 101 in the silicon substrate serves as a common plate electrode of the capacitor, and the capacitor insulating film 103 is provided between the n-type impurity region 101 and the polysilicon of the storage electrode 105. Generally, in the case of DRAM, a back bias is applied to the transistors in the memory array to solve the effect of noise from the input / output circuit of the memory, but the voltage applied to the capacitor insulating film of the trench capacitor increases due to the back bias. I do. Therefore, the memory cell array is electrically separated from the p-type silicon substrate (not shown) by the n-type impurity region 101 as shown in FIG. Further, a thick insulating film 104 is provided on the side wall of the trench capacitor in the p-type well 102. In this type of trench capacitor, a desired storage capacity can be obtained by increasing the depth of the trench in the n-type impurity region 101. As a result, even in a fine memory cell, operation of the memory cell and reliability can be ensured. Sufficient storage capacity can be ensured, thereby realizing a large-capacity DRAM of 1 gigabit class. Further, the trench capacitor does not affect the unevenness of the insulating film forming the metal wiring even if a large storage capacitance is formed as compared with a stacked capacitance type memory cell in which the capacitor is formed above the main surface of the silicon substrate. That is the feature.

[0005]

However, in the above-mentioned conventional trench capacitor type memory cell, although not described in detail here, a polycrystalline electrode 105 (hereinafter, the electrode on the source or drain side of the transistor is referred to as a storage electrode) is used. In order to connect the silicon and the high-concentration impurity region 112 in a self-aligned manner, a complicated manufacturing process such as the self-aligned contact 113 is required. In addition, the leakage current caused by the vertical parasitic channel formed between the high-concentration n-type impurity region 112 of the self-aligned contact and the n-type impurity region 101 of the silicon substrate inverts the memory information. In order to cause a retention failure such as the above, it is necessary to provide a thick insulating film 104 on the side wall of the trench capacitor in the p-type well 102, which complicates the manufacturing process. Further, since the plate electrode of the capacitor becomes the n-type impurity region 101 below the p-type well 102, it is necessary to further increase the depth of the trench in order to obtain a necessary storage capacity. Furthermore, if the self-aligned contact 113 is provided close to the channel portion of the switching transistor, punch-through of the MISFET will be caused. Therefore, a certain distance must be provided, and the area occupied by the capacitor cannot be increased.

Accordingly, a first object of the present invention is to provide a semiconductor integrated circuit device capable of further increasing the storage capacitance value of a trench capacitor while maintaining a high degree of integration, and a method of manufacturing the same. A second object of the present invention is to realize a semiconductor integrated circuit device having a trench capacitor in which a storage electrode is connected to a source or a drain of a transistor with high accuracy, a large storage capacitance value of a trench capacity, and a simple manufacturing process. An object of the present invention is to provide a semiconductor integrated circuit device and a method for manufacturing the same. A third object of the present invention is to provide a DRAM type semiconductor memory device having a high integration density and high reliability, and a method of manufacturing the same.

[0007]

In order to achieve the above object, in a semiconductor integrated circuit device according to the present invention, a three-dimensional capacitor (hereinafter, referred to as a trench capacitor) formed in a trench inside a main surface of a substrate on which a transistor is formed. Call it)
A semiconductor integrated circuit device having a conductor in which a storage electrode of the trench capacitor is connected to a source or a drain of the transistor;
Provided on a thin silicon layer (SOI layer) on the insulating film of
An opening smaller than a plane area of the trench capacitor is provided in the first insulating film, and a conductor of the connection portion is formed in the opening. The trench shape means that the storage electrode is three-dimensional, and the planar area of the trench capacitor means a cross-sectional area of the three-dimensional shape in a substrate plane direction. One preferred embodiment of the semiconductor integrated circuit device of the present invention is a case where the semiconductor integrated circuit device is a DRAM, the transistor is a switching transistor, and forms a memory cell together with the capacitor.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the method for manufacturing the semiconductor integrated circuit device according to the present invention includes:
Forming the trench capacitor in the first semiconductor substrate, forming an insulating film on the first semiconductor substrate on which the trench capacitor is formed, and forming a conductor of the connection portion in the insulating film. Forming and laminating the second semiconductor substrate to the first semiconductor substrate, and forming the thin film layer by thinning the second semiconductor substrate.

In the semiconductor integrated circuit device according to the present invention, the conductor provided in the opening is provided in the silicon substrate with a source or a drain of a switching transistor provided in the thin film layer formed by bonding. The storage electrode of the trench capacitor is electrically connected,
Since the trench capacitor and the switching transistor are electrically insulated and separated from each other in the portion other than the conductor portion, the area occupied by the trench capacitor should be increased irrespective of the switching transistor formed above the trench capacitor. And the effective area of the capacitor can be increased. Further, according to the present invention, since it is not necessary to form the n-type impurity region 101 in the silicon substrate as in the conventional example, the entire inner surface of the formed trench effectively functions as a charge storage capacitor. In addition, a complicated manufacturing process required for connecting the trench capacitor and the switching transistor as in the conventional example is unnecessary, and the n-type impurity region 101 and the thick insulating film 1 having the side wall of the trench capacitor are unnecessary.
Also, the manufacturing process can be simplified because the step 04 is not required.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail using embodiments. <Embodiment 1> FIGS. 1 and 2 are a partial sectional view and a partial plan view, respectively, showing the structure of a DRAM which is an embodiment of a semiconductor integrated circuit device according to the present invention.

The partial cross section of FIG. 1 is X in the plan view of FIG.
It is sectional drawing of the -X 'line part. DRAM as shown in FIG.
The word line 19 is provided in the Y direction, the data line 20 is provided in the X direction, the storage electrode (first electrode) 4 of the trench capacitor is a rectangular plane, and at least two Is formed below the word line 19 so that the longitudinal direction of the rectangular plane is the horizontal direction of the drawing when the trench capacitor is viewed from above.

Further, the storage electrode 4 of the capacitor is a conductor 6 buried in an opening formed in the insulating film 5 (FIG. 1) in the gap between the word lines 19 and has a high source (or drain) of the switching transistor. It is connected to the concentration n-type impurity region 12. The high-concentration p-type impurity region 2 formed in the p-type silicon substrate 1 serves as a common plate electrode (second two electrodes) of the charge storage capacitor, and is fixed at a predetermined potential. Further, the data line 20 is formed of the metal wiring 16 and has a high concentration n of the source (or drain) of the switching transistor through the contact hole.
It is connected to the type impurity region 11. Between the high-concentration p-type impurity region 2 serving as a plate electrode and the storage electrode 4, a capacitor insulating film 3 forming the capacitor is formed. A transistor including a thin silicon layer 7, a gate insulating film 9, a gate electrode 10, a high concentration source (or drain) n-type impurity region 11, and silicon oxide films 13 and 14 is formed on the insulating film 5. Reference numeral 8 denotes a silicon oxide film for element isolation. Reference numeral 15 denotes a silicon oxide film as an interlayer insulating film.

FIGS. 3 to 10 are cross-sectional views for explaining a manufacturing process of one embodiment of the semiconductor integrated circuit device according to the present invention. First, boron ions are implanted into the p-type silicon substrate 1 using a photoresist as a mask, and a predetermined annealing is performed to obtain a high concentration p of about 5 μm.
Form impurity region 2 is formed. The conditions for the ion implantation are as follows: an acceleration voltage of about 50 KeV, 1 × 10 ¹⁶ (1 / cm 2)
² ) An appropriate dose is appropriate. In addition to the ion implantation, a high concentration layer can be formed by diffusing phosphorus in a gas phase. Here, the illustration of the peripheral circuit portion other than the memory cells is omitted (FIG. 3).

Next, a trench 22 having a depth of 4 μm is formed in the high-concentration impurity region 2 by using known photolithography and anisotropic dry etching, and a capacitor insulating film 3 is deposited. Here, the required area of the trench is preferably large. As the capacitor insulating film 3, a composite film of a silicon oxide film and a silicon nitride film having an effective film thickness of about 4.5 nm is preferable, but tantalum pentoxide (Ta ₂ O ₅ ) or B
A dielectric film having a high relative dielectric constant, such as aTiO ₃ or SrTiO ₃ , or a ferroelectric film, such as a PZT film, can be used, whereby the effective film thickness can be further reduced. As a deposition method, it is preferable to use a known low pressure chemical vapor deposition method (hereinafter abbreviated as LPCVD) so as to be uniformly formed in the deep trench 22. Further, these dielectric films are preferably made of a material that can withstand a heat process in the subsequent bonding process (FIG. 4).

Next, a polycrystalline silicon film having a thickness of about 500 nm to which an n-type impurity is added at a high concentration is deposited by the LPCVD method, and n-type polycrystalline silicon is formed in the trench 22 formed by the known etch back. To form a storage electrode 4. At this time, the portion of the capacitor insulating film 3 other than the trench may be etched by over-etching. Preferably, the polycrystalline silicon film is doped polysilicon in which phosphorus is added during the deposition of the film. In this case, the impurity concentration is 1 × 10 ²¹ (1
/ Cm ³ ) is appropriate. Then, a thickness of 300 nm
Of silicon oxide film 5 is deposited by the LPCV method. Although the silicon oxide film 5 is used here, other types of insulating films can be used. Further, a material that generates fluidity by annealing, such as a so-called BPSG film to which boron and phosphorus are added, is preferable (FIG. 5).

Next, the storage electrode 4 is formed on a predetermined portion of the silicon oxide film 5 by photolithography and dry etching.
Is formed, and a polycrystalline silicon film having a thickness of about 300 nm to which an n-type impurity is added at a high concentration is formed by LPCV.
A conductor 6 is formed by embedding n-type polycrystalline silicon in an opening formed by a known etch-back method. Here, the required area of the opening is desirably small. It is preferable that the polycrystalline silicon film be doped polysilicon in which phosphorus is added during the deposition of the film. In this case, the impurity concentration is 1 × 10 ²¹ (1 / cm 2)
³ ) The degree is appropriate (Fig. 6).

Next, a separately prepared silicon substrate 23 is bonded to the surface of the silicon substrate 1 in which the above-described trench is formed, and is subjected to a predetermined high-temperature treatment.
Is chemically bonded to the surface of the silicon substrate 1 (FIG. 7).

Next, the entire surface of the silicon substrate 23 is etched using a known method to form a thin-film silicon layer 7 (thin-film SOI layer) having a thickness of about 50 nm, and an element is formed on the thin-film silicon layer 7 using a known method. Silicon oxide film 8 for separation
Is formed so as to reach the silicon oxide film 5. In photolithography for forming a silicon oxide film 5 for element isolation, a photomask (reticle) of an element isolation pattern was formed by a conductor 6 and a storage electrode 4 when positioning with respect to a lower layer pattern. It is preferable to perform alignment using the mark (FIG. 8).

Next, sacrificial oxidation of the active region is performed by a known method, and then gate oxidation is performed in an oxygen atmosphere at about 800.degree. The gate oxide film thickness is, for example, 4.5 nm.
It is. Next, a polycrystalline silicon film having a thickness of about 100 nm to which an n-type impurity is added at a high concentration and a thickness of about 50 nm are formed.
Is continuously deposited, and the gate electrode 10 is patterned by photolithography and dry etching. Next, the silicon oxide film by LPCVD is etched back to form sidewall spacers 14 on the side walls of the gate electrode 10, and the source and drain heights are increased by ion implantation of arsenic using the silicon oxide film 13 and the sidewall spacers 14 as a mask. The n-type impurity regions 11 and 12 are formed. The ion-implanted impurity region is diffused to the lower portion of the thin-film silicon layer 7 and the position of the gate electrode by a subsequent thermal process. In addition,
In this embodiment, the MISFET has a single drain structure, but a known LDD (Lightly Doped) is used.
It goes without saying that a Drain structure can be used. Further, the resistance of the word line can be reduced by using a well-known composite film of a silicide of a refractory metal such as tungsten and a polycrystalline silicon film or a refractory metal such as tungsten (FIG. 9). . Finally, a silicon oxide film 15 having a thickness of about 400 nm is deposited as an interlayer insulating film, and a contact hole is formed in the interlayer insulating film 15 on the high concentration impurity region 11.
Is formed to complete the semiconductor memory device shown in FIG. 1 (FIG. 10). The metal wiring 16 is preferably made of a low resistance metal such as aluminum, but may be made of a high melting point metal such as tungsten.

As described above, according to the present embodiment, there is no problem even when the mask alignment shift occurs and the element isolation pattern is applied to the conductor 6, so that the high concentration n-type impurity region of the source or drain of the MISFET is not generated. 12 can be reduced as much as possible. As a result, the capacity of the data line can be reduced, the power consumption when charging and discharging the data line can be reduced, and the power consumption of the semiconductor memory device can be reduced. .

<Embodiment 2> FIG. 11 is a partial sectional view showing a structure of a DRAM which is another embodiment of the semiconductor integrated circuit device according to the present invention. In FIG. 1, a silicon oxide film 5 is provided above a trench capacity field (provided in a substrate 1).
Is provided, and a thin-film silicon layer 25 having a relatively large thickness is provided thereon. Therefore, the silicon oxide film 8 for element isolation formed in the thin-film silicon layer 25 and the n-type high-concentration impurity regions 11 and 12 serving as the source and drain of the MISFET do not reach the lower part of the thin-film silicon layer 25. Further, the thin silicon layer 25 and the silicon oxide film 5 are provided with a common conductor 24 having a smaller area than the above-mentioned trench capacitor, and the high-concentration impurity region 12 of the source / drain region and the storage electrode 4 of the trench capacitor are formed. Electrically connected.

FIGS. 12 to 19 are sectional views for explaining the manufacturing steps of another embodiment of the semiconductor integrated circuit device according to the present invention shown in FIG. High concentration p on silicon substrate 1
The manufacturing steps from forming the mold impurity region 2, forming the trench 22 and the capacitor insulating film 3, and depositing the silicon oxide film 5 are the same as those in FIGS. 3 to 5 of the first embodiment (FIGS. 12 and 13). , 14).

Then, a separately prepared silicon substrate 27 is adhered to the surface of the silicon substrate 1 having the trenches formed thereon, and subjected to a predetermined high-temperature treatment to thereby form the silicon substrate 27.
Is chemically bonded to the surface of the silicon substrate 1 (FIG. 15).
Next, using a known method, the entire surface of the silicon substrate 27 is etched to form a thin film silicon layer 25 (thin film SOI layer) having a thickness of, for example, about 300 nm, and an element is formed on the surface of the thin film silicon layer 25 using a known method. A silicon oxide film 8 for isolation is formed (FIG. 16).

Next, an opening reaching the storage electrode 4 is formed at a predetermined position of the thin silicon layer 25 and the silicon oxide film 5 by using known photolithography and dry etching, and an n-type impurity having a thickness of about 300 nm is formed. A polycrystalline silicon film doped at a high concentration is deposited by an LPCVD method, and n-type polycrystalline silicon is buried in the opening formed by the known etch back, and a conductor 24 (silicon plug)
To form Here, the required area of the opening is desirably small. It is preferable that the polycrystalline silicon film be doped polysilicon in which phosphorus is added during the deposition of the film. In this case, the impurity concentration is 1 × 10 ²¹ (1 /
cm ³ ) is appropriate. At this time, the conductor 24
Although phosphorus diffuses from the side wall of the thin film silicon layer 25 into the thin film silicon layer 25, it is not shown in the figure (FIG. 17).

The conductor 24 and the thin film silicon layer 25 may be electrically insulated, and a silicon oxide film (not shown) having a thickness of about 50 nm is previously formed on the side wall of the opening using a known method. It can also be formed. In this case, it is desirable to form the silicon oxide film 8 for element isolation after forming the conductor 24. Further, before and after the formation of the silicon oxide film 8 for element isolation, the silicon oxide film (not shown) on the side wall of the opening is removed by etching only the upper portion, so that the source or drain formed in the subsequent steps is removed. Of the high concentration n-type impurity region 12 and the conductor 24 are connected. Next, as described with reference to FIG. 9 of the first embodiment, the gate electrode 10 of the MISFET and the high-concentration impurity regions 11 and 12 of the source / drain regions are formed on the thin film silicon layer 25. As a result, the high concentration n-type impurity region 12 and the storage electrode 4 of the trench capacitor are connected by the conductor 24 (FIG. 18). Thereafter, the manufacturing steps up to the final step in FIG. 19 are the same as those in FIG. 10 in the first embodiment.

According to the present embodiment, the thickness of the thin silicon layer 25 used as the SOI substrate is determined by the thickness of the silicon oxide film 8 for element isolation and the n-type high-concentration impurity regions 11 and 12 of the source or drain of the MISFET. Since the substrate is thicker than the depth, the potential of the substrate can be easily fixed and the SOI
The problem of the inherent substrate floating can be solved.

[0027]

As described above, according to the present invention, a trench-type capacitor having a large occupied area can be formed inside a substrate, and a conventional MISFET can be connected to a trench capacitor. It is possible to provide a highly reliable, low-cost, highly-integrated semiconductor integrated circuit device which does not require a complicated self-alignment process and has high soft error resistance.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 20 is a sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

1 ... p-type silicon substrate, 2 ... high-concentration p-type impurity region,
3, 103: capacitor insulating film, 4, 105: storage electrode, 6, 24: conductor, 7, 25: thin-film silicon layer,
5, 8, 13, 14, 15, 109, 110, 114 ...
Silicon oxide film, 9, 107 ... gate insulating film, 10, 1
08 ... gate electrode, 11, 12, 111, 112 ... high concentration n-type impurity region, 16, 115 ... metal wiring, 18 ... active region, 19 ... word line, 20 ... data line, 21 ... contact hole, 22 ... trench , 23, 27: silicon substrate, 101: n-type impurity region, 102: p-type well,
104: insulating film; 106: shallow trench isolation; 113: self-aligned contact.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ken Sakata 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Tomoki Sekiguchi 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (12)

[Claims] 1. A semiconductor integrated circuit having a three-dimensional trench capacitor formed inside a main surface of a substrate on which a transistor is formed, wherein a storage electrode of the trench capacitor has a connection portion connected to a source or a drain of the transistor. In the circuit device, the transistor is provided in a thin-film silicon layer (SOI layer) over a first insulating film, an opening is provided in the first insulating film, and the conductor of the connection portion is formed in the opening. A semiconductor integrated circuit device characterized by being performed. 2. The semiconductor device according to claim 1, wherein the opening is smaller than a plane area of the storage electrode of the trench capacitor.
13. The semiconductor integrated circuit device according to claim 1. 3. A plurality of memory cells each having a switching transistor and a storage capacitor connected to a source or a drain of the switching transistor, wherein the storage capacitor is located inside a main surface of a substrate on which the transistor is formed. In a semiconductor memory device which is a formed three-dimensional capacitor, the transistor is provided on a thin film silicon layer on a first insulating film formed on an upper surface of the capacitor, and a first electrode of the capacitor is provided on the first electrode. A semiconductor integrated memory device electrically connected to a source or a drain of the transistor by a conductor provided in the insulating film. 4. The semiconductor memory device according to claim 3, wherein a cross-sectional area of said conductor in a direction parallel to said main surface of said substrate is smaller than a plane area of said first electrode of said capacitor. 5. The semiconductor memory device according to claim 3, wherein a second insulating film for insulating and separating the periphery of said transistor is provided on a part of said first electrode. 6. The capacitor according to claim 3, wherein at least two word lines are provided above the capacitor.
13. The semiconductor memory device according to claim 1. 7. The capacitor according to claim 3, wherein a plane of the capacitor on the surface of the silicon substrate is substantially rectangular, and a long side direction of the rectangle is parallel to the data line.
13. The semiconductor device according to claim 1. 8. The semiconductor memory device according to claim 3, wherein said memory cells are memory cells of a dynamic random access memory. 9. A step of forming a three-dimensional capacitor in a first silicon substrate, a step of forming an insulating film on the first silicon substrate on which the capacitor is formed, and a step of forming the capacitor in the insulating film. Forming a conductor to be connected to the first electrode, and bonding a second silicon substrate to the first silicon substrate to form a thin-film silicon layer for thinning the second silicon substrate. A method for manufacturing an integrated circuit device. 10. The method according to claim 1, further comprising, after the step of thinning the second silicon substrate, a step of forming a transistor on the second silicon substrate, the transistor being connected to the conductor or the source or the drain. Item 10. The method for manufacturing a semiconductor integrated circuit device according to item 9. 11. A method for manufacturing a semiconductor integrated circuit device according to claim 9, further comprising the step of using a mark pattern formed of said first electrode or said conductor as a positioning mark for photolithography. A method for manufacturing a semiconductor integrated circuit device. 12. A method of manufacturing a semiconductor integrated memory device, wherein said transistor is a transistor for switching a memory cell, and said three-dimensional capacitor is a storage capacitor of said memory cell.