JPS63281457A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS63281457A
JPS63281457A JP62114630A JP11463087A JPS63281457A JP S63281457 A JPS63281457 A JP S63281457A JP 62114630 A JP62114630 A JP 62114630A JP 11463087 A JP11463087 A JP 11463087A JP S63281457 A JPS63281457 A JP S63281457A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
shaped
contact hole
contact
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62114630A
Inventor
Yoshio Sakai
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62114630A priority Critical patent/JPS63281457A/en
Publication of JPS63281457A publication Critical patent/JPS63281457A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor

Abstract

PURPOSE:To shorten a distance between a contact hole for a transistor and a gate electrode, and to reduce the area of a memory cell and improve the degree of integration by forming the contact hole for a memory-cell bit line onto flattened polycrystalline silicon shaped so as to be superposed on the gate electrode. CONSTITUTION:First layer polycrystalline silicon formed onto a p-type silicon substrate 1 through thin gate insulating films 12 or gate electrodes 3 as word lines for a memory cell are coated with insulating films 14 consisting of SiO2, etc., shaped in a self alignment manner. Polycrystalline silicon 6 is shaped to a storage capacitance section and polycrystalline silicon 8 as upper electrodes onto the polycrystalline silicon 6, and a contact hole on flattened polycrystalline silicon 61 is formed extending over the upper sections of the gate electrodes 3 in the contact section of a bit line. A MOS transistor has low-concentration drain structure, and source.drain regions 4, 5 being in contact with polycrystalline silicon 6, 61 are shaped in high-concentration n-type regions. Margins among the contact hole and the word lines 3 can be brought to zero.
JP62114630A 1987-05-13 1987-05-13 Semiconductor memory Pending JPS63281457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62114630A JPS63281457A (en) 1987-05-13 1987-05-13 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62114630A JPS63281457A (en) 1987-05-13 1987-05-13 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS63281457A true JPS63281457A (en) 1988-11-17

Family

ID=14642649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62114630A Pending JPS63281457A (en) 1987-05-13 1987-05-13 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS63281457A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0439965A2 (en) * 1989-12-29 1991-08-07 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor memory
US5068200A (en) * 1989-06-13 1991-11-26 Samsung Electronics Co., Ltd. Method of manufacturing DRAM cell
US5111275A (en) * 1987-12-22 1992-05-05 Kabushiki Kaisha Toshiba Multicell semiconductor memory device
US5248628A (en) * 1989-09-08 1993-09-28 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor memory device
US5264712A (en) * 1989-03-20 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5834106A (en) * 1992-05-26 1998-11-10 Nihon Cement Co., Ltd. Ceramic substrate and producing process thereof, and a suction carrier for wafers using a ceramic wafer-chucking substrate
US5900660A (en) * 1993-02-12 1999-05-04 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5973343A (en) * 1995-04-20 1999-10-26 Nec Corporation Semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner and process of fabrication thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5111275A (en) * 1987-12-22 1992-05-05 Kabushiki Kaisha Toshiba Multicell semiconductor memory device
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5264712A (en) * 1989-03-20 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5068200A (en) * 1989-06-13 1991-11-26 Samsung Electronics Co., Ltd. Method of manufacturing DRAM cell
US5248628A (en) * 1989-09-08 1993-09-28 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor memory device
EP0439965A2 (en) * 1989-12-29 1991-08-07 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor memory
US5834106A (en) * 1992-05-26 1998-11-10 Nihon Cement Co., Ltd. Ceramic substrate and producing process thereof, and a suction carrier for wafers using a ceramic wafer-chucking substrate
US5900660A (en) * 1993-02-12 1999-05-04 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls
US6110774A (en) * 1993-02-12 2000-08-29 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5973343A (en) * 1995-04-20 1999-10-26 Nec Corporation Semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner and process of fabrication thereof
US6143600A (en) * 1995-04-20 2000-11-07 Nec Corporation Method of fabricating a semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner

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