JP2771903B2 - High breakdown voltage MOS transistor and method of manufacturing the same, and semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS transistor and a method for manufacturing the same, and a semiconductor device having the MOS transistor and a method for manufacturing the same. For details, for example, DR
High breakdown voltage MOS transistor suitable for use in AM boost section, method of manufacturing the same, and such high breakdown voltage MO
The present invention relates to a semiconductor device having an S transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a DRAM, in order to reliably write data by applying a sufficiently high voltage to a capacitor of a memory cell, a voltage applied to a word line is generally increased to a power supply voltage or more. I have. FIG. 21 shows an example of a bootstrap word line drive circuit for applying a boosted voltage to a word line. In the figure, the first and second N-type M
The OS transistors 551 and 552 are connected in series, and the drain d of the third N-type MOS transistor 553 is
₃ is connected to the gate g ₁ of the transistor 551 at node A.

A boosted voltage V ₀ from a booster circuit (not shown) is applied to the drain d _{1 of the} transistor 551 via a terminal 555, and a power source (not shown) is applied to a gate g _{3 of the} transistor 553. Voltage V _CC is applied via terminal 556. The source s ₃ of the transistor 553, the output signal of the decoder (not shown) is applied through the terminal 557. Source s ₃ and terminal 557 are connected to node B
Connected by The gate g of the transistor 552
₂ is connected to the reset signal line RL via the terminal 558. The source s ₁ of the transistor 551 and d _{2 of the} transistor 552 are connected at a node D, and the node D is connected to a word line WL via a terminal 559. Source s ₂ of the transistor 552 is grounded.

The output signal of the decoder causes the transistor 5
When 53 is selected and turned on, the potential of the source s ₃ (node B) becomes V _CC . The potential of the drain d ₃ (node A) of the transistor 553 becomes V _CC −V _th (V _th is the threshold voltage of the transistor 553). Thus, the transistor 551 is turned on, the transistor 553 is turned off, the drain d ₃ is floating. In addition,
Voltage V _r potential of the node A is boosted to the boosted voltage greater than or equal _to V ₀ by the gate capacitance coupling of the transistor 551
Therefore, the boosted voltage V ₀ at the node D is applied to the word line WL without lowering the voltage. For example, V _CC = 5
V, V ₀ = 7.5V, V _r = 14V.

[0005] Since the voltage supply voltage V _CC is boosted V _r is the drain d ₃ of the transistor 553 is applied, sufficient breakdown voltage in the diffusion layer constituting the drain d ₃ is required. When the drain d ₃ no sufficient withstand voltage to the diffusion layer constituting the potential of the node A is decreased gradually, it becomes impossible maintain the voltage to be applied to the word line WL to V _0.

As a method for preventing the potential of the node A from lowering,
Although it is conceivable to increase the thickness of the gate oxide film of the transistor 553, this is contrary to the recent trend of thinning the gate oxide film with miniaturization of semiconductor devices.

As a conventional example, for example, an LD shown in FIG.
There is a high voltage MOS transistor having a D structure. The drain d _{3 of the} transistor 553 is formed of a relatively low-concentration and wide N-type layer 553d. It is possible. Also, the drain electrode 6
Since 01 usually consists of aluminum (Al), at the portion where the drain electrode 601 such that the contact resistance does not increase to connect the drain d ₃ is the relatively high concentration of N ⁺ -type layer 553e. In FIG. 22, 602 is a field oxide film, 603 is a gate oxide film, and 604 is a BPS.
This is a G interlayer insulating film.

As a method of manufacturing the above conventional example, there are roughly first and second methods. According to the first method, the previously formed N ⁺ layer 553e To the drain electrode 60
One contact hole is formed. On the other hand, according to the second method, ions are implanted through the contact hole for the drain electrode 601 to form the N ⁺ -type layer 553e in a self-aligned manner.

[0009]

FIG. 23 is a diagram for explaining the first method. In the figure, L ₁ is a gate g ₃
The distance between the N ⁺ -type layer 553e, L ₂ is BPGS interlayer insulating film 604 and the N ⁺ -type layer 553e and the distance to overlap, L ₃ is a distance corresponding to the width of the contact hole for the source electrode 601 is there. The withstand voltage of the drain d ₃ is L ₁
Is determined. However, if the N-type layer 553d makes direct contact with the Al drain electrode 601, the contact resistance becomes too large. Therefore, it is necessary to provide the N ⁺ -type layer 553 e for contact with the drain electrode 601. to reduce the L ₃ also has limitations. If a contact hole is not formed with a margin of L _2, the drain electrode 601 is directly connected to the N-type layer 553.
since there is a possibility of d and the contact, there is a limit to reduce the L _2. Therefore, conventionally, L ₁ + L ₂ + L ₃ becomes distance partial elements in order to ensure the withstand voltage of the drain d ₃ which is determined by L ₁ will spread laterally. That is, there is a limit to the reduction of the occupied area of the high breakdown voltage MOS transistor. FIG. 24 is a diagram for explaining the second method. FIG. 11A shows a state in which an N-type layer 553s is formed and contact holes are formed in the BPSG interlayer insulating film 604 and the gate oxide film 603. FIG. 4B shows that the ion implantation is performed after the formation of the resist layer 605 to form the N ⁺ -type layer 5.
53e and a process of forming an N ⁺ -type layer 553s which forms the source s _3. At the time of this ion implantation, the resist layer 6
Due to the alignment margin of 05, impurity ions are also implanted into the portions indicated by “x” in FIG. For this reason, if pretreatment with an HF-based etchant is performed before the step of forming the Al layer forming the drain electrode 601,
Since the etching rate of the ion-implanted portion is higher than that of the other portions, a step 610 as shown in FIG. If such a step 610 is present, disconnection is likely to occur in a wiring layer or the like formed thereafter, which is not preferable.
Also, since the N ⁺ -type layer 553e is formed in a self-aligned manner as compared with the first method, there is a merit that L ₂ can be reduced. However, a high breakdown voltage MOS is required to secure L ₁ + L ₂ + L _3. There is a limit in reducing the area occupied by transistors. Further, according to the second method, the number of steps is increased as compared with the first method.

According to the present invention, there is provided a high-density device capable of reducing the occupied area and increasing the withstand voltage of the drain / source without increasing the contact resistance between the drain / source electrode and the diffusion layer constituting the drain / source. It is intended to realize a withstand voltage MOS transistor and a method of manufacturing the same, and a semiconductor device having a high withstand voltage MOS transistor and a method of manufacturing the same.

[0011]

FIG. 1 is a diagram for explaining the principle of a high voltage MOS transistor according to the present invention. In the figure,
1 is a first conductivity type semiconductor substrate, 13 is a gate oxide film, 14
And a gate electrode, 15 is a drain / source region of a second conductivity type having a relatively low impurity concentration, 16 is a source / drain region of a second conductivity type having a relatively high impurity concentration, 28 is a contact hole for a source / drain electrode, and 29 is a contact hole for a source / drain electrode. A contact hole for a drain / source electrode, 35 a source / drain electrode,
38 is a drain / source electrode, and 27 is an interlayer insulating film. The source / drain electrode 35 and the drain / source electrode 38 are made of a conductive layer 49 containing polycrystalline silicon of the second conductivity type and having an impurity concentration higher than the impurity concentration of the drain / source region 15 of the second conductivity type. The first and second conductivity types are opposite to each other.

[0012]

The drain / source of the MOS transistor comprises only the relatively low-concentration second-conductivity-type drain / source region 15, and the drain / source electrode 38 intervenes through the relatively-high-concentration second-conductivity-type region. And directly to the drain / source region 15 of the second conductivity type. Thus, L ₂ required by the conventional method becomes unnecessary, thereby enabling miniaturization of the correspondingly MOS transistor.

The drain / source electrode 38 is directly connected to the relatively low-concentration drain / source region 15 of the second conductivity type.
Since the conductive layer 49 is of a conductive type and contains polycrystalline silicon, the contact resistance does not increase. Further, since the drain / source region 15 of the second conductivity type having a relatively low concentration is thin, if the Al electrode is formed directly above, spikes of Al may occur. However, since the drain / source electrode 38 does not use Al, the problem of spikes may occur. Does not occur.

Furthermore, compared to the contact between Al and Si, the contact between polycrystalline silicon and Si can be contacted with a lower impurity concentration. Since the withstand voltage of the transistor increases as the impurity concentration decreases, the transistor of the present invention can easily increase the withstand voltage of the transistor as compared with the conventional example.

The second electrode constituting the drain / source electrode 38
When conductive layer 49 of conductive type and containing polycrystalline silicon is formed, impurities in conductive layer 49 diffuse into shallower second conductive type drain / source region 15 of relatively low concentration by solid phase diffusion to a depth smaller than its depth. I do. Thereby, the contact resistance can be reduced. Further, since the boundary between the relatively low-concentration second conductivity type drain / source region 15 and the portion where the concentration is increased by the solid-phase diffusion is loose, a structure with a higher breakdown voltage as compared with the related art is realized. You.

FIG. 2 is a diagram showing characteristics of the high breakdown voltage MOS transistor according to the present invention in comparison with a conventional example. In the figure,
The vertical axis shows the impurity concentration on a log scale, and the horizontal axis shows FIG.
The x direction at 22 and 24 is shown. Dashed lines I and II indicate the characteristics of the conventional example manufactured by the first and second methods, respectively, and dashed line III indicates the characteristics of the high breakdown voltage MOS transistor according to the present invention.

Therefore, according to the present invention, the occupied area of the multi-breakdown-voltage MOS transistor is reduced, and the drain / source is increased without increasing the contact resistance between the drain / source electrode and the diffusion region forming the drain / source. Can withstand a high voltage.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a semiconductor device according to the present invention having a first embodiment of a high breakdown voltage MOS transistor according to the present invention will be described with reference to FIG. FIG. 1A is a cross-sectional view of a semiconductor device, and FIG. 1B is a circuit diagram thereof.

On a P-type semiconductor substrate 1 of silicon or the like, a plurality of elements such as N-type MOS transistors described later are formed. The bootstrap word line drive circuit 2 for applying a voltage to the word line WL includes three MOS transistors 3 to 5 described later. The first MOS transistor 3 and the second MOS transistor 4 are connected in series,
The drain layer 15 of the third MOS transistor 5 is connected to the gate electrode 7 of the first MOS transistor 3.

The first MOS transistor 3 is a semiconductor-based
A gate electrode formed on a plate 1 via a gate oxide film 6
The electrode 7 is formed on the semiconductor substrate 1 on both sides of the gate electrode 7.
N ⁺And N^-Source layer 8 having an LDD structure
And an in-layer 9.

The second MOS transistor 4 is formed by a gate electrode 11 provided on the semiconductor substrate 1 with a gate oxide film 10 therebetween, and a source layer 12 and a drain layer 113 having an LDD structure formed on both sides thereof. ing. Since the drain layer 113 is provided integrally with the source layer 9 of the first MOS transistor 3, the first and second MOs
The S transistors 3 and 4 are connected in series.

The third MOS transistor 5 has a gate electrode 14 formed on a gate oxide film 13, an N ⁻ type conductive layer 15 is provided on one side of the substrate 1, and an LDD is formed on the other side. The structure is such that a conductive layer 16 having a structure is formed. N ^{− type} conductive layer 15 is connected to gate electrode 7 of first MOS transistor 3 by a wiring electrode (not shown).

Stacked capacitor type DRAM cell 17
The fourth MOS transistor 18 that constitutes the same as the three MOS transistors 3 to 5 described above has an insulating film 20.
Gate electrode 21 formed on semiconductor substrate 1 through
And N-type or N ⁻ -type conductive layers 22 provided on both sides thereof.
23. One conductive layer 22 is connected to the bit line BL, and the gate electrode 21 is connected to the word line WL. The capacitor 19 of the DRAM cell 17 is provided on the other conductive layer 23 through a contact hole 34 described later. The capacitor 19 includes a storage electrode 24 made of polycrystalline silicon doped with N-type impurity ions such as phosphorus (P), a dielectric film 25 made of SiO ₂ , and a counter electrode made of polycrystalline silicon containing N-type impurity ions. The electrode 26 is formed by sequentially laminating the electrodes 26, and a voltage of V _CC / 2 is applied to the counter electrode 26.

First to fourth MOS transistors 3 to 5, 1
Contact holes 28 to 33 for exposing the conductive layers 8, 9, 15, 16, etc. are formed in the interlayer insulating film 27 made of PSG or the like formed on 8. Interlayer insulating film 27
Above each of the source layers 9 and 12 and the drain layers 8 and 13
Electrodes 35 to 40 made of polycrystalline silicon in which impurities of the same polarity are diffused are formed so as to fill contact holes 28 to 33. Also, similarly to these, the fourth MOS
An electrode 41 is formed on one conductive layer 22 of the transistor 18.

Reference numeral 42 denotes a field oxide film formed around the first to third MOS transistors 3 to 5 and the periphery of the DRAM 17 by a selective oxidation method.

In this embodiment, the data is stored in the DRAM cell 17.
When writing data, first, the third MOS transistor
The power supply voltage V is applied to the gate electrode 14 of the star 5._CCIs applied. No.
N of the third MOS transistor 5⁺Deco on the mold conductive layer 16
When an output signal of a conductive layer (not shown) is input, the conductive layer
16 is V_CCbecome. This gives N^-Mold conductive layer 1
5 is V_CC-V_th(V_thIs the gate threshold voltage)
The first MOS transistor 3 is turned on and
3 MOS transistor 5 is turned off, and N^-Type conductive layer
15 is a capacitive coupling of the first MOS transistor 3
The boosted potential V ₀It is boosted even higher. Follow
And the boost voltage V₀Is the first MOS transistor without voltage drop.
Applied to the drain layer 9 of the transistor 3 and the word line WL.
It is.

Thus, the boosted voltage V is applied to the gate electrode 21 of the fourth MOS transistor 18 via the word line WL.
₀ is applied. The fourth MOS transistor 18 selected by the bit selection signal from the bit line BL is turned on, and the electric charge is accumulated in the capacitor 19 connected to the fourth MOS transistor 18, and data is written to the DRAM cell 17.
When a boosted voltage V ₀ higher than the power supply voltage V _CC is applied to the drain layer 8 of the first MOS transistor 3, the first MO
The gate electrode 7 of the S transistor 3 is boosted by the capacitive coupling to have a potential of about twice V ₀ . Therefore, a double boosted voltage is also applied to the N ^{− type} conductive layer 15 of the third MOS transistor 5. However, the conductivity type 15 of the third MOS transistor 5 is reduced in concentration and N
^Since it is a negative type, it has high withstand voltage to the semiconductor substrate 1.

In addition, since the N ^- type conductive layer 15 is formed of a low concentration layer without a high concentration conductive layer, the area of the element does not increase. Moreover, N ^- and type conductive layer 15 of the electrode 38 of polycrystalline silicon comprising the polar impurities the N ^- because it formed on the conductive layer 15, the impurity in the electrode 38 by annealing N ^- type The contact resistance can be reduced by diffusing the conductive layer 15 shallowly.

FIG. 4 is a diagram showing the relationship between the dose of polycrystalline silicon and the contact resistance between the electrode 38 and the N ^{− type} conductive layer 15. In the figure, the vertical axis indicates resistance on a log scale, and the horizontal axis indicates dose on a log scale. FIG.
The film thickness of the polycrystalline silicon electrode 38 is 2000 Å, N ^-
It is obtained under the condition that the impurity dose of the conductive layer 15 is 1 × 10 ¹³ / cm ² , and it can be seen from FIG. 3 that if the dose of polycrystalline silicon is 1 × 10 ¹⁵ / cm ² or more, the contact resistance becomes higher. Is very small.

FIGS. 5 and 6 are enlarged views showing the main parts of the first embodiment of the high breakdown voltage MOS transistor, respectively. In this embodiment, LDD N ⁺ type conductive layer 16 as shown in FIG. 5
It has a structure, ₁ and N N ⁺ -type portion 16 ^- made of the mold portion 16 _2. The impurity concentration of the N ⁺ -type portion 16 ₁ N ^- is greater than the mold section 16 _2, N ^- impurity concentration of the mold portion 16 ₂ N ^- type conductive layer 15 to be substantially the same. Further, as shown in FIG. 6, N ^- Part 16
₂ partially overlaps with the gate electrode 14.

The dose of P ions in N ^{− type} conductive layer 15 is 1 × 10 ³ / cm ² , the thickness of polycrystalline silicon electrode 38 is 2000 °, and the dose of P ions in polycrystalline silicon is 1 ×. Under the conditions of 10 ¹⁵ / cm ² and the distance D between the gate electrode 14 and the contact hole 29 shown in FIG. 5 of 1 μm, a withstand voltage of 20 V could be secured at the drain of the MOS transistor.

Next, the method of forming the first and third MOS transistors 3 and 5 will be described as an example, and the low-concentration drain layer 1 is formed.
An embodiment of a method of manufacturing a semiconductor device having a high-concentration source layer 5 and a high concentration source layer 16 will be described.

First, a first embodiment of the method of manufacturing a semiconductor device according to the present invention will be described. As shown in FIG. 7A, the first and third transistor forming regions T ₁ and T 1 of the semiconductor substrate 1 are formed.
After a field oxide film 42 is formed around _{2 by} the LOCOS method, gate oxide films 6 and 13 are formed by a thermal oxidation method. Thereafter, a polycrystalline silicon film containing impurities is formed and patterned by photolithography, and a gate made of polycrystalline silicon is formed at the center of each of the transistor forming regions T ₁ and T ₂ via gate oxide films 6 and 13. The electrodes 7 and 14 are formed.

Then, N-type impurity ions such as P are implanted and diffused on both sides of the gate electrodes 7 and 14 in a self-aligned manner to form a low-concentration conductive layer 43. In this case, the impurity dose is 10 ¹³ to 10 ¹⁴ / cm ² , and the N ^{− type} conductive layer 43 is formed.

Thereafter, as shown in FIG. 7 (b), an SiO ₂ film 44 is formed to a total thickness of about 1000 ° by the CVD method. Also covered by the third transistor forming region T one of the conductive layers 43 and the resist 45 around its _2, SiO ₂ film 4 by reactive ion etching (RIE) method
4 is selectively removed, the portion of the SiO ₂ film 44 covered by the resist 45 remains, and the sidewalls 4 of the remaining SiO ₂ film 44 beside the gate electrodes 7 and 14.
6 are formed as shown in FIG.

Next, arsenic (As) ions are applied to the semiconductor substrate 1 using the SiO ₂ film 44 and the side walls 46 as a mask.
Implanted and diffused, a high concentration layer of about 10 ²⁰ / cm ³ is formed in a region not covered by the SiO ₂ film 44, and the conductive layer 43 has an LDD structure. In this case, the conductive layer 43 covered with the SiO ₂ film 44 is maintained at a low concentration as shown in FIG.

Thereafter, as shown in FIG.
An O ₂ film 47 is formed, and the SiO ₂ film 47 and the SiO ₂ film 44 are patterned by photolithography to form a contact hole 28 as shown in FIG.
To 31 are formed on the conductive layer 43.

Next, after forming a polycrystalline silicon film 49 having a thickness of about 2000.degree.
Implant at a dose of ¹⁵ / cm ² . Also, the polycrystalline silicon film 49 is selectively etched by photolithography to form contact holes 28 to 3 as shown in FIG.
The polycrystalline silicon film 49 is left in 1.

In this state, the conductive layer 43 formed in the first transistor formation region T ₁ has an LDD structure, one of which forms the drain layer 8 shown in FIG. Among the conductive layers 43 formed in the third transistor formation region T ₂ , the one which is covered with the SiO ₂ film 44 and has a low concentration is the N ^{− type} conductive layer 1.
5 and the other forms a conductive layer 16 having an LDD structure. Further, the polycrystalline silicon film 49 left in the contact holes 28 to 31 is used as the electrodes 35 to 38.

The electrodes 35 to 38 are heated in a subsequent heating step such as thermal oxidation or annealing, and impurities contained in these electrodes are removed from the source layer 9, the drain layer 8, the conductive layer 15,
16 and these layers and the electrodes 35 to 38
And the contact resistance with the electrode becomes low.

Therefore, even if one of the conductive layers 15 of the third MOS transistor 5 to which a voltage higher than the boosted voltage V ₀ is applied is of the N ⁻ type, the contact resistance with the electrode 38 is reduced, and good contact is obtained. I can do it.

By the way, the third MOS transistor 5
N^-Type conductive layer 15_TwoWhen covering with the film 44,
As shown in FIG. 7C, using the resist 45 as a mask, S
iO _TwoWhen the film 44 is patterned, on the semiconductor substrate 1
Remaining SiO_TwoThe periphery of the film 44 has a vertical shape and a step
Occurs. For this reason, SiO_TwoWhen the film 44 is thick,
In the subsequent process, disconnection of wiring and etching residue during processing may occur.
Inconveniences, such as wandering, can occur.

Therefore, a second embodiment of the method of manufacturing a semiconductor device according to the present invention which solves this problem will be described with reference to FIG.

FIG. 9A shows a state in which the resist 45 has been removed from the step of FIG. 7C. Next, FIG. 9 as shown in (b), the second SiO ₂ film 4 by RIE after laminating the second SiO ₂ film 44b to a thickness of 1000Å on the entire
When 4b is etched, the side edge of the SiO ₂ film 44 remaining on the source layer 15 becomes smooth as shown in FIG. 9C, and the step coverage is improved. in this case,
The sidewalls 46 on both sides of the gate electrodes 7 and 14 are doubled, and the thickness is easily controlled by adjusting the thicknesses of the first and second SiO ₂ films 44 and 44b. it can.

Thereafter, the side wall 46 and the SiO ₂
Impurity ions are implanted and diffused using the films 44 and 44b as masks, and the conductive layer 43 having the LDD structure and the low-concentration conductive layer 43 coexist as shown in FIG. 9D in the same manner as in FIG. 7D. .

According to the second embodiment of the method for manufacturing a semiconductor device, the second embodiment of the high breakdown voltage MOS transistor according to the present invention is manufactured. FIG. 10 shows a main part of a second embodiment of the high breakdown voltage MOS transistor. In the present exemplary e.g., N of the N ⁺ type conductive layer 16 ^- -type portion 16 ₂ is formed under the sidewall 46.

Next, the high breakdown voltage MOS transistor according to the present invention will be described.
A third embodiment of the star will be described with reference to FIG. In the figure,
The same reference numerals are given to the same portions as 3 and the description is omitted.
You. In this embodiment, the contact hole 28 and the gate electrode
Distance d to 14₁But the contact hole 29 and the game
Distance d_TwoSet smaller
FIG. 12 shows the distance d_TwoAnd N^-With respect to the withstand voltage of the conductive layer 15
Show the person in charge. According to FIG. _TwoIs about 0.8 μm or more
It can be seen that the breakdown voltage is 20V.

FIG. 13 is a view for explaining fourth and fifth embodiments of the high breakdown voltage MOS transistor according to the present invention. 3, the same parts as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. FIG. 13A shows cross sections of the fourth and fifth embodiments, and FIGS. 13B and 13C show plan views of the fourth and fifth embodiments, respectively. As shown in FIG. 13B, in the fourth embodiment, the contact hole 29 includes a plurality of holes.
On the other hand, as shown in FIG. 13C, in the fifth embodiment, the contact hole 29 is a single hole larger than that in the fourth embodiment. In the fifth embodiment, a larger contact area can be obtained than in the fourth embodiment.

When the electrodes 38 and the like are formed of polycrystalline silicon, the manufacturing steps can be simplified if they are formed in the same step as the conductive layer of the semiconductor device. Therefore, in the second embodiment of the semiconductor device according to the present invention, the polycrystalline silicon layer forming the electrode 38 is also used as a conductive layer in the DRAM. FIG. 14 shows a main part of a second embodiment of the semiconductor device. The same parts as those in FIG. For example, the storage electrode 24 and the electrode 38 of the DRAM may be formed of the same polycrystalline silicon layer, and the bit line BL and the electrode 38 of the DRAM may be formed of the same polycrystalline silicon layer.

Next, a description will be given of a first embodiment of a method of manufacturing a high breakdown voltage MOS transistor according to the present invention, by referring to FIG.
7, the same parts as those in FIGS. 7 and 8 are denoted by the same reference numerals, and the description thereof will be omitted.

In this embodiment, as shown in FIG.
As described with reference to FIG. 7A, the field oxide film 42 is formed by the LOCOS method, the gate oxide film 13 is formed by the thermal oxidation method, and the polycrystalline silicon film is formed and patterned to form the gate electrode 14. Then, a low-concentration conductive layer 43 is formed by ion implantation.

Thereafter, as shown in FIG.
As described with (c), a resist 45 is formed on the conductive layer 43 on the side to which a high voltage is applied. The conductive layer 43 (source layer 16) having the LDD structure is formed by performing ion implantation using the field oxide film 42, the gate electrode 14, and the resist 45 as a mask.

The formation of the interlayer insulating film, the formation of the contact holes, and the formation of the electrodes may be performed in the same manner as in FIGS. 7 and 8, and a description thereof will be omitted.

Next, a description will be given of a second embodiment of the method of manufacturing a high breakdown voltage MOS transistor according to the present invention, by referring to FIG.
7, the same parts as those in FIGS. 7 and 8 are denoted by the same reference numerals, and the description thereof will be omitted.

[0055] In this embodiment, by forming the entire SiO ₂ oxide film 44 after obtaining such a structure shown in FIG. 15 (a) RI
By etching the SiO ₂ oxide film 44 by the E method, a sidewall 46 is formed on the side surface of the gate electrode 14 as shown in FIG. Further, a resist 45 is formed on the conductive layer 43 to which a high voltage is applied. By performing ion implantation using the field oxide film 42, the sidewalls 46, the gate electrode 14, and the resist 45 as a mask, a conductive layer 43 (source layer 16) having an LDD structure is formed.

Next, a description will be given of a third embodiment of the method of manufacturing a high breakdown voltage MOS transistor according to the present invention, by referring to FIG.
7, the same parts as those in FIGS. 7 and 8 are denoted by the same reference numerals, and the invention is omitted. In this embodiment, the conductive layer 43 (source layer 16) having the LDD structure is formed using the SiO ₂ oxide film 44 as a part of the mask instead of the resist 45 shown in FIG.

Next, a description will be given of a fourth embodiment of the method of manufacturing a high breakdown voltage MOS transistor according to the present invention, by referring to FIG.
7, the same parts as those in FIGS. 7 and 8 are denoted by the same reference numerals, and the description thereof will be omitted. In the present embodiment, the SiO 2 shown in FIG.
_{When the 2} oxide film 44 is etched by the RIE method, a sidewall 46 is formed on the side surface of the gate electrode 14. Therefore, when forming the conductive layer 43 (source layer 16) having the LDD structure, the sidewall 46 is also used as a part of the mask.

Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In FIG.
The same parts as those of 7 and 8 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, as shown in FIG. 19A, after forming the gate electrode 14 of the high breakdown voltage MOS transistor 5 and the gate electrode 21 of the MOS transistor 18 of the DRAM cell 17, an SiO ₂ oxide film 44 is formed on the entire surface. . MOS constituting a memory cell by photolithography technology
SiO ₂ oxide film 44 on transistor 18 and on conductive layer 43 (drain layer 15) of high voltage MOS transistor 5
19B, ions are implanted using the SiO ₂ oxide film 44 as a mask to form a conductive layer 43 (source layer 16) having an LDD structure, as shown in FIG. Note that the sidewalls 46 remaining on the side surfaces of the gate electrode 14 when the SiO ₂ oxide film 44 is etched by the RIE method are also used as a part of the mask as in the case of FIG.

Next, a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In the figure, the same parts as those in FIGS. 3 and 9 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, as shown in FIG. 20 (a), SiO ₂
After the oxide film 44 is etched by the RIE method, a SiO ₂ film 44b is further laminated, and the SiO ₂ film 44b is etched by the RIE method.
_{The two} layers 44b are etched. As a result, FIG.
As shown in (b), the side edge of the SiO ₂ oxide film 44 remaining on the conductive layer 43 (source layer 16) and the gate electrode 14 becomes gentle, and both sides of the gate electrode 21 become gentle. For this reason, it is possible to prevent inconveniences such as disconnection of wiring in a subsequent step and occurrence of etching residue during effect processing.

Since the etching of the oxide film directly exposes the substrate surface to the etching, the junction leak increases due to contamination, surface damage and the like. Therefore, it is desirable not to perform etching of the oxide film in the memory cell portion of the DRAM where the minute leakage current causes a deterioration in characteristics. In the third and fourth embodiments of the method of manufacturing a semiconductor device, a step of covering the memory cell portion with a resist when etching the SiO ₂ oxide film 44 is required. However, at the same time, the conductive layer 43 (drain layer 15) of the high breakdown voltage MOS transistor 5 is also covered with the resist, so that the number of steps is not increased. Although the conductive layers 22 and 23 in the memory cell portion have the same relatively low impurity concentration as the conductive layer 43 (drain layer 15), high-concentration ion implantation induces crystal defects and causes junction leakage. This is a rather desirable condition.

In each of the above embodiments, the electrode formed on the low-concentration conductive layer is made of polycrystalline silicon. However, amorphous silicon or high-melting metal silicide may be used instead of polycrystalline silicon. The refractory metal contained in the refractory metal silicide includes tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti).
Etc. Alternatively, a polycide film in which a high melting point metal silicide such as tungsten silicide is stacked on a polycrystalline silicon film may be used as an electrode on the conductive layer. Further, an Al wiring layer may be formed on an electrode made of polycrystalline silicon or polycide, and “AL” in FIG. 1 indicates an Al wiring layer. In order to form the polycide film, for example, after a high-melting point metal film having a thickness of 0.1 μm is laminated on a polycrystalline silicon film having a thickness of 0.1 μm, for example, P ions are formed from above the high-melting point metal film. It may be implanted at a dose of about 10 ¹⁵ / cm ² .

[0062]

According to the present invention, the relatively low-concentration drain / source region of the high-voltage MOS transistor is directly connected to the drain / source electrode, so that the MOS transistor can be miniaturized. Since a conductor containing polycrystalline silicon is used for the source electrode, the drain /
Since it is possible to prevent an increase in contact resistance between the source region and the drain / source electrode and to realize a high breakdown voltage, it is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating the principle of a high breakdown voltage MOS transistor according to the present invention.

FIG. 2 is a diagram showing characteristics of a high breakdown voltage MOS transistor according to the present invention in comparison with a conventional example.

FIG. 3 is a sectional view and a circuit diagram showing a first embodiment of the semiconductor device according to the present invention.

FIG. 4 shows an impurity dose of polycrystalline silicon, an electrode, and N ^−.
FIG. 4 is a diagram showing a relationship with a contact resistance between the conductive layer and a mold conductive layer.

FIG. 5 shows a first example of a high breakdown voltage MOS transistor according to the present invention.
It is sectional drawing which expands and shows the principal part of an Example.

FIG. 6 shows a first example of a high voltage MOS transistor according to the present invention.
It is sectional drawing which expands and shows a principal part of an Example.

FIG. 7 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a sectional view illustrating a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a sectional view illustrating a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 10 is a sectional view showing a main part of a second embodiment of the high breakdown voltage MOS transistor according to the present invention.

FIG. 11 is a sectional view showing a main part of a third embodiment of the high breakdown voltage MOS transistor according to the present invention.

FIG. 12 is a diagram showing a relationship between a distance d ₂ and a breakdown voltage on the N ⁻ type conductive layer side.

FIG. 13 is a sectional view and a plan view of a main part for describing fourth and fifth embodiments of the high breakdown voltage MOS transistor according to the present invention.

FIG. 14 is a sectional view showing a main part of a second embodiment of the semiconductor device according to the present invention.

FIG. 15 is a cross-sectional view illustrating a first embodiment of a method for manufacturing a high withstand voltage MOS transistor according to the present invention.

FIG. 16 is a cross-sectional view for explaining a second embodiment of the method for manufacturing a high withstand voltage MOS transistor according to the present invention.

FIG. 17 is a cross-sectional view for explaining a third embodiment of the method for manufacturing a high withstand voltage MOS transistor according to the present invention.

FIG. 18 is a sectional view for explaining a fourth embodiment of the method for manufacturing a high withstand voltage MOS transistor according to the present invention.

FIG. 19 is a sectional view for explaining the third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 20 is a sectional view illustrating a fourth embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 21 is a circuit diagram illustrating an example of a boot strap word line drive circuit.

FIG. 22 is a cross-sectional view showing an example of a conventional high voltage MOS transistor having an LDD structure.

FIG. 23 is a cross-sectional view illustrating an example of a conventional method for manufacturing a high withstand voltage MOS transistor.

FIG. 24 is a cross-sectional view for explaining another example of a method for manufacturing a conventional high breakdown voltage MOS transistor.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 boost circuit 3 first MOS transistor 4 second MOS transistor 5 third MOS transistor 6, 13 gate oxide film 7, 14 gate electrode 8 source layer 9 drain layer 15 N ^- type conductive layer 16 LDD Structure of conductive layer 35-38 Electrode 44 SiO ₂ film

Claims (7)

(57) [Claims] A semiconductor substrate (1) and an element isolation region (4)
2) a high-breakdown-voltage MOS transistor comprising a first diffusion region (15) and a second diffusion region (16) of the opposite conductivity type to the semiconductor substrate and a gate electrode (14); An impurity concentration of the diffusion region (15) is lower than an impurity concentration of the second diffusion region (16), and is directly connected to at least the first diffusion region (15);
The electrode (38) arranged so as not to be in contact with the element isolation region (42) is made of a conductor (49) containing polycrystalline silicon, and the impurity concentration of the conductor (49) containing polycrystalline silicon is A high breakdown voltage MOS transistor having a higher impurity concentration than the first diffusion region (15). 2. The second diffusion region (16) has a substantially same impurity concentration as the first diffusion region (15) and is formed on a front surface side of the semiconductor substrate (1). (16
With ₂₎ an LDD structure consisting a second region (16 ₁₎ contiguous with the first region has a higher impurity concentration impurity concentration of the first diffusion region (15), according to claim 1 High voltage MOS transistor. 3. The high breakdown voltage M according to claim 2, wherein a sidewall (46) of an insulating film is formed on at least the first region (16 ₂ ) on the side surface of the gate electrode (14).
OS transistor. 4. A conductor (4) containing polycrystalline silicon.
The depth of solid-phase diffusion from 9) to the first diffusion region (15) is shallower than the depth of the first diffusion region.
Or 3 high voltage MOS transistors. 5. A step of selectively forming a field oxide film (42) on a semiconductor substrate (1); and forming a gate oxide film (13) and a gate in a region on the semiconductor substrate defined by the field oxide film. A step of sequentially forming electrodes (14); a step of forming impurity regions (43, 15, 16) of opposite conductivity type to the semiconductor substrate on both sides of the gate electrode by first ion implantation; The regions (43, 15) are masked with the mask layers (45, 4).
4) performing a second ion implantation using the field oxide film, the gate electrode, and the mask layer as a mask to adjust the impurity concentration of the other impurity region (43, 16) to the impurity concentration of the one impurity region. A field oxide film comprising a conductor (49) containing polycrystalline silicon having an impurity concentration higher than that of the one impurity region directly on at least one of the impurity regions. Forming a high-breakdown-voltage MOS transistor. 6. The step of covering one of the impurity regions (43, 15) with a mask layer (45, 44) includes forming the mask layer over the entire surface of the semiconductor substrate (1) and performing selective etching. 6. The method for manufacturing a high withstand voltage MOS transistor according to claim 5, wherein a sidewall (46) of said mask layer is left on at least said other impurity region (43, 16) on a side surface of said gate electrode (14). . 7. A step of selectively forming a field oxide film (42) on a semiconductor substrate (1), and forming a gate oxide film (13) and a gate in a region on the semiconductor substrate defined by the field oxide film. A step of sequentially forming electrodes (14); a step of forming impurity regions (43, 15, 16) of opposite conductivity type to the semiconductor substrate on both sides of the gate electrode by first ion implantation; The regions (43, 15) are masked with the mask layers (45, 4).
4) performing a second ion implantation using the field oxide film, the gate electrode, and the mask layer as a mask to adjust the impurity concentration of the other impurity region (43, 16) to the impurity concentration of the one impurity region. Forming an electrode (38) comprising a conductor (49) containing polycrystalline silicon having an impurity concentration higher than that of the one impurity region directly on at least one of the impurity regions; And the one impurity region (43, 15) is masked with a mask layer (45, 15).
In the step of covering with 44), the mask layer is formed on the entire surface of the semiconductor substrate (1) and selective etching is performed, and at least the other impurity region (43, 16) on the side surface of the gate electrode (14). On the side wall of the mask layer (4
While leaving 6), a second mask layer (44b) is further laminated on the mask layer and selective etching is performed to make the side edges of the mask layer and the portions of the side walls (46) gentle. , A method of manufacturing a high voltage MOS transistor.