JP2002289703A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique by which a memory cell size of an SRAM can be easily reduced without remarkably increasing the number of steps, and to improve the soft error resistance of the SRAM due to alpha rays. SOLUTION: In a semiconductor memory having the SRAM where a memory cell is constituted of a flip flop circuit, which comprises a pair of drive transistors and a pair of load transistors, and a pair of transfer transistors, each gate electrode of the drive transistors, the load transistors and the transfer transistors is constituted by using a first conductive film wiring formed by using a first conductive film provided on a semiconductor substrate, and one side of a pair of local wirings which are cross-coupled between a pair of input- output terminals of the flip flop circuit is constituted by using an embedding groove wiring which includes the gate electrodes and is formed in a first insulating film provided on the semiconductor substrate, and the other of the pair of local wirings is constituted of a second conductive film wiring formed by using a second conductive film provided via the second insulating film on the first insulating film including the embedding groove wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to an SRAM (Static Random Access Memory).
The present invention relates to a semiconductor memory device having an ss memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art The basic structure of an SRAM memory cell as a semiconductor memory device will be described with reference to the drawings.

As shown in the circuit diagram of FIG. 22, the SRAM memory cell includes a flip-flop circuit as an information storage section, and data lines (bit lines BL ₁ and BL ₂ ) for writing and reading information and a flip-flop circuit. And a pair of transfer transistors T ₁ and T ₂ for controlling conduction between the transfer transistors T ₁ and T ₂ . The flip-flop circuit is composed of, for example, a pair of CMOS inverters.
The inverter includes one drive transistor D ₁ (D ₂ ) and one load transistor P ₁ (P ₂ ).

[0004] _One of the source / drain regions of the transfer transistor T ₁ (T ₂ ) is connected to the drain of the load transistor P ₁ (P ₂ ) and the drain of the drive transistor D ₁ (D ₂ ), and the other is connected to the bit line BL ₁ ( BL ₂ ). Also,
The gates of the pair of transfer transistors T ₁ and T ₂ each constitute a part of the word line WL and are connected to each other.

The gates of the driving transistor D ₁ and the load transistor P ₁ constituting one CMOS inverter are
The drain (the storage node N) of the driving transistor D ₂ and the load transistor P ₂ that constitute the other CMOS inverter
₂ ) Connected. The gate of the drive transistor D ₂ and the load transistor P ₂ constituting the latter CMOS inverter is connected to the drive transistor D ₁ and the load transistor P ₁ of the drain constituting the former CMOS inverter (storage node N ₁₎ ing. In this way, one C
The input / output section of the MOS inverter and the gate of the other CMOS inverter are cross-coupled (cross-coupled) to each other via a pair of wirings L ₁ and L ₂ called local wirings (local wirings).

A reference voltage (Vss, eg, GND) is supplied to the source regions of the driving transistors D ₁ and D ₂ , and a power supply voltage (Vcc) is supplied to the source regions of the load transistors P ₁ and P _2. Is done.

The above-described SRAM cell has excellent device characteristics such as high resistance to noise and low power consumption during standby. Conventionally, in this type of SRAM cell, in terms of element characteristics, materials are selected and laid out so as not to impair the symmetry of the element structure as much as possible (that is, to suppress unbalance).

[0008] However, the above-mentioned SRAM cell has the following problems.
The need for six transistors in a memory cell, the need for many wires, and the p-type MOS and n-type
Since element isolation from S is required, there is a problem that the cell area tends to be large. In addition, there is a problem that the number of steps is large in manufacturing.

Conventionally, various proposals have been made for the structure and manufacturing method of a 6-transistor type SRAM cell.

For example, M. Inohara et al., Symp. On VLS
I Tech., P. 64 (1998), describes a method for forming both of a pair of local wirings by a metal damascene process. In this method, a cross couple is formed by forming a tungsten (W) local wiring, which is a buried trench wiring, in different layers. It is described that since the W plug reaching the active region of the substrate and the one (lower) local wiring are simultaneously opened, the SRAM memory cell can be manufactured without increasing the photomask and the number of steps. I have. However, in this method, in order to form the other (upper layer) local wiring, it is necessary to arrange the wiring so as to avoid contact with the lower local wiring, and a sufficient reduction in cell size has not been achieved.

Japanese Patent Application Laid-Open No. H11-251457 describes that in the manufacture of a six-transistor cell, both a pair of local wirings are formed by a metal damascene process and are arranged in the same layer. Also in this method, since it is necessary to arrange a pair of local wirings so as to avoid contact with each other, it is difficult to sufficiently reduce the cell size.

On the other hand, Japanese Patent Application Laid-Open No. 9-260510 discloses the following element structure as a 6-transistor type SRAM memory cell for the purpose of reducing the memory cell size and improving the α-ray soft error resistance. I have. Also,
A similar configuration is described in F. Ootsuka et al., IEDM, p.205 (1998)
It is also described in

In this structure, a pair of local wirings forming a cross couple are formed by etching different conductive layers, respectively, and the upper local wiring is arranged so as to overlap the lower local wiring. A capacitor is formed by these local wirings and an insulating film (capacitive insulating film) interposed between these local wirings.

However, in such an element structure, it is necessary to form contact holes for each of the pair of local wirings in the manufacture thereof, so that the number of steps is increased. Further, in this structure, the local wiring is disposed over a relatively wide area through the thin insulating film up to the upper part of the gate electrode. When patterning the conductive film by anisotropic etching or the like, it is difficult to remove the conductive film near the step, which causes a problem that the conductive film remains in unnecessary portions. In addition, when a capacitor insulating film is formed on such a surface having large irregularities, the film thickness tends to be increased near the step, and when the film thickness near the step is reduced, the flat portion becomes too thin, resulting in poor insulation. It is difficult to form a thin and uniform capacitance insulating film.

[0015]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to easily provide an SR without significantly increasing the number of steps.
An object of the present invention is to provide a technology capable of reducing the memory cell size of an AM. Another object of the present invention is to provide a technique for improving the α-ray soft error resistance of the SRAM.

[0016]

SUMMARY OF THE INVENTION The present invention is a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of driving transistors and a pair of load transistors, and a pair of transfer transistors. A first conductor formed of a first conductor provided on a semiconductor substrate;
The wiring forms gate electrodes of the driving transistor, the load transistor, and the transfer transistor, and includes a second wiring including a second conductor in a groove formed in a first insulating film provided on the semiconductor substrate. One of a pair of local wirings cross-connecting between a pair of input / output terminals of the flip-flop circuit, and a third wiring provided via a second insulating film provided in a region including on the second wiring. so,
A semiconductor memory device, wherein the other of the pair of local wirings is formed, and one of the second wiring and the third wiring has a buried conductive portion formed to bury the inside of the groove. About. Further, in the invention, it is preferable that the second wiring and the third wiring have a portion overlapping with each other via the second insulating film, and the second wiring and the third wiring and the second insulating material interposed therebetween. The present invention relates to the above-described semiconductor memory device in which a capacitor is formed by a film. Further, in the invention, it is preferable that the second conductor is a drain region forming one first drive transistor of the pair of drive transistors, and one of the load transistors of the pair of load transistors. A drain region forming a first load transistor having a gate electrode formed of a common first wiring A and a first driving transistor, and a first region forming a gate electrode of the other second driving transistor and the other second load transistor. It is arranged so as to be in contact with the wiring B,
The third wiring is in contact with a contact portion connected to the first wiring A, a contact portion connected to a drain region of the second drive transistor, and a contact portion connected to a drain region of the second load transistor. And the above-mentioned semiconductor memory device. Further, the present invention is a semiconductor memory device including an SRAM in which a memory cell is formed by a flip-flop circuit including a pair of driving transistors and a pair of load transistors and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. The first formed of a conductive film
The gate electrodes of the driving transistor, the load transistor, and the transfer transistor are formed by conductive film wiring, and the buried trench wiring formed in the first insulating film provided on the semiconductor substrate forms the flip-flop circuit. One of a pair of local wirings cross-coupled between the pair of input / output terminals is formed, and a second conductive film formed of a second conductive film provided on the first insulating film via a second insulating film The present invention relates to a semiconductor memory device, wherein the wiring forms the other of the pair of local wirings.

Further, according to the present invention, the second conductive film wiring is arranged so as to overlap at least a part of the upper surface of the buried trench wiring with the second insulating film interposed therebetween, and The present invention relates to the above-described semiconductor memory device in which a capacitive element is formed by two conductive film wirings and the second insulating film interposed therebetween.

Further, in the present invention, the second conductive film wiring is arranged so as to cover a part of a side surface of the buried trench wiring via the second insulating film, and the buried trench wiring and the second The present invention relates to the above-described semiconductor memory device in which a capacitance element is formed by a conductive film wiring and the second insulating film interposed therebetween.

Further, according to the present invention, the buried trench wiring is a drain region forming one of the pair of drive transistors and a load transistor of one of the pair of load transistors. A drain region forming a first load transistor having a gate electrode formed of a first conductive film wiring A common to the first drive transistor, and a gate electrode of the other second drive transistor and the other second load transistor. The second conductive film wiring is disposed so as to be in contact with the first conductive film wiring B, and the contact portion reaching the first conductive film wiring A and the contact reaching the drain region of the second drive transistor. And a contact portion reaching the drain region of the second load transistor.

Further, according to the present invention, the first conductive film wiring B is preferably
The present invention relates to the semiconductor memory device described above, wherein a branch is made between a drain region of the second drive transistor and a drain region of the second load transistor, and the branched wiring portion is in contact with the buried trench wiring.

Further, according to the present invention, the contact region between the branched wiring portion and the buried trench wiring may be a contact portion reaching the first conductive film wiring A when viewed from the top surface of the substrate, A contact portion reaching the drain region,
And a point equidistant from any of the contact portions reaching the drain region of the second load transistor.

According to another aspect of the present invention, there is provided a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors, and a pair of transfer transistors. A first conductive film wiring formed of the first conductive film
The gate electrodes of the driving transistor, the load transistor, and the transfer transistor are configured, and the buried trench wiring formed in the first insulating film provided on the semiconductor substrate and the buried trench wiring are provided. One of a pair of local wires cross-connecting between a pair of input / output terminals of the flip-flop circuit is constituted by the stack electrode, and a second conductive film provided on the first insulating film via a second insulating film The other of the pair of local wirings is constituted by the second conductive film wiring formed by the method described above, and the second conductive film wiring is formed by at least part of the upper surface and part of the side surface of the stack electrode and the second insulating film. A semiconductor device, wherein the capacitor is constituted by the stack electrode, the second conductive film wiring, and the second insulating film interposed therebetween. On 憶 apparatus. The present invention also provides
A semiconductor memory device including an SRAM in which a memory cell includes a flip-flop circuit including a pair of driving transistors and a pair of load transistors, and a pair of transfer transistors, which is formed using a first conductive film provided over a semiconductor substrate. The gate electrodes of the driving transistor, the load transistor, and the transfer transistor are formed by the first conductive film wiring, and the first conductive film wiring is provided on the semiconductor substrate.
One of a pair of local wirings cross-coupled between a pair of input / output terminals of the flip-flop circuit is constituted by a buried trench wiring formed in the insulating film, and a third insulating film provided on the first insulating film. A second conductive film provided in a groove formed in the film and having an in-groove electrode film at the bottom thereof in contact with the buried groove wiring, provided on the third insulating film via a second insulating film; The other of the pair of local wirings is constituted by a buried electrode embedded in the groove via the in-groove electrode film and the second insulating film, and the buried electrode, the in-groove electrode film, and And a second insulating film interposed therebetween to form a capacitive element.
Further, the present invention is a semiconductor memory device including an SRAM in which a memory cell is formed by a flip-flop circuit including a pair of driving transistors and a pair of load transistors and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. The first conductive film wiring formed of the conductive film forms the respective gate electrodes of the driving transistor, the load transistor, and the transfer transistor, and is formed in a trench formed in the first insulating film provided on the semiconductor substrate. One of a pair of local wirings cross-coupled between the pair of input / output terminals of the flip-flop circuit by the conductive film in the trench, and a second insulating film is formed on the first insulating film. And a buried electrode buried in the groove via the in-groove electrode film and the second insulating film. Other wiring is formed, a semiconductor memory device, wherein the second insulating film and the capacitive element interposed between them and the embedded electrode and the groove conductive film is formed. Further, according to the present invention, there is provided the above-described semiconductor memory, wherein a refractory metal silicide layer is formed on a surface of a gate electrode, a source region, and a drain region of each of the pair of drive transistors, the pair of load transistors, and the pair of transfer transistors. Related to the device.

The present invention is also a method of manufacturing a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of driving transistors and a pair of load transistors, and a pair of transfer transistors.
Forming, on a semiconductor substrate, an active region for forming a source region and a drain region of each of the drive transistor, the load transistor, and the transfer transistor; and each of the drive transistor, the load transistor, and the transfer transistor. Forming a first conductive film on the semiconductor substrate as a wiring constituting the gate electrode of the first embodiment, and patterning the first conductive film to form a first conductive film;
Forming a first insulating film on the semiconductor substrate as one of a pair of local wires cross-coupled between a pair of input / output terminals of the flip-flop circuit; Forming a buried trench wiring in one insulating film; forming a second insulating film on the first insulating film as the other wiring of the pair of local wirings;
Forming a conductive film and patterning the second conductive film to form a second conductive film wiring.

Further, in the present invention, the second conductive film wiring is arranged so as to overlap at least a part of the upper surface of the buried trench wiring via the second insulating film, and the buried trench wiring and the second The present invention relates to the above-described method for manufacturing a semiconductor memory device in which a capacitance element is formed by two conductive film wirings and the second insulating film interposed therebetween.

The present invention is also a method of manufacturing a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors and a pair of transfer transistors.
Forming, on a semiconductor substrate, an active region for forming a source region and a drain region of each of the drive transistor, the load transistor, and the transfer transistor; and each of the drive transistor, the load transistor, and the transfer transistor. Forming a first conductive film on the semiconductor substrate as a wiring constituting the gate electrode of the first embodiment, and patterning the first conductive film to form a first conductive film;
Forming a first insulating film on the semiconductor substrate as one of a pair of local wires cross-coupled between a pair of input / output terminals of the flip-flop circuit; A step of forming a buried trench wiring in one insulating film, a step of exposing a part of a side surface of the buried trench wiring, and a second insulating film on an exposed portion of the buried trench wiring and on the first insulating film. Is formed, a second conductive film is formed, and the second conductive film is patterned so as to overlap a part and an upper surface of a side surface of the buried trench wiring with the second insulating film interposed therebetween.
Forming a second conductive film constituting the other of the pair of local wires, and forming the second conductive film between a part and an upper surface of a side surface of the buried trench wiring and the second conductive film; Forming a capacitive element composed of an insulating film and a method of manufacturing a semiconductor memory device.

Also, in the present invention, the buried trench wiring may be formed by a drain region forming one of the pair of drive transistors and a load transistor of one of the pair of load transistors. And a drain region forming a first load transistor having a gate electrode formed of a first conductive film wiring A common to the first drive transistor, and a gate electrode of the other second drive transistor and the other second load transistor. The second conductive film wiring is formed so as to be in contact with the first conductive film wiring B to be formed, and the second conductive film wiring has a contact hole reaching the first conductive film wiring A and a contact hole reaching the drain region of the second drive transistor. And a contact hole reaching the drain region of the second load transistor at the same time. Either of a contact portion formed by burying a material formed in contact about the method of manufacturing the semiconductor memory device.

Further, according to the present invention, the first conductive film wiring B is
A drain region of the second drive transistor and a drain region of the second load transistor are formed so as to be branched, and the buried trench wiring is formed so as to contact the branched wiring portion. The present invention relates to a method for manufacturing the above semiconductor memory device.

Further, according to the present invention, the surface of the source region and the drain region of each of the pair of driving transistors, the pair of load transistors and the pair of transfer transistors, and the surface of the first conductive film wiring forming the gate electrode are provided. The present invention relates to the above-described method for manufacturing a semiconductor memory device, which includes a step of forming a refractory metal silicide layer.

According to the present invention, by forming a pair of local wirings with different conductive layers, the local wirings can be arranged so as to partially overlap each other.
The area occupied by the memory cells can be reduced.

Further, according to the present invention, since the capacitance element can be constituted by one of the local wirings, the other of the local wirings and the insulating film interposed therebetween, the memory cell can be miniaturized and the operating voltage can be reduced. It is possible to prevent a decrease in α-ray soft error resistance due to the decrease.

Further, according to the present invention, when one of the local wirings provided in the lower layer is constituted by a buried trench wiring, the connection plug can be formed simultaneously with the formation of the local wiring in the lower layer. Can be manufactured.
Further, in the case where one of the local wirings provided in the lower layer is formed of a buried trench wiring, the flatness is improved, so that the capacitor insulating film provided in the upper layer and the other local wiring can be easily formed thin and uniformly. In addition, the yield and device characteristics can be improved.

Further, according to the present invention, by forming a refractory metal silicide layer which is a low-resistance material on the source / drain region or on the gate electrode, the SRA
Even higher speed operation can be realized regardless of the symmetry of the M structure.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described.

As shown in FIG. 1, the SRAM memory cell of the present invention has a word line WL and a pair of bit lines BL ₁ , B
Is disposed at the intersection of the L _2, and a pair of driving transistors D _1, D ₂ and a pair of load transistors P _1, P ₂ and a pair of transfer transistors T _1, T _2. Here, the pair of drive transistors D ₁ , D ₂ and the pair of transfer transistors T ₁ , T ₂ are of an n-channel type, and the pair of load transistors P ₁ , P ₂ are of a p-channel type.

The pair of drive transistors D ₁ and D ₂ and the pair of load transistors P ₁ and P ₂ constitute a flip-flop circuit as an information storage unit for storing 1-bit information. This flip-flop circuit is composed of a pair of CMOS inverters, and each CMOS inverter is composed of one drive transistor D ₁ (D ₂ ) and one load transistor P ₁ (P ₂ ).

_One of the source / drain regions of the transfer transistor T ₁ (T ₂ ) is connected to the load transistor P ₁ (P ₂ ) and the drain of the drive transistor D ₁ (D ₂ ), and the other is connected to the bit line BL ₁ ( BL ₂ ). Also,
The gates of the pair of transfer transistors T ₁ and T ₂ each constitute a part of the word line WL and are connected to each other.

The gates of the driving transistor D ₁ and the load transistor P ₁ constituting one CMOS inverter are
The drain (the storage node N) of the driving transistor D ₂ and the load transistor P ₂ that constitute the other CMOS inverter
₂ ) Connected. The gate of the drive transistor D ₂ and the load transistor P ₂ constituting the latter CMOS inverter is connected to the drive transistor D ₁ and the load transistor P ₁ of the drain constituting the former CMOS inverter (storage node N ₁₎ ing. In this way, one C
Input / output part (storage node) of MOS inverter and the other C
The gate of the MOS inverter is cross-coupled (cross-coupled) to each other via a pair of lines L ₁ and L ₂ called local lines (local lines).

A reference voltage (Vss, eg, GND) is supplied to the source regions of the driving transistors D ₁ and D ₂ , and a power supply voltage (Vcc) is supplied to the source regions of the load transistors P ₁ and P _2. Is done.

First and Second Embodiments First and second embodiments of the present invention will be described below. In the first embodiment, a pair of local wirings L ₁ , L ₂
Are arranged in different layers, the local wiring in the lower layer is formed by buried trench wiring, the local wiring in the upper layer is formed by a plate-shaped conductive film, and the local wiring in the upper layer (plate-shaped) is viewed from the upper surface (plane) of the substrate. A part of the wiring is arranged so as to overlap with at least a part of the upper surface of the lower local wiring (buried trench wiring) via an insulating film. The lower layer local wiring (buried trench wiring), the upper layer local wiring (plate-like wiring), and an insulating film interposed therebetween constitute a capacitive element.

Since the buried trench wiring is thick (long in the depth direction) and the plate-shaped conductive film wiring has a large area on the upper surface, any of the wirings is smaller than the wiring made of a fine linear conductive thin film. Wiring resistance can be reduced.

The specific structure of the SRAM memory cell will be further described with reference to the drawings.

FIG. 2 is a plan view of the memory cell, FIG. 3A is a sectional view taken along line aa 'of FIG. 2, and FIG. 3B is a sectional view taken along line bb' of FIG. In the plan view, an insulating film, bit lines, and plugs connected to the bit lines are omitted.

The six transistors constituting the memory cell are composed of element isolation 5 on a semiconductor substrate made of single crystal silicon.
Is formed in the active region AR surrounded by the region. The n-channel drive transistors D ₁ and D ₂ and the transfer transistors T ₁ and T ₂ are formed in a p-type well region, and the p-channel load transistors P ₁ and P ₂ are formed in an n-type well region. I have.

Each of the pair of transfer transistors T ₁ and T ₂ has an n-type source / transistor formed in the active region of the p-type well.
It comprises a drain region 13a, a gate oxide film 7 formed on the surface of the active region, and a gate electrode 8 formed on the gate oxide film 7. This gate electrode 8
Has a laminated structure of, for example, an impurity-doped polycrystalline silicon film and a refractory metal silicide film (such as a tungsten silicide film, a cobalt silicide film, and a titanium silicide film), and is formed integrally with the word line WL. Word line W
L is provided to extend in a first direction (the left-right direction in FIG. 2), and a pair of transfer transistors are arranged adjacent to each other along the first direction. Further, the pair of transfer transistors have a second gate length direction orthogonal to the first direction.
It is arranged so as to coincide with the direction (vertical direction in FIG. 2).

Each of the pair of drive transistors D ₁ and D ₂ has an n-type source / drain formed in an active region of a p-type well.
It comprises a drain region 13a, a gate oxide film 7 formed on the surface of the active region, and gate electrodes 9 and 10 formed on the gate oxide film 7. The gate electrodes 9 and 10 are made of, for example, an impurity-doped polycrystalline silicon film and a refractory metal silicide film (a tungsten silicide film,
(A cobalt silicide film, a titanium silicide film, etc.). Drain region of the driving transistor D ₁ is formed on one common active region of the source / drain region of the transfer transistor T _1, the drain region of the driving transistor D ₂ is the source / drain region of the transfer transistor T ₂ It is formed in an active region common to one.

Each of the pair of load transistors P ₁ and P ₂ is connected to a p-type source / source formed in an active region of an n-type well.
It comprises a drain region 13b, a gate oxide film 7 formed on the surface of the active region, and gate electrodes 9 and 10 formed on the gate oxide film 7. The gate electrode 9 of the load transistor P ₁ is integrally formed with the gate electrode of the driving transistor D _1, the gate electrode 10 of the load transistor P ₂ is formed integrally with the gate electrode of the driving transistor D _2.

The drive transistor D ₁ is connected to the transfer transistor T ₁ and the load transistor P ₁ in the second direction.
And is located between. Drive transistor D _2, in the second direction, it is arranged between the transfer transistor T ₂ and the load transistor P _2. Each of the pair of drive transistors and the pair of load transistors
The gate length direction is arranged so as to coincide with the first direction.

The surfaces of the source / drain regions of each of the pair of drive transistors, the pair of load transistors, and the pair of transfer transistors are formed of titanium silicide or cobalt silicide for the purpose of reducing sheet resistance or connection resistance with connection plugs. Refractory metal silicide layer (not shown)
Is preferably provided.

A side wall 12 is formed on the side wall of the gate electrode constituting each of the pair of drive transistors, the pair of load transistors, and the pair of transfer transistors. Further, a cap layer (not shown) made of a silicon oxide film or the like may be provided above the gate electrode.

A silicon nitride film 14 is formed on the upper part of the six transistors.
PSG or B with a thickness of about 300 to 1000 nm
A first interlayer insulating film 15 made of PSG or the like is formed.

A buried trench wiring 16 (L ₁ ), which is one of a pair of local wirings, is formed in the first interlayer insulating film 15. The buried groove wiring 16 (L ₁ ) is formed by burying a conductive metal such as W in a groove formed by opening the first interlayer insulating film 15. One end of the buried trench wiring 16 (L ₁ ) is electrically connected to the drain region of the drive transistor D ₁ , and the other end is electrically connected to the drain region of the load transistor P ₁ . Furthermore, the buried groove wiring 1
6 (L ₁ ) is electrically connected to the gate electrode 10 common to the driving transistor D ₂ and the load transistor P ₂ . The gate electrode 10 is connected to the drive transistor D
_{2 and} the drain region of the load transistor P ₂ , branching in the direction of the transistors D ₁ and P _1, and the branched portion is in contact with the center of the buried trench wiring 16. It is preferable that this contact portion be disposed at substantially the same distance from any of the three contact plugs 18, 19, and 20 described later when viewed from the top. At that time, the buried groove wiring 16
The (L ₁ ) shape can be a rectangular band shape when viewed from the top, but as shown in the plan view of FIG. 2, it is bent so that both ends protrude toward the transistors D ₂ and P _2. It may be a strip-like shape. Thereby, a sufficient margin can be secured.

The first in which the buried trench wiring 16 (L ₁ ) is formed
On the interlayer insulating film 15, a second interlayer insulating film 17 made of a silicon oxide film or the like and having a thickness of about 10 nm to 150 nm is formed. Then, the second interlayer insulating film 17 and the first
A connection plug in which a conductive metal such as W is embedded in a connection hole opened in the interlayer insulating film 15 is provided. These connection plug is a plug 19-26 that connect to the source / drain regions of the six transistors, a plug 18 connected to the common gate electrode 9 to the drive transistor D ₁ and the load transistor P _1.

On top of the second interlayer insulating film 17, a thickness of 10
Local wiring 2 of TiN or the like of about 0 to 200 nm
7 (L ₂ ) are formed. Local wiring 27 (L ₂ )
Are connected to a plug 18 connected to the gate electrode 9 common to the drive transistor D ₁ and the load transistor P ₁ , a plug 19 connected to the drain region of the drive transistor D ₂ , and a plug 20 connected to the drain region of the load transistor P _2. It is provided so as to be connected to each other. Also, a part of the local wiring 27 (L ₂ ) is arranged so as to overlap with at least a part of the upper surface of the buried trench wiring 16 (L ₁ ), which is the other local wiring, via the second interlayer insulating film 17. Is done.
The local wiring 27 (L ₂ ), the buried trench wiring 16 (L ₁ ), and the second interlayer insulating film interposed therebetween constitute a capacitive element. In view of the provision of the capacitive element, the local wiring 27
(L ₂ ) preferably covers the upper surface of the buried groove wiring 16 (L ₁ ) as much as possible. In the configuration shown in FIG. 2, the local wiring 27 (L ₂ ) is formed on the upper surface of the buried groove wiring 16 (L ₁ ). It covers the whole.

Incidentally, on the connection plugs 21 to 26, rectangular conductive film patterns 28 to 33 are formed simultaneously with the local wiring 27 (L ₂ ) in order to facilitate connection with via plugs from above. Are formed.

A third interlayer insulating film 34 made of a silicon oxide film or the like is formed on the second interlayer insulating film 17 on which the local wiring 27 (L ₂ ) is formed, and a power supply voltage Vcc is provided on the third interlayer insulating film 34. The applied power supply voltage line 41 and the reference voltage V
A reference voltage line 42 to which ss is applied is formed along the first direction. The power supply voltage line 41 is connected to the third interlayer insulating film 3.
4, connection plugs (via plugs) 36 and 37 provided in the first and second interlayer insulating films;
23, they are electrically connected to the source regions of the load transistors P ₁ and P ₂ , respectively. Reference voltage line 42
Drive transistors D ₁ and D ₂ via connection plugs (via plugs) 35 and 38 provided in the third interlayer insulating film 34 and connection plugs 21 and 24 provided in the first and second interlayer insulating films, respectively. Is electrically connected to the source region of These wirings can be composed of, for example, a patterned aluminum film, or a laminated film in which a film made of TiN or the like is disposed as an anti-reflection film on the upper part of the aluminum film and as a barrier metal film on the lower part.

Note that the third transistor is electrically connected to one of the source / drain regions of the transfer transistors T ₁ and T ₂ .
On top of the plugs 39 and 40 provided in the interlayer insulating film 34, a rectangular conductive film patterned simultaneously with the power supply voltage line 41 and the reference voltage line 42 to facilitate connection with the via plug from the upper layer. Patterns 43 and 44 are formed.

A fourth interlayer insulating film (not shown) made of a silicon oxide film or the like is formed on the third interlayer insulating film 34 on which the power supply voltage line 41 and the reference voltage line 42 are formed. , A pair of bit lines B along the second direction.
L ₁ and BL ₂ (not shown) are formed. One of the bit lines BL ₁ includes a connection plug (via plug) provided in the fourth interlayer insulating film, a connection plug 40 provided in the third interlayer insulating film, and a connection plug provided in the first and second interlayer insulating films. 26, it is electrically connected to _one of the source / drain regions of the transfer transistor T1. The other bit line BL ₂ includes a connection plug (via plug) provided in the fourth interlayer insulating film, a connection plug 39 provided in the third interlayer insulating film, and a connection plug provided in the first and second interlayer insulating films. It is electrically connected to one of the source / drain region of the transfer transistor T ₂ through 25. These wirings can be composed of, for example, a patterned aluminum film, or a laminated film in which a film made of TiN or the like is disposed as an anti-reflection film on the upper part of the aluminum film and as a barrier metal film on the lower part.

According to a second embodiment of the present invention, in the above-described structure, the configuration of the capacitive element is such that, when viewed from the upper surface of the substrate, a part of the upper local wiring (plate-like wiring) is formed in the lower local wiring (embedded). In addition to being arranged so as to overlap with at least a part of the upper surface of the groove wiring) via an insulating film,
Part of the upper local wiring (plate-like wiring) is arranged to partially cover the side surface (surface along the depth direction) of the lower local wiring (embedded trench wiring) via an insulating film. May be adopted. According to this structure, since the capacitance element is formed not only on the upper surface but also on the side surface of the local wiring (buried trench wiring) in the lower layer, the capacitance of the element can be increased. FIG. 21 shows a cross-sectional view (corresponding to the plan view of FIG. 2) of an example of this embodiment.

Next, the SRAM of the semiconductor memory device of the present invention will be described.
A method of manufacturing a memory cell will be described with reference to the drawings, taking the method of manufacturing the first embodiment as an example. Note that, in the plan views, the insulating film is omitted as appropriate.

First, a silicon oxide film 2 and a silicon nitride film 3 are sequentially formed on a main surface of a semiconductor substrate 1 made of p-type single crystal silicon by a conventional method. Subsequently, the silicon nitride film 3 and the silicon oxide film 2 are patterned by dry etching using a photoresist having a predetermined pattern shape formed by a conventional method as a mask. Thereafter, the semiconductor substrate 1 is dry-etched using the remaining silicon nitride film 3 and silicon oxide film 2 as a mask to form trenches 4 for element isolation (FIGS. 4 and 5). In the figure, AR
Is an active region. In this step, a trench 4 for element isolation is formed in a region other than the AR. A region surrounded by a dotted line indicated by MR indicates one memory cell region. The plurality of memory cells are arranged between adjacent memory cells with each side along the first direction (the left-right direction in FIG. 4) of a rectangle indicated by MR as a target axis.
Are arranged so that the shape becomes line-symmetric (mirror inversion),
In addition, the rectangular shape indicated by MR is arranged so as to be parallel-shifted (shifted) in the first direction with each side along the second direction (vertical direction in FIG. 4) as a reference line.
In addition, each side of the rectangle indicated by MR is set as an axis of symmetry and AR
Can be arranged on the substrate so that the shape of the line becomes symmetrical.

Next, as shown in FIG. 6, a silicon oxide film is buried in the trench 4 to form an element isolation 5. This element isolation 5 is formed by forming a silicon oxide film on the semiconductor substrate 1 including the trench 4 by the CVD method.
After the silicon nitride film 3 is used as a stopper, the thick silicon oxide film is etched back or chemically and mechanically polished (CMP) to completely fill the inside of the trench 4. It can be formed by removing the silicon oxide film.

Next, the silicon nitride film 3 on the semiconductor substrate 1
And after removing the silicon oxide film 2 by etching,
As shown in FIGS. 7 and 8, the thickness 10~30nm about thin silicon oxide film (sacrificial oxide film) 2a is formed, followed by forming a resist 6 in the region for forming the load transistors P _1, P ₂ . The resist 6 as a mask, said p-type impurity oxide film 2a as a through film (e.g., boron) is ion-implanted, p-type well region provided after the driving transistor D _1, D ₂ and the transfer transistor T _1, T ₂ To form Next, after removing the resist 6, a resist is formed on the p-type well region, and this resist is used as a mask,
Using the oxide film 2a as a through film, an n-type impurity (for example, phosphorus or arsenic) is ion-implanted to form an n-type well region provided with the load transistors P ₁ and P ₂ later.

Next, after removing the silicon oxide film (sacrificial oxide film) 2a on the semiconductor substrate, a gate oxide film is formed by a thermal oxidation method, and then an impurity-doped polycrystalline silicon film is formed. At this time, a refractory metal silicide film such as a W silicide film may be formed on the impurity-doped polycrystalline silicon film, and a silicon oxide film for forming a cap layer may be formed thereon. Next, dry etching is performed using the photoresist formed in a predetermined pattern as a mask, and the impurity-doped polycrystalline silicon film and the gate oxide film (if a high-melting metal silicide film and a silicon oxide film are formed, the silicide film and the oxide film are further added). ) Is simultaneously patterned to form transfer transistors T ₁ , T _{2 as} shown in FIGS.
Gate electrode (word line WL) 8 and drive transistor D
₁ , D ₂ and the gate electrodes 9 of the load transistors P ₁ , P ₂ ,
Form 10.

Next, the transistor structure shown in FIGS. 11 and 12 is formed as follows. Using a resist formed on the n-type well region as a mask, an n-type impurity (for example, phosphorus or arsenic) is ion-implanted with a relatively small implantation amount to form the LDD region 11 in the p-type well region. After removing the resist, similarly, using the resist formed on the p-type well region as a mask, a p-type impurity (for example, boron) is ion-implanted, and the LDD region 11 is formed in the n-type well region.
To form Next, after removing this resist, CV
A silicon oxide film is formed on the substrate by the method D, and the silicon oxide film is etched back to form a sidewall 12 on a side surface of the gate electrode. The sidewall may be a stacked film composed of an oxide film-nitride film-oxide film or a nitride film-polycrystalline silicon film. Thereafter, using the resist formed on the n-type well region as a mask, n-type impurities are ion-implanted in a relatively large implantation amount to form n-type source / drain regions 13a in the p-type well region. continue,
After removing the resist, similarly, p-type impurities are ion-implanted using the resist formed on the p-type well region as a mask, and p-type source / drain regions 1 are formed in the n-type well region.
3b is formed.

After this step, a high melting point silicide film is preferably formed on the source / drain regions. First, a refractory metal (eg, Ti, Co) film is formed on a semiconductor substrate by a sputtering method or the like. Next, heat treatment (annealing) is performed to cause the high melting point metal film to react with the source / drain regions, and then the unreacted high melting point metal is removed by etching. As a result, a refractory metal silicide film is formed on the source / drain regions. At this time, if the W silicide film and the silicon oxide film are not provided on the gate electrode in the above process, a high melting point metal silicide film is also formed on the gate electrode.

Next, after a silicon nitride film 14 is formed on the semiconductor substrate by the CVD method, an interlayer insulating film 15 made of PSG, BPSG, or the like is formed. Next, dry etching is performed by using the photoresist formed in a predetermined pattern as a mask to open the first interlayer insulating film 15 and the silicon nitride film 14, thereby forming a groove reaching the substrate surface and the gate electrode. By embedding this groove with a conductive metal such as W,
As shown in FIGS. 13 and 14, a local wiring 16 (L ₁ ) composed of a buried trench wiring is formed. At this time, the conductive metal is buried in the groove, for example, by a sputtering method or the like.
/ TiN laminated film is formed on a substrate including the inside of a groove, and then a conductive metal film made of W or the like is formed by a CVD method or the like so as to fill the groove.
CMP can be performed on these metal films to remove the conductive metal film and the barrier metal film other than in the trench.

Next, after a second interlayer insulating film 17 made of a silicon oxide film or the like is formed by a CVD method, dry etching is performed using a photoresist as a mask to form a gate electrode 9.
And a contact hole (contact hole) reaching the source / drain region. After forming a barrier metal film composed of Ti, TiN, a laminated film of these on the substrate surface including the inside of the connection hole, a conductive metal film such as W is formed so as to bury these connection holes by a CVD method or the like,
CMP is performed on these metal films to remove the conductive metal film and the barrier metal film other than those in the connection holes. Thereby, as shown in FIGS. 15 and 16, the connection plug 18 reaching the gate electrode 9 and the connection plugs 19 to 26 reaching the source / drain regions are formed at the same time. At this time, when performing etch back instead of CMP, a barrier metal film composed of Ti, TiN, or a laminated film of these is left on the surface, and the barrier metal film is patterned using a resist as a mask, thereby forming a method described later. Instead of local wiring (L ₂ )
27 and conductive film patterns 28 to 33 can be formed.

Next, a conductive film such as a TiN film is formed by a sputtering method or a CVD method, and the conductive film is patterned by using a photoresist as a mask. As a result, as shown in FIGS.
Local wirings (L ₂ ) 27 that contact with 8, 19 and ₂₀ are formed. At this time, the local wiring (L ₂ ) 27 is formed such that a part thereof overlaps at least a part of the lower local wiring (L ₁ ) 16 via the second interlayer insulating film 17 as viewed from the upper surface. In the figure, the local wiring (L
₂ ) 27 is formed so as to overlap with the entire upper surface of the local wiring (L ₁ ) 16 in the lower layer.

At the time of patterning for forming the local wiring (L ₂ ) 27, connection between connection plugs (via plugs) formed later in the upper layer and connection plugs (contact plugs) 21 to 26 is easily performed. To this end, rectangular conductive film patterns 28 to 33 that are in contact with and cover the upper surfaces thereof are simultaneously formed on the respective connection plugs 21 to 26.

Next, after a third interlayer insulating film 34 made of a silicon oxide film or the like is formed by the CVD method, dry etching is performed using a photoresist as a mask to form connection holes (reaching the conductive film patterns 28 to 33). Via holes). After forming a barrier metal film on the substrate surface including the inside of the connection hole, a conductive metal film made of W or the like is formed by a CVD method or the like so as to fill these connection holes, and CMP is performed on the metal film. The conductive metal film other than the connection holes and the barrier metal are removed. As a result, as shown in FIGS. 19 and 20, connection plugs (via plugs) reaching the conductive film patterns 28 to 33 are formed.

Next, as shown in FIGS. 2 and 3, a power supply voltage line 41 to which the power supply voltage Vcc is applied and a reference voltage line 42 to which the reference voltage Vss is applied, on the third interlayer insulating film 34.
To form These wirings can be formed by forming an Al film on the third interlayer insulating film 34 by a sputtering method or the like, and then performing dry etching using a photoresist as a mask to pattern the Al film. At that time, Al
Instead of a film, a barrier metal film (such as a TiN film), an Al film,
A laminated film formed by sequentially forming an anti-reflection film (TiN film or the like) may be provided. The power supply voltage line 41 is connected to the connection plugs 36, 3
7 and is electrically connected to the respective source regions of the load transistors P ₁ and P ₂ . The reference voltage line 42 comes into contact with the connection plugs 35 and 38, and the drive transistors D ₁ ,
It is electrically connected to respective source regions of D _2.

The power supply voltage line 41 and the reference voltage line 42
During the patterning for forming the connection, the connection plug 3 communicating with one of the source / drain regions of the transfer transistor
9 and 40 and bit lines BL ₁ ,
To facilitate the connection with the connection plug leading to the BL _2, on the connection plug 39, 40 in contact against the respective and forms a rectangular conductive pattern 43 and 44 covering the upper surface.

Next, a fourth interlayer insulating film made of silicon oxide or the like is formed by a CVD method on the third interlayer insulating film 34 on which the power supply voltage line 41, the reference voltage line 42 and the like are formed. Next, dry etching using a photoresist as a mask is performed to form connection holes reaching the conductive film patterns 43 and 44 formed on the connection plugs 39 and 40, respectively. Subsequently, after a barrier metal film is formed on the fourth interlayer insulating film including the inside of these connection holes, a conductive metal film made of W or the like is formed by a CVD method or the like so that these connection holes are buried. . Next, the metal film other than the inside of the connection hole is removed by CMP to form a connection plug.

Next, bit lines BL ₁ and BL ₂ are formed on the fourth interlayer insulating film on which these connection plugs are formed.
These bit lines can be formed by forming an Al film on the fourth interlayer insulating film by a sputtering method or the like, then performing dry etching using a photoresist as a mask, and patterning the Al film. At that time, instead of the Al film,
A laminated film formed by sequentially forming a barrier metal film (such as a TiN film), an Al film, and an antireflection film (such as a TiN film) may be provided. Each bit line contacts one of the connection plugs formed in the fourth interlayer insulating film and is electrically connected to one of the source / drain regions of one of the transfer transistors T ₁ and T ₂ .

Through the above steps, the memory cell of this embodiment is completed. After that, a desired process can be appropriately performed, for example, by forming a passivation film on the fourth interlayer insulating film on which the bit lines are formed.

The structure of the second embodiment described with reference to FIG. 21 as another embodiment can be formed as follows.

Subsequent to the step of forming the structure shown in FIG. 14 (the step of forming the buried trench wiring 16 (L ₁ )), the buried trench wiring 1 is formed.
Etch-back is performed so that the upper surface of the first interlayer insulating film 15 is lower than the upper surface of 6 and the side surfaces of the buried trench wiring are partially exposed.

Next, after a second interlayer insulating film 17 made of a silicon oxide film or the like is formed by a CVD method, dry etching is performed using a photoresist as a mask to form a gate electrode 9.
And a contact hole (contact hole) reaching the source / drain region. After forming a barrier metal film composed of Ti, TiN, a laminated film of these on the substrate surface including the inside of the connection hole, a conductive metal film such as W is formed so as to bury these connection holes by a CVD method or the like,
The metal film is etched back to remove the conductive metal film and the barrier metal film other than in the connection holes. Thus, connection plugs 18 reaching the gate electrode 9 and connection plugs 19 to 26 reaching the source / drain regions are formed at the same time.

Next, a conductive film such as a TiN film is formed by a sputtering method or a CVD method, and the conductive film is patterned by using a photoresist as a mask. Thereby, as shown in FIG. 21, the connection plugs 18, 19, 2
A local wiring (L ₂ ) 27 that contacts 0 is formed.
At this time, the local wiring (L ₂ ) 27
A part thereof is formed so as to overlap at least a part of the upper surface of the lower local wiring (L ₁ ) (buried trench wiring 16) or the entire upper surface via the second interlayer insulating film 17, and the buried trench wiring is formed. The exposed side surfaces of the second interlayer insulating film 1
7 so as to cover it.

Hereinafter, as another embodiment of the present invention, a configuration in which the capacitance of the capacitive element is further increased will be described.

Third Embodiment FIG. 23 is a sectional view showing the structure of the present embodiment. FIG.
3A and 3B respectively correspond to FIGS. 3A and 3B showing the structure of the first embodiment.

In the structure of this embodiment, the buried trench wiring
The local wiring 16 (L ₁) Stack electricity on
The pole 101 is arranged. Plate-shaped upper layer loca
Wiring 27 (L_Two) Shows this stack through the insulating film 17.
At least a part of the upper surface and a part of the side surface of the
It is arranged to cover. In the figure, the stack electrode 10
1 is partially covered on the top and side, but merged
Each may cover the whole if allowed. like this
According to such a configuration, the capacitance element is also provided on the side of the stack electrode.
The capacitance of the element.
it can.

The structure of this embodiment can be formed as follows.

Up to the step shown in FIG. 14, the same operation as in the first embodiment is performed. Thereafter, as shown in FIG.
A film of HSG, TiN, or the like is formed, and the formed conductive film is patterned by ordinary lithography to form a stack electrode 101 on the lower local wiring 16 (L ₁ ). At the time of this patterning, a mask having the same pattern as that of the local wiring 16 (L ₁ ) in the lower layer can be used. The lower local wiring 16 (L ₁ ) and the stack electrode 101 are
Within a range in which electrical continuity and a margin are allowed, they may be arranged so as to partially overlap each other at a planar position viewed from above, or to include the other. After the stack electrode 101 is formed in this manner, the second
An interlayer insulating film 17 (a high dielectric constant film such as SiO ₂ , SiN, or TaO) is formed. Thereafter, connection plugs 18 reaching the gate electrode and connection plugs 19 to 26 reaching the source / drain regions are formed. Next, as shown in FIG. 25, a plate-like local wiring 27 (L ₂ ) in the upper layer is formed, and then a third interlayer insulating film 34 is formed.
The configuration shown in FIG. Providing the stack electrode 101,
An upper local wiring 27 is formed so as to cover the stack electrode.
(L ₂ ), and the first interlayer insulating film 34 is formed thicker by providing the stack electrode.
Can be manufactured in the same manner as in the embodiment.

Fourth Embodiment FIG. 27 is a sectional view showing the structure of the present embodiment. FIG.
3A and 3B respectively correspond to FIGS. 3A and 3B showing the structure of the first embodiment.

In the structure of the present embodiment, a groove is provided in the third interlayer insulating film 34 provided before the second interlayer insulating film 17 serving as a capacitive insulating film, and the groove covers the side wall in the groove. And a cylinder electrode (square cylindrical electrode film in a groove) 1 in contact with the lower local wiring 16 (L ₁ ) at the bottom thereof.
And a buried electrode 112 buried via the second interlayer insulating film 17 and a second interlayer insulating film 17 interposed therebetween. According to such a configuration, since the capacitance element is also formed on the side wall in the groove, the capacitance of the element can be increased.

The structure of this embodiment can be formed as follows.

Up to the step shown in FIG. 14, the same as in the first embodiment is performed.
After that, as shown in FIG.
The film 34 is provided, and the local wiring 16 (L₁) On top
The groove is formed so that at least a part of the upper surface of the
You. Next, a conductive film made of DOPOS, DOPOS-HSG, TiN, etc.
Is formed, then a resist is applied, and the resist film is
Etch back to remove the resist outside the groove. next,
The conductive film is etched back to remove the conductive film outside the groove.
Removes the resist inside the groove, resulting in a seal on the inner surface of the groove.
A solder electrode (electrode film in a groove) 111 is formed (FIG. 2).
9). After that, the second interlayer insulating film 17 serving as a capacitive insulating film
(SiO_TwoOr high dielectric constant film such as SiN or TaO)
To form When forming the groove, the lower layer local wiring
16 (L₁) Can use the same pattern of mask
You. Further, the local wiring 16 (L ₁) And cylinder
The electrode 111 is electrically conductive and a margin is allowed.
Within the range, partially overlapped
Or may be arranged to include the other. Next
Provided on the third interlayer insulating film 34 and the first interlayer insulating film 15
A via hole is formed to reach the connection plug. Next
First, a barrier metal film (Ti or T
iN, TiN / Ti laminated film). At that time, in the groove
May be embedded with the barrier metal (embedded electrode 1
12). Also, if the width of the groove is wide enough,
Form a barrier metal film on the surface and fill it with a conductive material such as W
May be embedded. Then, use a conductive material such as W
Embed and etch back, the structure shown in FIG.
obtain. At this time, the barrier metal on the substrate surface remains
You may. Next, in the same manner as in the manufacturing method of the first embodiment,
As shown in FIG. 31, plate-shaped upper layer local wiring 27
(L_Two), And then a fifth interlayer insulating film 201 is formed.
It is formed into the structure shown in FIG. Hereinafter, the first embodiment
An SRAM memory cell is formed in the same manner as in the first embodiment.

Fifth Embodiment FIG. 33 is a sectional view showing the structure of the present embodiment. FIG.
3A and 3B respectively correspond to FIGS. 3A and 3B showing the structure of the first embodiment. In the configuration of the present embodiment, a groove is provided in the first interlayer insulating film 15, and a rectangular cylindrical local lower wiring 16 (L ₁ ) that covers a side wall in the groove is provided in the groove. The bottom surface (the contact surface with the substrate) of the cylindrical lower local wiring 16 (L ₁ ) is the lower local wiring (L ₁ ) of the first embodiment.
_It has the same shape as the bottom surface of the buried trench wiring which is ₁ ) and is arranged similarly. The buried electrode 112 buried in the groove via the cylindrical lower local wiring 16 (L ₁ ) in the groove and the second interlayer insulating film 17 and the second interlayer insulating film 17 interposed therebetween And constitute a capacitive element. According to such a configuration, since the capacitance element is also formed on the side wall in the groove, the capacitance of the element can be increased.

The structure of the present embodiment can be formed as follows.

Until the groove in the step shown in FIG. 14 is filled with a conductive material, the same as in the first embodiment is performed, as shown in FIG.
The structure shown in FIG. Next, DOPOS, DOPOS-HSG, Ti
A conductive film made of N or the like is formed, then a resist is applied, and the resist film is etched back to remove the resist outside the groove. Next, the conductive film is etched back to remove the conductive film outside the groove, and then the resist inside the groove is removed,
As a result, a rectangular cylindrical lower local wiring 16 (L ₁ ) is formed on the inner surface of the groove (FIG. 35). After that, a second interlayer insulating film 17 (SiO ₂ , SiN,
Alternatively, a high dielectric constant film such as TaO) is formed. Next, a predetermined contact hole is formed in the first interlayer insulating film 15,
A barrier metal film (Ti, TiN, TiN / Ti laminated film) is formed in these contact holes. At this time, the inside of the groove may be buried with the barrier metal (formation of buried electrode 112). If the width of the groove is sufficiently large, a barrier metal film may be formed on the inner surface of the groove and may be embedded with a conductive material such as W. Subsequently, the contact holes are buried with a conductive material such as W and etched back to obtain a structure shown in FIG. At this time, the barrier metal on the substrate surface may remain. Next, a plate-like upper local wiring 27 (L ₂ ) is formed as shown in FIG. 37, and then a third interlayer insulating film 34 is formed in the same manner as in the manufacturing method of the first embodiment. The structure shown in FIG. Thereafter, an SRAM memory cell is formed in the same manner as in the manufacturing method of the first embodiment.

[0092]

As is apparent from the above description, according to the present invention, the number of steps can be easily increased without significantly increasing the number of steps.
An SRAM with a reduced memory cell size can be obtained. Further, the α-ray soft error resistance of the SRAM can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an SRAM memory cell of a semiconductor memory device of the present invention.

FIG. 2 is a plan view illustrating one embodiment of an SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 3 is a cross-sectional view illustrating one embodiment of an SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 4 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device according to the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 6 is a cross-sectional view for describing the method for manufacturing the SRAM memory cell of the semiconductor memory device according to the present invention.

FIG. 7 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 9 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 11 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 13 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 15 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 16 is a sectional view for illustrating the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 17 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 18 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 19 is a plan view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device according to the present invention.

FIG. 20 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 21 is a cross-sectional view for explaining another embodiment of the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 22 is a circuit diagram of a conventional SRAM memory cell.

FIG. 23 is a cross-sectional view for explaining another embodiment of the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 24 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 25 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 26 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 27 is a cross-sectional view for explaining another embodiment of the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 28 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 29 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 30 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 31 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 32 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 33 is a cross-sectional view for explaining another embodiment of the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 34 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 35 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 36 is a cross sectional view for illustrating the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 37 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

FIG. 38 is a cross-sectional view for explaining the method for manufacturing the SRAM memory cell of the semiconductor memory device of the present invention.

[Explanation of symbols]

T ₁ , T ₂ transfer transistor D ₁ , D ₂ drive transistor P ₁ , P ₂ load transistor BL ₁ , BL ₂ bit line WL word line L ₁ , L ₂ local wiring N ₁ , N ₂ storage node Vcc power supply voltage Vss reference Voltage AR Active region MR One memory cell region 1 Semiconductor substrate 2 Silicon oxide film 2a Silicon oxide film (sacrifice oxide film) 3 Silicon nitride film 4 Trench (groove) 5 Element isolation 6 Resist 7 Gate oxide film 8 Gate electrode (word line) WL) 9, 10 Gate electrode 11 LDD region 12 Side wall 13 Source / drain region 13a N-type source / drain region 13b P-type source / drain region 14 Silicon nitride film 15 First interlayer insulating film 16 Local wiring (L ₁ ) 17 the second interlayer insulating film 18 to 26 connecting plug 27 local interconnection (L ₂₎ 28-3 , 43, 44 Conductive film pattern 34 Third interlayer insulating film 35-40 Connection plug (via plug) 41 Power supply voltage line 42 Reference voltage line 101 Stack electrode 111 Cylinder electrode (electrode film in groove) 112 Embedded electrode 119, 121, 124 , 126 Connection plug (via plug) 201 Fifth interlayer insulating film

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5F083 BS05 BS17 BS27 BS38 BS46 BS48 GA09 GA18 JA06 JA19 JA35 JA36 JA39 JA40 JA53 JA56 KA15 KA16 LA01 MA04 MA06 MA16 MA19 MA20 NA01 PR39 PR40

Claims (19)

[Claims] 1. A semiconductor memory device including an SRAM in which a memory cell is constituted by a flip-flop circuit including a pair of drive transistors and a pair of load transistors and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. The first wiring formed of a conductor forms the respective gate electrodes of the driving transistor, the load transistor, and the transfer transistor, and the second wiring in the groove formed in the first insulating film provided on the semiconductor substrate One of a pair of local wirings cross-coupled between a pair of input / output terminals of the flip-flop circuit is constituted by a second wiring including a conductor, and a second insulating film provided in a region including on the second wiring is formed. The other of the pair of local wirings is configured by a third wiring provided via the first wiring, and one of the second wiring and the third wiring is The semiconductor memory device characterized by having a buried conductor which is formed so as to bury the inner. 2. The semiconductor device according to claim 1, wherein the second wiring and the third wiring have a portion overlapping each other with the second insulating film interposed therebetween, and the second wiring interposed between the second wiring and the third wiring. 2. The semiconductor memory device according to claim 1, wherein the film and the film constitute a capacitive element. 3. The second conductive body is a drain region forming one of the pair of drive transistors, a first drive transistor, and one of the load transistors of the pair of load transistors. A drain region forming a first load transistor having a gate electrode formed of a common first wiring A and the first driving transistor, and a first region forming a gate electrode of the other second driving transistor and a gate electrode of the other second load transistor. A third wiring connected to the first wiring, a contact connected to the drain region of the second driving transistor, and a third wiring connected to the second load transistor. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is in contact with a contact portion connected to said drain region. 4. A semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. A gate electrode of each of the driving transistor, the load transistor, and the transfer transistor is configured by a first conductive film wiring formed of a conductive film, and a buried layer formed in a first insulating film provided on the semiconductor substrate. One of a pair of local wirings cross-connecting between the pair of input / output terminals of the flip-flop circuit is formed by the groove wiring, and a second wiring provided on the first insulating film via a second insulating film.
A semiconductor memory device, wherein the other of the pair of local wirings is constituted by a second conductive wiring formed of a conductive film. 5. The buried groove wiring and the second conductive film, wherein the second conductive film wiring is disposed so as to overlap at least a part of the upper surface of the buried groove wiring via the second insulating film. 5. The semiconductor memory device according to claim 4, wherein a capacitor is formed by the wiring and the second insulating film interposed therebetween. 6. The buried groove wiring and the second conductive film wiring, wherein the second conductive film wiring is disposed so as to cover a part of a side surface of the buried groove wiring via the second insulating film. 6. The semiconductor memory device according to claim 5, wherein a capacitive element is formed by the second insulating film interposed therebetween. 7. The buried trench wiring is a drain region forming a first drive transistor of one of the pair of drive transistors and one of the load transistors of the pair of load transistors. A drain region forming a first load transistor having a gate electrode formed of the first driving transistor and a common first conductive film wiring A, and a gate electrode of the other second driving transistor and the other second load transistor are formed. The second conductive film wiring is disposed so as to be in contact with the first conductive film wiring B, and the second conductive film wiring has a contact portion reaching the first conductive film wiring A, a contact portion reaching the drain region of the second driving transistor, 7. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is in contact with a contact portion reaching a drain region of said second load transistor. 8. The first conductive film wiring B branches between a drain region of the second drive transistor and a drain region of the second load transistor, and the branched wiring portion is connected to the buried trench wiring. The semiconductor memory device according to claim 7, which is in contact with the semiconductor memory device. 9. A contact region between the branched wiring portion and the buried trench wiring is formed in a contact portion reaching the first conductive film wiring A and a drain region of the second drive transistor when viewed from above the substrate. 9. The semiconductor memory device according to claim 8, further comprising a point that is equidistant from both the contact portion that reaches and the contact portion that reaches the drain region of the second load transistor. 10. A semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. A gate electrode of each of the driving transistor, the load transistor, and the transfer transistor is configured by a first conductive film wiring formed of a conductive film, and a buried layer formed in a first insulating film provided on the semiconductor substrate. One of a pair of local wirings cross-coupled between a pair of input / output terminals of the flip-flop circuit is constituted by the trench wiring and the stack electrode provided on the buried trench wiring, and a stack electrode provided on the first insulating film. 2 The second provided via the insulating film
The other of the pair of local wirings is formed of a second conductive film wiring formed of a conductive film, and the second conductive film wiring is formed of at least a part of an upper surface and a part of a side surface of the stack electrode and the second conductive film wiring. A semiconductor memory device arranged so as to overlap with an insulating film interposed therebetween, wherein a capacitive element is formed by the stack electrode, the second conductive film wiring, and the second insulating film interposed therebetween; . 11. A semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors, and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. A gate electrode of each of the driving transistor, the load transistor, and the transfer transistor is configured by a first conductive film wiring formed of a conductive film, and a buried layer formed in a first insulating film provided on the semiconductor substrate. One of a pair of local wires cross-coupled between the pair of input / output terminals of the flip-flop circuit is formed by the groove wire, and is formed in a groove formed in the third insulating film provided on the first insulating film. A second electrode provided on the third insulating film with a second insulating film interposed therebetween, the electrode film being in contact with the buried trench wiring at the bottom thereof.
The in-groove electrode film and the second
The other of the pair of local wirings is constituted by a buried electrode buried via an insulating film, and the buried electrode, the in-groove electrode film, and the second insulating film interposed therebetween have a capacitance element. A semiconductor memory device comprising: 12. A semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of driving transistors and a pair of load transistors, and a pair of transfer transistors, the first memory device being provided on a semiconductor substrate. Each gate electrode of the driving transistor, the load transistor, and the transfer transistor is configured by a first conductive film wiring formed of a conductive film, and is formed in a groove formed in a first insulating film provided on the semiconductor substrate. One of a pair of local wirings cross-coupled between the pair of input / output terminals of the flip-flop circuit by the conductive film in the trench, and a second insulating film is formed on the first insulating film. The second provided through
The in-groove electrode film and the second
The other of the pair of local wirings is constituted by a buried electrode buried via an insulating film, and the buried electrode, the in-groove conductive film, and the second insulating film interposed therebetween have a capacitance element. A semiconductor memory device comprising: 13. A refractory metal silicide layer is formed on a surface of a gate electrode, a source region, and a drain region of each of the pair of drive transistors, the pair of load transistors, and the pair of transfer transistors. 13. The semiconductor memory device according to any one of items 12. 14. A method of manufacturing a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors and a pair of transfer transistors, comprising: Forming an active region for forming a source region and a drain region of each of the drive transistor, the load transistor, and the transfer transistor; and forming respective gate electrodes of the drive transistor, the load transistor, and the transfer transistor. Forming a first conductive film on the semiconductor substrate as a wiring to be formed and then patterning the first conductive film to form a first conductive film wiring; and forming a first conductive film wiring between the pair of input / output terminals of the flip-flop circuit. As one of a pair of cross-coupled local wires, Forming a first insulating film on the semiconductor substrate, forming a buried trench wiring in the first insulating film, and forming the first wiring as the other wiring of the pair of local wirings.
Forming a second conductive film on the insulating film, forming a second conductive film, and patterning the second conductive film to form a second conductive film wiring. Manufacturing method. 15. The buried groove wiring and the second conductive film, wherein the second conductive film wiring is disposed so as to overlap with at least a part of the upper surface of the buried groove wiring via the second insulating film. 15. The method of manufacturing a semiconductor memory device according to claim 14, wherein a capacitance element is formed by the wiring and the second insulating film interposed therebetween. 16. A method for manufacturing a semiconductor memory device having an SRAM in which a memory cell is constituted by a flip-flop circuit having a pair of drive transistors and a pair of load transistors and a pair of transfer transistors, comprising: Forming an active region for forming a source region and a drain region of each of the drive transistor, the load transistor, and the transfer transistor; and forming respective gate electrodes of the drive transistor, the load transistor, and the transfer transistor. Forming a first conductive film on the semiconductor substrate as a wiring to be formed, and then patterning the first conductive film to form a first conductive film wiring; and forming a first conductive film wiring between the pair of input / output terminals of the flip-flop circuit. As one of a pair of cross-coupled local wires, Forming a first insulating film on the semiconductor substrate and then forming a buried trench wiring in the first insulating film; exposing a part of a side surface of the buried trench wiring; A second portion is formed on the exposed portion of the wiring and the first insulating film.
After forming the insulating film, a second conductive film is formed, and the second conductive film is formed on a part of the side surface and the upper surface of the buried trench wiring and the second conductive film.
The second conductive film wiring forming the other of the pair of local wirings is formed by patterning so as to overlap with an insulating film interposed therebetween. Forming a capacitive element composed of a film wiring and the second insulating film interposed therebetween. 17. The buried trench wiring includes a drain region forming one first drive transistor of the pair of drive transistors and one load transistor of the pair of load transistors. A drain region forming a first load transistor having a gate electrode formed of a first conductive film wiring A common to the driving transistor, and a drain region forming a gate electrode of the other second driving transistor and a gate electrode of the other second load transistor. A contact hole reaching the first conductive film line A, a contact hole reaching the drain region of the second drive transistor, After simultaneously forming a contact hole reaching the drain region of the second load transistor, a conductive material is embedded in these contact holes. Method for producing a crowded by forming a semiconductor memory device according to claim 14, 15 or 16, wherein forming in contact with any of the contact portion. 18. The buried trench wiring, wherein the first conductive film wiring B is formed so as to be branched between a drain region of the second drive transistor and a drain region of the second load transistor. 18. The method of manufacturing a semiconductor memory device according to claim 17, wherein the semiconductor device is formed so as to be in contact with the branched wiring portion. 19. A high melting point metal is formed on the surface of the source region and the drain region of each of the pair of drive transistors, the pair of load transistors, and the pair of transfer transistors and the surface of the first conductive film wiring forming the gate electrode. 2. The method according to claim 1, further comprising the step of forming a silicide layer.
19. The method for manufacturing a semiconductor memory device according to any one of 4 to 18.