JP3382005B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device (DRAM) having a memory cell composed of a transistor and a capacitor.
And a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits such as DRAM have been increasingly integrated, and accordingly, the area of capacitors for storing charges (information) has been miniaturized. This reduction in capacitor area reduces the capacitance of the capacitor, which results in erroneous reading of memory contents,
Alternatively, a soft error or the like in which the memory contents are destroyed by α rays or the like becomes a problem.

In order to solve the above problem, a so-called "stacked capacitor structure" in which a MOS capacitor is stacked on a memory cell region has been proposed. In the stacked capacitor structure, the storage node electrode can be expanded over the element isolation region, and by increasing the thickness of the electrode, the side surface of the electrode can also be used three-dimensionally as the capacitor area. It is possible to obtain several times the capacity of the structure.

However, even in such a stacked capacitor structure DRAM, the area occupied by the memory cell is reduced as the element is further miniaturized, so that the effective height of the storage node electrode is increased in order to obtain a sufficient capacitor capacitance. Is required to be high. in this case,
A bit line contact to be formed later must be formed deeply, which makes it difficult to form the contact.

Therefore, a structure has been proposed in which a storage node electrode is provided below the bit line contact and is used as a plug to make the depth of the bit line contact shallow. However, although this structure is effective in the simple stack structure, the following problem is brought about when the cylindrical storage node electrode which can increase the capacitor area is used.

FIG. 10 is a sectional view showing a memory cell structure of a DRAM having a stacked capacitor. A MOS transistor having a source / drain diffusion region 15 and a gate electrode 13 is formed on the Si substrate 10, and a cylindrical storage node electrode 21 (21) is formed on the diffusion region 15.
a, 21b) are formed, and the plate electrode 28 is formed on the surface of the storage electrode 21 with the gate insulating film 27 interposed therebetween. Here, 21b is the original storage node electrode and 21a is the pad electrode for the bit line contact. Then, an interlayer insulating film 31 is deposited on these,
The bit line 33 is formed by providing the bit line contact 39. In addition, 38 is the plate electrode 28 and the bit line 3
It is an insulating film for insulating 3 and.

As shown in this figure, after forming a plate electrode 28 covering the storage node electrode 21 with a capacitor insulating film 27 interposed therebetween, the plate electrode 28 and the capacitor insulating film 27 in the bit line contact portion are selectively removed. If the upper surface of the storage node electrode 21b to be the plug is removed and exposed, it can be electrically connected to the bit line 33, but the contact area is small and the contact resistance increases. Further, since the cylindrical bit line contact pad electrode 21b is used as a plug, the resistance of the bit line contact becomes larger,
There is a problem that the read / write operation is adversely affected.

Further, when the capacitor insulating film 27 is made of, for example, Ta ₂ O ₅ having a larger dielectric constant than the conventional SiN film and SiN / SiO ₂ laminated film, the following problems occur. . That is, when these high dielectric films are used, a metal film such as TiN is required as the plate electrode 28, but these materials are processed with a selection ratio with respect to the storage node electrode 21 (for example, polysilicon). Because it is difficult, as shown in FIG.
The problem is that it becomes difficult to expose the storage node electrode 21b.

[0009]

As described above, in the conventional DRAM having the stacked capacitor memory cell structure, when the cylindrical storage node structure is adopted, it is difficult to form the bit line contact using the storage node electrode as a plug. There was a problem that was.

The present invention has been made in consideration of the above circumstances, and an object thereof is to realize a good bit line contact even in a cylindrical stacked capacitor structure, and to obtain a sufficient capacitor capacity. It is an object of the present invention to provide a semiconductor memory device capable of realizing a low resistance bit line contact and a manufacturing method thereof.

[0011]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention (claim 1) provides a semiconductor memory device in which a memory cell is composed of a capacitor having a storage node which is formed above a substrate surface and has at least an upper portion formed in a tubular shape, and a transistor which functions as a switching element. A bit line contact pad having the same structure as the storage node is formed at the connection portion of the transistor with the bit line, and a conductive material is embedded in the pad.

According to the present invention (claim 2), in the method of manufacturing a semiconductor memory device having the above structure, an MO is formed on a semiconductor substrate.
A step of forming an S transistor, a step of forming a first interlayer insulating film on a substrate on which a MOS transistor is formed, a step of selectively removing the first interlayer insulating film, and a storage node contact and a first bit line. A step of forming a contact, a step of depositing a conductive film on at least a side wall of each contact to form a storage node electrode and a contact pad electrode, and a step of forming a second interlayer insulating film so as to fill each contact. , A step of selectively removing the second interlayer insulating film to form a second bit line contact, a step of filling the second bit line contact with a conductive material, and then the first and second interlayers. The step of removing the insulating film, the step of sequentially laminating the capacitor insulating film and the plate electrode on the surface of each electrode to form a capacitor, and the step of removing the capacitor on the conductive material. Characterized in that it comprises a step of forming a step of exposing the upper portion of the conductor material to remove the film and a plate electrode, a bit line so as to be connected to the conductive material.

The preferred embodiments of the present invention are as follows. (1) The storage node and the bit line contact pad must be formed in a cylindrical shape. (2) The contact point between the conductive material and the bit line is higher than the upper surface of the plate electrode. (3) A third insulating film is formed on the entire surface after the upper portion of the conductive material is exposed, and the surface of this insulating film is at the same height as the upper portion of the conductive material. (4) MOS transistors are connected in series to form a NAND cell.

[0014]

According to the present invention, the plug electrode (bit line contact pad and conductive material) can be formed in the bit line contact region in the same layer as the storage node electrode, so that the plug electrode can be formed even if the storage node height increases. At the same time it gets higher. Therefore, since the bit line contact may be formed on this plug electrode, the bit line contact can be easily formed, and a structure in which there is no risk of short circuit between the plate electrode and the bit line can be realized.

Further, by embedding a conductive material in the bit line contact pad, the plug finally becomes a columnar type, so that the contact resistance with the bit line and the resistance of the plug itself can be reduced. As a result, it becomes possible to realize a sufficient capacitor capacity and a good bit line contact.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 shows a DR according to a first embodiment of the present invention.
It is for explaining the memory cell structure of AM.
Is a plan view and (b) is a cross-sectional view taken along the line AA ′ of (a).

Field insulating film 11 of p-type Si substrate 10
A gate electrode 13 made of polycrystalline silicon is formed in a device region surrounded by a gate insulating film, and silicon nitride films 14 and 16 are formed on the upper and side portions of the gate electrode 13. The substrate surface adjacent to the gate electrode 13 has n
^The source / drain regions 15 formed of the -type diffusion layer are formed, and thereby a MOS transistor is formed.

Source / drain region 15 of transistor
Of these, a cylindrical storage node electrode 21b is formed on the portion to which the capacitor is connected. further,
A bit line contact pad electrode 21a having the same structure as the storage node electrode 21b is formed in a portion to be connected to the bit line. A conductive material 24a is embedded in the bit line contact pad electrode 21a,
The conductive material 24a projects above the upper end of the pad electrode 21a. A plate electrode 28 is formed on the surface of the storage node electrode 21b via a gate insulating film 27.

Then, an interlayer insulating film 31 is formed so as to bury these parts and flatten the surface.
A bit line 33 is formed on the top of the bit line 33 so as to be connected to the conductive material 24a.

In the DRAM cell of this embodiment, a stacked type capacitor is formed under the bit line 33, and a pad electrode 21b for contacting the bit line is formed at the same time when the cylindrical storage node electrode 21b is formed. The pad electrode 21b is filled with a conductive material 24a such as polysilicon to form a plug electrode, and the bit line 33 is electrically connected to the plug electrode at a position higher than the uppermost surface of the plate electrode 28.

As described above, by making a bit line contact with the cylindrical plug electrode having the inside of the cylindrical pad electrode 21a filled with the conductive material 24a, a large contact area can be obtained and the contact resistance can be reduced. Furthermore, the resistance of the plug itself can be reduced. Further, by forming the height of the embedded conductive material upper surface at a position higher than the plate electrode upper surface, it is possible to prevent a short circuit between the bit line 33 and the plate electrode 28.

Next, a method of manufacturing the DRAM cell of this embodiment will be described with reference to FIGS. First, FIG.
As shown in (a), after the field oxide film 11 is formed on the surface of the p-type silicon substrate 10 having a specific resistance of about 5 Ω · cm by a normal LOCOS method, a gate insulating film made of a silicon oxide film of about 10 nm thickness The film 12 is formed. Further, a first polycrystalline silicon film 13 having a thickness of about 150 nm and a silicon nitride film 14 having a thickness of about 150 nm are deposited thereon, and the gate electrode 13 is formed by using the photolithography technique and the RIE technique.

Then, using the gate electrode 13 as a mask, As or P ions are ion-implanted to form the source / drain regions 15 made of n ⁻ type diffusion layers. Further, a silicon nitride film 16 having a film thickness of about 100 nm is deposited on the entire surface, and the entire surface is etched by RIE, so that the sidewall insulating film 16 is self-aligned with the sidewall of the gate electrode 13.
To leave.

Next, as shown in FIG. 2B, after depositing a thin silicon nitride film 17 on the entire surface, a SiO ₂ film or a BPSG film is formed by, for example, 300 n by a CVD method or the like.
The first interlayer insulating film 18 is formed by depositing m to 1000 nm. The thickness of the insulating film 18 determines the height of the capacitor electrode. Then, the insulating film 18 is formed by the RIE method.
Then, the storage node contact 19 and the first bit line contact 20 are simultaneously opened.

Next, as shown in FIG. 2C, a second polycrystalline silicon film 21 is deposited on the entire surface, and doping with P or As is performed. Further, the second interlayer insulating film 22
To flatten the surface. As the interlayer insulating film 22,
Either SiO ₂ or BPSG may be used.

Then, as shown in FIG. 3A, the second bit line contact 23 is again formed in the bit line contact portion.
Is opened, and a third polycrystalline silicon film 24 is deposited so as to fill it.

Next, as shown in FIG. 3B, the third polycrystalline silicon film 24 is entirely etched back to leave the polycrystalline silicon film (conductive material) 24a only inside the contact 23. The polycrystalline silicon film 24a remaining in the contact 23 later becomes a plug of the bit line contact. Here, the polycrystalline silicon film is taken as an example of the conductive material, but a metal such as W, Ti, Al or W
A compound such as Si or TiSi, or a conductive material having a laminated structure may be used.

Next, as shown in FIG. 3C, the second interlayer insulating film 22 is entirely etched back to leave the insulating film 22 in the recess of the storage node contact portion, and the second polycrystalline silicon film. The surface of 21 is exposed. The RIE method may be used for the etch back, or the isotropic etching by the wet method may be used.

Here, as shown in FIG.
Then, the entire surface of the second polycrystalline silicon film 21 is etched back by the method. Then, the polycrystalline silicon 21 is separated on the first interlayer insulating film 18 to form a cylindrical storage node electrode 21b. At this time, the bit line contact pad electrode 21a is simultaneously formed separately.

Next, as shown in FIG. 4B, the first interlayer insulating film 18 is completely removed by wet etching. At this point, the storage node electrode 21b and the plug electrodes (21a, 24a) are completed.

Next, as shown in FIG. 4C, a capacitor insulating film 27 and a fourth polycrystalline silicon film 28 to be a plate electrode are deposited and P or the like is doped. After that, as shown in FIG. 5A, a resist 29 is applied on the entire surface, and then the third bit line contact 30 is opened by photolithography, and CDE (Chemical Dry Etchi) is performed.
ng) etc., the polycrystalline silicon film 2 on the bit line plug 2
At the same time when 8 is removed, a plate electrode is formed.

Next, as shown in FIG. 5B, after depositing a third interlayer insulating film 31, CMP (Chemical Mecha
Etching back is performed until the upper part of the bit line contact plug is exposed by using the nical polishing method or the like, and the surface is flattened to the same height as the bit line plug.

Thereafter, the bit line 33 is formed so as to be electrically connected to the bit line contact plug, whereby the memory cell having the structure shown in FIG. 1 can be obtained. Since the plug electrode can be formed to be the same as or higher than the storage node electrode by the above process, the bit line contact can be formed extremely easily.

In FIG. 3A, the opening to the second interlayer insulating film 22 is formed by the RIE method. However, as shown in FIG. 6, isotropic etching by wet etching is used to form the plug electrode. The surface area of the upper surface can be increased. In FIG. 6, reference numeral 61 is a resist.

(Embodiment 2) FIG. 7 is a sectional view showing a memory cell structure of a DRAM according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The basic structure of this embodiment is the same as that of the first embodiment, but in this embodiment, as shown in FIG. 7, the plate electrode 71 is processed and opened by RIE on the plug electrode to insulate it. By forming the film 72 on the side wall of the bit line contact, insulation between the plate electrode 71 and the bit line 33 is maintained.

According to the structure of this embodiment, the plate electrode 7
In addition, even if a material such as a metal material that cannot provide a processing selection ratio with respect to polycrystalline silicon is used, a good bit line contact can be formed.

(Embodiment 3) FIGS. 8A and 8B are for explaining a memory cell structure of a DRAM according to a third embodiment of the present invention. FIG. 8A is a plan view and FIG. View A-
It is an A'cross section figure. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The basic structure of this embodiment is similar to that of the first embodiment, but in this embodiment, as shown in FIG. 8, a plurality of transistors and stacked capacitors are connected in series to form a NAND type memory cell. I am configuring.

Of course, even with such a structure, the same effect as that of the first embodiment can be obtained. (Embodiment 4) FIG. 9 shows the D according to the fourth embodiment of the present invention.
It is sectional drawing which shows the memory cell structure of RAM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the above-described embodiments, a method of leaving the polycrystalline silicon film on the inner wall of the contact hole is shown as a method of manufacturing the cylindrical storage node electrode, but in the present embodiment, the periphery of the cylindrical insulating film is shown. A method of forming a bit line plug when leaving polycrystalline silicon is shown in FIG.

That is, after forming the storage node contact and the bit line contact, the second polycrystalline silicon film 91 is deposited and n-type doping is performed. further,
After depositing the insulating film 92 that becomes the core of the cylindrical capacitor,
The insulating film 92 and the second polycrystalline silicon film 91 are formed into a column (or a rectangular parallelepiped) by photolithography and RIE.
Process into a mold. Here, after depositing the third polycrystalline silicon film 93 on the entire surface and performing n-type doping, the entire surface R
The storage node electrode is completed by leaving the side wall of the third polycrystalline silicon film 93 in a cylindrical shape by IE.

Further, a first interlayer insulating film 94 is deposited,
The bit line contact is opened, and the bit line plug 95 is left inside the bit line contact hole as in the first embodiment. After that, the first interlayer insulating film 94 may be removed and the capacitor insulating film, the plate electrode, etc. may be formed as described above.

The present invention is not limited to the above embodiments. In the embodiment, the storage node has a cylindrical shape, but it is not limited to the cylindrical shape and may be a cylindrical shape. Further, the entire structure does not have to be cylindrical, and the present invention can be applied as long as at least the upper portion is formed in a cylindrical shape. Further, the conditions such as the material and the film thickness of each part can be appropriately changed according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0045]

As described above, according to the present invention, since a conductive material is embedded in the bit line contact pad, a good bit line contact can be realized even in the cylindrical stacked capacitor structure. Therefore, it is possible to realize a bit line contact with sufficient capacitance and low resistance.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a memory cell structure of a DRAM according to a first embodiment.

FIG. 2 is a sectional view showing a manufacturing process of the memory cell according to the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the memory cell in the first embodiment.

FIG. 4 is a sectional view showing a manufacturing process of the memory cell in the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the memory cell in the first embodiment.

FIG. 6 is a cross-sectional view showing a modification of the method for manufacturing the memory cell in the first embodiment.

FIG. 7 is a sectional view showing a memory cell structure of a DRAM according to a second embodiment.

FIG. 8 is a plan view and a cross-sectional view showing a memory cell structure of a DRAM according to a third embodiment.

FIG. 9 is a sectional view showing a memory cell structure of a DRAM according to a fourth embodiment.

FIG. 10 is a sectional view showing a memory cell structure of a conventional DRAM.

FIG. 11 is a cross-sectional view for explaining problems in a conventional DRAM memory cell.

[Explanation of symbols]

10 ... p-type Si substrate 11 ... field insulating film 12 ... gate insulating film 13 ... first polycrystalline silicon film (gate electrode) 15 ... n ^- type diffusion layer (source / drain region) 16 ... sidewall insulating film 18 ... First interlayer insulating film 19 ... Storage node contact 20 ... First bit line contact 21 ... Second polycrystalline silicon film 21a ... Bit line contact pad 22b ... Storage node 22 ... Second interlayer insulating film 23 ... Second Bit line contact 24 ... Third polycrystalline silicon film 24a ... Buried conductive material 27 ... Capacitor insulating film 28 ... Fourth polycrystalline silicon film (plate electrode) 30 ... Third bit line contact 31 ... Third interlayer Insulating film 33 ... Bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-226603 (JP, A) JP-A-3-82155 (JP, A) JP-A-2-76257 (JP, A) JP-A-2- 60162 (JP, A) JP 5-114710 (JP, A) JP 2-23657 (JP, A) JP 7-249689 (JP, A) JP 1-110763 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 27/108

Claims (10)

(57) [Claims] 1. A semiconductor memory device in which a memory cell is composed of a capacitor having a storage node formed above a surface of a substrate and having at least an upper portion formed in a tubular shape, and a transistor functioning as a switching element. the storage node and the top of the same configuration in the connection portion between is formed cylindrical bit line pad contact, at least its bottom within the pad
The semiconductor memory device characterized by electrically conductive material in direct contact with the surface, which are buried. 2. A step of forming a MOS transistor on a semiconductor substrate, a step of forming a first interlayer insulating film on the substrate on which the MOS transistor is formed, and a step of selectively removing the first interlayer insulating film. Forming a storage node contact and a first bit line contact, depositing a conductive film on at least a sidewall of each contact to form a storage node electrode and a contact pad electrode, and filling each contact. A step of forming a second interlayer insulating film, and a step of selectively removing the second interlayer insulating film to form a second bit line contact,
Directly within the second bit line contact, at least on its bottom surface.
Filling the conductive material so as to come into intimate contact , and then the first step
And a step of removing the second interlayer insulating film, a step of sequentially stacking a capacitor insulating film and a plate electrode on the surface of each electrode to form a capacitor, and removing the capacitor insulating film and the plate electrode on the conductive material. the method of manufacturing a semiconductor device which comprises exposing a top of said conductive material, and forming a bit line to be connected to the conductive material and. 3. A semiconductor substrate, a plurality of memory cells arranged in a matrix on the semiconductor substrate, each memory cell including a MOS transistor and a capacitor, and formed on the memory cell and selectively formed. An interlayer insulating film having a plurality of openings; a plurality of plug electrodes respectively formed in the openings of the interlayer insulating film; and each of the MO electrodes through a corresponding one of the plug electrodes.
A plurality of bit lines connected to one of the source / drain regions of the S transistor and a plurality of word lines each serving as a gate electrode of the MOS transistor; and the capacitor formed on the semiconductor substrate, A storage node electrode having a cylindrical portion laminated on one of source / drain regions of the MOS transistor, a capacitor insulating film formed at least on the storage node electrode, and at least the storage node via the capacitor insulating film. A plate electrode formed to face the electrode, wherein the bit line is formed on the interlayer insulating film,
The upper surface of the plug electrode connected to the other of the source / drain regions of the OS transistor is connected to the upper surface of the plug electrode by burying the opening by itself, and the plug electrode is a lower surface conductor formed of the same layer as the storage node electrode. Section and a cylindrical side wall conductor section ,
A semiconductor memory device comprising: an upper surface conductor portion formed on the lower surface conductor portion and in direct contact therewith . 4. The semiconductor memory device according to claim 3, wherein the surface of the upper surface conductor portion is located at a level higher than the height of the storage node electrode. 5. A semiconductor substrate, a plurality of memory cells arranged in a matrix on the semiconductor substrate, each memory cell including a MOS transistor and a capacitor, and a plurality of selectively formed on the memory cell. A plurality of plug electrodes respectively formed in the openings of the interlayer insulating film; and the plurality of plug electrodes respectively formed through the corresponding one of the plug electrodes.
A plurality of bit lines connected to one of the source / drain regions of the S-transistor, and a plurality of word lines each serving as a gate electrode of the MOS transistor, wherein the bit lines are formed on the interlayer insulating film. Formed, said M
The upper surface of the plug electrode connected to the one of the source / drain regions of the OS transistor is connected to the upper surface of the plug electrode by burying the opening by itself, and the capacitor is formed on the semiconductor substrate. A storage node electrode having a cylindrical portion laminated on the other of the drain regions, at least a capacitor insulating film formed on the storage node electrode, and at least the storage node electrode via the capacitor insulating film. Bottom electrodes and side walls of the plug electrodes connected to the bit lines are formed of the same layer as the storage node electrodes, and are filled with a conductive layer that is in direct contact with the storage node electrodes. , and the flop
Bottom of the lug electrode is selectively connected to said one of the source / drain regions of the MOS transistor, the semiconductor memory device, characterized in that the upper surface of the plug electrode is positioned higher than the upper surface of the storage node electrode. 6. The semiconductor memory device according to claim 3, wherein the inside of the plug electrode is filled with a conductor. 7. The cylindrical portion of the storage node electrode
6. The semiconductor memory device according to claim 3, wherein the inside of the semiconductor device is filled with an insulating material. 8. The semiconductor memory device according to claim 3, wherein the upper surface conductor portion of the plug electrode is flush with the surface of the interlayer insulating film. 9. The semiconductor memory device according to claim 3, wherein the capacitor insulating film is formed on a side wall of the plug electrode. 10. A plurality of the transistors are connected in series such that one of the source / drain regions is shared by the adjacent transistors, and the storage node electrode of the capacitor corresponding to each of the transistors is 6. The method according to claim 3, wherein the bit line is connected to a corresponding source / drain region of a transistor, and the bit line is connected to a source / drain region at one end of the transistor connected in series. The semiconductor memory device described.