JP3147163B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a capacitor structure of a memory cell in a dynamic random access memory (hereinafter referred to as "DRAM") and a method of manufacturing the same.

[0002]

2. Description of the Related Art DRAM known as a semiconductor memory device
Is composed of a memory cell array for storing a large amount of information and peripheral circuits for performing input / output with the outside. At present, DRAM has one switch element (transistor)
And a memory cell having one charge storage element (capacitance part).

In recent years, as the density and integration of DRAMs have increased, the size of memory cells has been reduced, and the planar area of capacitors used in capacitor units for storing electric charges has also been reduced. Therefore, in order to secure a sufficient capacitance value of the capacitor, a trench type or stack type three-dimensional capacitor structure is adopted instead of the conventional planar type (planar type). The trench capacitor structure is a structure in which a groove is dug in a silicon substrate and the side wall of the groove is used. On the other hand, the stacked capacitor structure is a structure in which a storage electrode is formed on a silicon substrate and its surface is used. This stacked capacitor has the advantage that the α-ray collection efficiency is small and the soft error resistance is high because the diffusion layer area of the storage electrode is relatively smaller than that of the trench capacitor structure. Therefore, high-density and high-integration D
This stack type capacitor structure is often employed in RAM.

Hereinafter, an example of a stacked capacitor structure and a manufacturing process thereof will be described with reference to FIGS. The memory array section of FIG.
It is a line cross section.

First, as shown in FIG. 14A, an element isolation region 2 made of a silicon oxide film is formed in a predetermined region on a semiconductor substrate 1, and then a gate oxide film is formed by a thermal oxidation method or the like. . A gate electrode 3 is selectively formed on the gate oxide film, and then a diffusion layer 5 is formed by ion implantation to form a transistor. The gate electrode 3
Corresponds to the part of the diffusion layer formation region of the word line 4 (see FIG. 13).

Subsequently, after an insulating film 8 is formed as required, a first interlayer insulating film 6 is formed as a BPSG film (boron phosphorus film).
(Silica-glass film). Thereafter, a bit contact 10 and a bit line 11 are formed, and a second interlayer insulating film 7 is formed thereon. If necessary, an insulating film 9 made of a silicon oxide film is further formed.

Next, as shown in FIG. 14B, a contact hole 12a for the capacitor contact 12 is formed (first capacitor PR (photoresist) step).

Thereafter, as shown in FIG. 14C, a polycrystalline silicon layer 13a doped with impurities is formed. At this time, the capacitance contact 12 is also formed at the same time.

Next, as shown in FIG. 14D, a storage electrode (stack) 13 is patterned by photoetching (a second capacitor PR step). Subsequently, after a capacitor insulating film is formed, a plate electrode is patterned thereon (third capacitor PR step).

[0010]

However, in the above-mentioned prior art, a short circuit between two storage electrodes is likely to occur as the density and the degree of integration of the DRAM are further increased. In particular, the interval between the two storage electrodes is set to 0.
It is remarkable below 3 μm. The occurrence of such a short circuit between the storage electrodes is a serious problem because it lowers the yield in manufacturing and lowers the quality and reliability of the final product.

A high-density and highly integrated DRAM is provided.
In (2), a wiring (upper-layer wiring) for connecting a peripheral circuit in a DRAM to another peripheral circuit is formed over a memory cell array portion for effective use of a plane area. Therefore, it is required that the underlying layer of these wirings be flat.

Further, in order to reduce the manufacturing cost, it is required that the manufacturing process is simple, and in particular, that the number of PR processes is small. This is because the PR process has many ancillary processes before and after, and has the greatest effect as a cost factor.

An object of the present invention is to provide a high-quality and highly reliable semiconductor memory device in which a short circuit between storage electrodes is prevented. Another object of the present invention is to provide a semiconductor device having no step on the surface of a base layer of an upper wiring. Another object of the present invention is to provide a method for manufacturing such a semiconductor memory device by a simple process.

[0014]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a switch element and a charge storage element, comprising the steps of forming a MOS transistor as a switch element on a silicon substrate; Forming a first insulating film, forming predetermined contacts and wirings, and forming a second insulating film having a thickness equal to or greater than the height of the storage electrode on the first insulating film; Forming an engraved portion for forming a plurality of storage electrodes in the second insulating film; forming a first conductive film so as to embed the engraved portion; and forming each storage electrode in the first conductive film. Providing an opening for forming a hole, forming a capacitor insulating film on at least the inner surface of the opening, and then forming a contact hole at the bottom of the opening, and filling the contact hole and the opening. So second The method of manufacturing a semiconductor device, wherein a conductive film formed to have a step of forming a storage electrode related.

The present invention also relates to a method of manufacturing a semiconductor device having a switch element and a charge storage element, comprising the steps of forming a MOS transistor as a switch element on a silicon substrate, and forming a first insulating film on the silicon substrate. To form
Forming a predetermined contact and wiring, forming a second insulating film on the first insulating film, forming a first conductive film having a thickness equal to the height of the storage electrode; Providing an opening for forming each storage electrode in the one conductive film, forming a capacitor insulating film on at least the inner surface of the opening, and then forming a contact hole at the bottom of the opening; A method of manufacturing a semiconductor device, comprising: forming a second conductive film so as to fill the contact hole and the opening to form a storage electrode.

The present invention is also a semiconductor device having a switch element and a charge storage element, wherein a MOS transistor formed as a switch element on a silicon substrate and a predetermined contact hole is formed on the silicon substrate. A first insulating film, a second insulating film having a thickness equal to or greater than a height of the storage electrode formed on the first insulating film, and a plurality of storage electrodes formed on the second insulating film. A first conductive film formed so as to embed the carved portion, and an opening for forming each storage electrode in the first conductive film; A capacitor insulating film formed on the inner surface of the portion, a contact hole formed at the bottom of the opening, and a storage electrode having a second conductive film formed so as to fill the contact hole and the opening. Features That relates to a semiconductor device.

[0017]

Embodiments of the present invention will be described below in detail.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1 to 4 and FIG. 1 to 4 are partial process sectional views of a memory array portion and a peripheral portion. In the drawings, a portion showing the memory array portion is a sectional view taken along line AA of a partial plan view of the memory array portion in FIG.

First, as shown in FIG. 1A, an element isolation region 2 made of a silicon oxide film is formed in a predetermined region on a semiconductor substrate 1, and then a gate oxide film is formed by a thermal oxidation method or the like. . A gate electrode 3 is selectively formed on the gate oxide film, and then a diffusion layer 5 is formed by ion implantation to form a transistor. The gate electrode 3
Corresponds to the part of the diffusion layer formation region of the word line 4 (see FIG. 13).

Subsequently, if necessary, an insulating film 8 made of a silicon oxide film or a silicon nitride film is formed to protect the insulation between the interlayer film and the wiring.
A first interlayer insulating film 6 having a thickness of about nm is formed by BPSG, and flattened by etch back or CMP. After that, a bit contact 10 and a bit line 11 are formed,
After an insulating film 11a made of a silicon oxide film or the like is formed as required for insulating protection between the interlayer film and the bit line, a thick second interlayer insulating film 7 having a thickness of about 700 to 1200 nm is formed on the insulating film 11a. And the like. The thickness of the second interlayer insulating film 7 is equal to or greater than the height of the storage electrode to be formed. After the interlayer insulating film is formed, planarization may be performed by etch back or CMP (chemical mechanical polishing).

Next, as shown in FIGS. 1B and 3A, the second interlayer insulating film in the memory cell array portion forming region is removed by photoetching to have a depth of 5,000 to 5,000.
A carved portion 14 of about 10000A is formed (first capacitor PR step).

Subsequently, if necessary, as shown in FIG. 1C, an insulating film 9 made of a silicon oxide film or the like is formed on the entire surface to protect the insulating property between the storage electrode and the interlayer film.

Next, as shown in FIGS. 1D and 3B, a polycrystalline silicon film 15a doped with impurities for forming a plate electrode is formed on the entire surface.

Subsequently, as shown in FIG. 1E and FIG. 3C, the region (the insulating film 9 in the present embodiment) where the engraved portion in the peripheral portion is not formed by CMP or etch back. The upper layer of impurity-doped polycrystalline silicon film 15a is removed so that the surface can be seen.

Next, as shown in FIGS. 1F and 4A, an opening 16 is formed by photoetching (a second capacitor PR step).

Subsequently, as shown in FIG. 2A, after a capacitor insulating film 17 made of a silicon nitride oxide film or the like is formed, a protective film 17a made of impurity-doped polycrystalline silicon or the like is formed.
To form

Thereafter, as shown in FIG. 2B, a contact hole 18 for a capacity contact is formed in the opening 16 by photoetching (third capacitor PR step). Subsequently, as shown in FIG. 2C, a polycrystalline silicon layer 13a doped with an impurity for forming a storage electrode is formed.
To form At this time, the capacitance contact 12 is also formed at the same time.

Next, as shown in FIG. 2D and FIG. 4B, C
The region (the insulating film 9 in the present embodiment) and the plate electrode 1 where the engraved portion of the peripheral portion is not formed by MP
The upper portion of the impurity-doped polycrystalline silicon layer 13a is removed so that the surface of No. 5 can be seen. Thereby, the storage electrode 1
3 is formed.

Thereafter, as shown in FIG. 2E, an insulating film 19 made of a silicon oxide film or the like is formed on the entire surface, and an upper wiring 20 is formed thereon. FIG. 4C shows a state in which the upper wiring 20 connecting the peripheral circuits is formed so as to extend over the memory cell array portion. In this figure, the insulating film 19 is omitted.

In the present embodiment, even in the capacitor structure in which the distance between the storage electrodes is narrow, the order of the processes is reverse to that of the prior art, that is, after the plate electrode and the capacitor insulating film are formed, they are buried in the openings. Therefore, a short circuit between the storage electrodes is less likely to occur.
Further, since the memory cell array portion and the peripheral portion are flattened, an upper layer wiring can be formed thereon without any problem, and electrical failure hardly occurs even after the wiring is formed. As a result, a high quality and highly reliable semiconductor memory device can be manufactured. In the present embodiment, such a semiconductor memory device can be manufactured without increasing the number of PR steps as compared with the related art.

Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. 5 to 7 are partial process sectional views of the memory array portion and the peripheral portion. In the drawings, the portion showing the memory array portion is a sectional view taken along line AA of the partial plan view of the memory array portion in FIG.

First, as shown in FIG. 5A, an element isolation region 2 made of a silicon oxide film is formed in a predetermined region on a semiconductor substrate 1, and then a gate oxide film is formed by a thermal oxidation method or the like. . A gate electrode 3 is selectively formed on the gate oxide film, and then a diffusion layer 5 is formed by ion implantation to form a transistor. The gate electrode 3
Corresponds to the part of the diffusion layer formation region of the word line 4 (see FIG. 13).

Subsequently, if necessary, an insulating film 8 made of a silicon oxide film, a nitride film or the like is formed.
A first interlayer insulating film 6 of about 700 nm is formed by BPSG or silicon oxide film or the like, and etched back or CM
Flatten with P. Thereafter, a bit contact 10 and a bit line 11 are formed, and if necessary, an insulating film 11 made of a silicon oxide film or the like is formed.
A second interlayer insulating film 7 having a thickness of about 700 nm is formed by BPSG or a silicon oxide film or the like.
Flatten by MP. . If necessary, an insulating film 9 made of a silicon oxide film or the like is further formed.

Next, as shown in FIGS. 5 (b) and 7 (a), a polycrystalline silicon film 15a having an entire surface doped with impurities for forming a plate electrode is formed to a thickness of 500 to 1000 nm.
Formed with a thickness of

Next, as shown in FIGS. 5 (c) and 7 (b), the plate electrode 15 is patterned by photo-etching, and an opening 16 is formed at the same time (first).
Capacitor PR process).

Subsequently, as shown in FIG. 5D, after a capacitor insulating film 17 made of a silicon nitride oxide film or the like is formed, a protective film 17 made of impurity-doped polycrystalline silicon or the like is formed.
a is formed.

Thereafter, as shown in FIG. 5E, a contact hole 18 for a capacity contact is formed in the opening 16 by photoetching (second capacitor PR step). Next, as shown in FIG. 6A, a polycrystalline silicon layer 13a doped with an impurity for forming a storage electrode is formed. At this time, the capacitance contact 12 is also formed at the same time.

Subsequently, as shown in FIG. 6B and FIG. 7C, the surface of the peripheral portion (the insulating film 9 in the present embodiment) and the surface of the plate electrode 15 can be seen by etching back or the like. Then, the upper portion of impurity-doped polycrystalline silicon layer 13a is removed. Thereby, the storage electrode 13 is formed.

Thereafter, an insulating film 19 made of a silicon oxide film or the like is formed on the entire surface, and an upper wiring is formed thereon.

In this embodiment, even in the capacitor structure in which the interval between the storage electrodes is narrow, the order of the processes is reverse to that of the prior art, that is, after the plate electrode and the capacitor insulating film are formed, they are buried in the openings. Therefore, a short circuit between the storage electrodes is less likely to occur.
As a result, a high quality and highly reliable semiconductor memory device can be manufactured. Further, in the present embodiment, since the number of PR steps is smaller than that of the related art, such a semiconductor memory device can be easily manufactured at low cost.

Third Embodiment This embodiment is the same as the second embodiment up to the capacitor forming step shown in FIG.

After forming the capacitor as shown in FIG. 6B, an insulating film 19 thicker than the height of the storage electrode 13 is formed on the entire surface as shown in FIG. 8A.

Subsequently, as shown in FIG. 8B, the surface of the insulating film 19 is flattened by CMP, and then on the flattened insulating film 19, as shown in FIG. The upper wiring 20 is formed.

In this embodiment, an insulating film 19 thicker than the height of the storage electrode 13 is formed on the entire surface and is planarized, so that an upper layer wiring can be formed thereon without any problem. Also, electrical failures are unlikely to occur.

Fourth Embodiment This embodiment is the same as the first embodiment up to the capacitor forming step shown in FIG. Hereinafter, description will be made with reference to FIGS. 9 and 10.

After forming a capacitor as shown in FIG. 9A, a polycrystalline silicon film 13 for a storage electrode is formed on the entire surface, and an organic material such as a resist is formed so that the concave portion of the polycrystalline silicon film 13 is filled. A film 24 is formed.

Thereafter, as shown in FIG. 9B, the surface of the plate electrode 15 is planarized by CMP until the surface thereof is visible, and the organic film remaining in the concave portion is removed to form the storage electrode 13.

Next, as shown in FIG. 9C, a capacitor insulating film 22 is formed on the entire surface including the surface in the carved portion 21.

Next, as shown in FIG. 10A, an impurity-doped polycrystalline silicon layer 23 for forming a plate electrode is formed on the entire surface so as to cover the surface in the engraved portion 21. Then, as shown in FIG. 2), the polycrystalline silicon layer 23 on the peripheral surface is removed by dry etching.

Finally, as shown in FIG. 10C, an insulating film 19 is formed on the entire surface, and after preferably performing a CMP process, an upper wiring 20 is formed thereon.

In this embodiment, since the storage electrode 13 in the first embodiment is engraved into a cylindrical shape and the inner surface thereof is used, a larger storage capacitance can be obtained. Fifth Embodiment This embodiment is the same as the second embodiment up to the capacitor forming step shown in FIG. Hereinafter, FIG.
This will be described with reference to FIG. Note that FIG.
(A) and FIG.6 (b) are the same figures.

After forming the capacitor as shown in FIG. 11A, the engraved portion 21 is formed in the storage electrode 13 by dry etching as shown in FIG. 11B.

Next, as shown in FIG. 11C, a capacitor insulating film 22 is formed on the entire surface including the surface in the engraved portion 21.

Next, as shown in FIG. 12A, an impurity-doped polycrystalline silicon layer 23 for forming a plate electrode is formed on the entire surface so as to cover the surface of the engraved portion 21. Then, as shown in FIG. As shown in ()), the polysilicon layer 23 on the peripheral surface is removed by etch back.

Finally, an insulating film 19 is formed on the entire surface, and an upper wiring 20 is formed thereon. Preferably, FIG.
As shown in (c), after a thick insulating film is formed, a flattening process is performed by CMP, and then an upper wiring is formed.

In this embodiment, since the storage electrode 13 in the second embodiment is engraved into a cylindrical shape and the inner surface thereof is used, a larger storage capacitance can be obtained. Other Embodiments In each of the first to fifth embodiments described above, crystal grains are grown on the side surface of a plate electrode adjacent to a storage electrode via a capacitor insulating film, and the fourth and fifth embodiments are also described. In the above, crystal grains may be grown on the inner wall surface of the engraved portion of the storage electrode to increase the surface area of the storage electrode. Thereby, a capacitor having a large capacitance value per occupied area can be realized.

As the method, for example, Patent No. 25
The invention according to No. 08948 can be used. Specifically, an amorphous silicon film is deposited, and in a state where the surface of the amorphous silicon film is substantially clean, the amorphous silicon film is subjected to a predetermined pressure in a vacuum or in a gas that does not substantially react with the amorphous silicon. A method including a step of forming a polycrystalline film by heating to a temperature to generate a crystal nucleus on the surface of the amorphous silicon film, lowering the temperature, and growing the crystal nucleus can be used. A capacitor insulating film is formed on the granular surface of the polycrystalline film thus formed, and an opposing electrode region is formed thereon.

[0058]

As apparent from the above description, according to the present invention, it is possible to provide a high-quality and highly reliable semiconductor memory device in which a short circuit between storage electrodes is prevented.
Further, it is possible to provide a semiconductor device having no step on the surface of the underlying layer of the upper wiring. Further, such a semiconductor memory device can be manufactured by a simple process.

[Brief description of the drawings]

FIG. 1 is a process partial cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a process partial cross-sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a process partial plan view for explaining the first embodiment of the present invention.

FIG. 4 is a process partial plan view for describing the first embodiment of the present invention.

FIG. 5 is a process partial cross-sectional view for explaining a second embodiment of the present invention.

FIG. 6 is a process partial cross-sectional view for explaining a second embodiment of the present invention.

FIG. 7 is a process partial plan view for describing a second embodiment of the present invention.

FIG. 8 is a process partial cross-sectional view for explaining a third embodiment of the present invention.

FIG. 9 is a process partial cross-sectional view for explaining a fourth embodiment of the present invention.

FIG. 10 is a process partial cross-sectional view for explaining a fourth embodiment of the present invention.

FIG. 11 is a process partial cross-sectional view for explaining a fifth embodiment of the present invention.

FIG. 12 is a process partial cross-sectional view for explaining a fifth embodiment of the present invention.

FIG. 13 is a partial plan view of a memory cell portion of the semiconductor memory device.

FIG. 14 is a process partial cross-sectional view for explaining the conventional method of manufacturing a semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 element isolation region 3 gate electrode 4 word line 5 diffusion layer 6 first interlayer insulating film 7 second interlayer insulating film 8, 9, 19 insulating film 10 bit contact 11 bit line 11a insulating film 12 contact 13 accumulation Electrode (stack) 13a Impurity-introduced polycrystalline silicon film for forming storage electrode 14, 21 Engraved portion 15 Plate electrode 15a, 23 Impurity-introduced polycrystalline silicon film for forming plate electrode 16 Opening 17, 22 Capacitor insulating film 17a Protective film 18 Contact hole 20 Upper wiring 24 Organic film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (9)

(57) [Claims] 1. A method for manufacturing a semiconductor device having a switch element and a charge storage element, comprising: forming a MOS transistor as a switch element on a silicon substrate; and forming a first insulating film on the silicon substrate. Forming a predetermined contact and wiring, and forming a second insulating film having a thickness equal to or greater than the height of the storage electrode on the first insulating film;
Forming a carved portion for forming a plurality of storage electrodes in the second insulating film; forming a first conductive film so as to embed the carved portion; Providing an opening for forming a storage electrode, and forming a capacitor insulating film on at least the surface in the opening,
Manufacturing a semiconductor device, comprising: forming a contact hole at the bottom of the opening; and forming a storage electrode by forming a second conductive film so as to fill the contact hole and the opening. Method. 2. The method according to claim 1, wherein the second conductive film is formed on the entire surface so as to fill the contact hole and the opening.
2. The method according to claim 1, wherein the second conductive film is processed by a chemical mechanical polishing method so that the second conductive film does not remain on the conductive film.
The manufacturing method of the semiconductor device described in the above. Forming a second opening in the second conductive film in the opening after forming the second conductive film so as to fill the contact hole and the opening; 2
Forming a second capacitor insulating film on the surface of the conductive film, and forming a third conductive film on the second capacitor insulating film and the first conductive film. 2. The method for manufacturing a semiconductor device according to claim 1. 4. A method for manufacturing a semiconductor device having a switch element and a charge storage element, comprising: forming a MOS transistor as a switch element on a silicon substrate; and forming a first insulating film on the silicon substrate. Forming a predetermined contact and wiring, forming a second insulating film on the first insulating film, and then forming a first conductive film having a thickness equal to the height of the storage electrode; Providing an opening for forming each storage electrode in the first conductive film, forming a capacitor insulating film on at least a surface in the opening, and then forming a contact hole at the bottom of the opening; A method for manufacturing a semiconductor device, comprising: forming a second conductive film so as to fill the contact hole and the opening to form a storage electrode. 5. The method according to claim 1, wherein the second conductive film is formed on the entire surface so as to fill the contact hole and the opening.
5. The method according to claim 4, wherein an etch-back process is performed so that the second conductive film does not remain on the conductive film. 6. After forming the second conductive film so as to fill the contact hole and the opening, the second conductive film is formed on the entire surface.
5. The method according to claim 4, wherein a third insulating film thicker than the height of the storage electrode is formed, and the third insulating film is planarized by a chemical mechanical polishing method. 7. A step of forming the second conductive film so as to fill the contact hole and the opening, and then forming a second opening in the second conductive film in the opening. 2
Forming a second capacitor insulating film on the surface of the conductive film, and forming a third conductive film on the second capacitor insulating film and the first conductive film. 5. The method for manufacturing a semiconductor device according to item 4. 8. After forming the third conductive film, a third insulating film thicker than the height of the third conductive film from the surface of the second insulating film is formed on the entire surface, and then the third insulating film is formed. 8. The method according to claim 7, wherein the film is planarized by a chemical mechanical polishing method. 9. A semiconductor device having a switching element and a charge storage element, comprising: a MOS transistor formed as a switching element on a silicon substrate; and a first transistor having a predetermined contact hole formed on the silicon substrate. An insulating film, a second insulating film having a thickness equal to or greater than the height of the storage electrode formed on the first insulating film, and a plurality of storage electrodes formed on the second insulating film. An engraved portion is formed, a first conductive film formed to bury the engraved portion, and an opening for forming each storage electrode is provided in the first conductive film, and a surface in the opening is provided. And a contact hole formed at the bottom of the opening, and a storage electrode formed with a second conductive film so as to fill the contact hole and the opening. Semiconductor device .