JPH1079505A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent short-circuit for a connection hole, for connecting a wiring to a source area, and a connection hole, for connecting a wiring to a drain area, even when a MISFET is miniaturized. SOLUTION: After a connection hole 12 which bestrides a source region and a drain region of a MISFET is formed, a TiN film 15 and a W film 16 are accumulated, and they are polished in chemical-mechanical polishing(CMP) method to remove the TiN film 15 and the W film 16 in regions other than the inside of the connection hole 12. Thereby the TiN film 15 and the W film 16 buried in the connection hole 12 are divided into the source area side and the drain area side by a silicon nitride film 7 on a gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a miniaturized MISFET.
(Metal Insulator Semiconductor Field Effect Transi
The present invention relates to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a stor).

[0002]

2. Description of the Related Art In recent years, in the manufacturing process of an LSI manufactured under the design rule of deep submicron, the alignment accuracy of an exposure apparatus is approaching a limit.
When forming a connection hole (contact hole) for connecting a wiring to a source region and a drain region of an FET, it is difficult to secure a margin for mask alignment between the connection hole and the gate electrode.

As a countermeasure, SAC (Self Align Contact) technology, in which a connection hole is formed in a self-aligned manner by using a silicon nitride film having a high selectivity of about 10 to 20 with respect to a silicon oxide film as an etching stopper, attracts attention. Have been.
This is the insulating film (cap insulating film) on the gate electrode
And a sidewall insulating film (sidewall spacer) are formed of a silicon nitride film, and when the silicon oxide film deposited on the gate electrode is etched to form a connection hole, an etching stopper is formed between the cap insulating film and the sidewall spacer. This prevents the gate electrode from being scraped, thereby eliminating the need for a margin for aligning the gate electrode and the connection hole.

The SAC technique using a silicon nitride film is described in Japanese Patent Application Laid-Open No. 4-342164.

[0005]

However, MISFETs
With further miniaturization, the connection hole for connecting the wiring to the source region and the connection hole for connecting the wiring to the drain region become extremely close to each other, and in some cases, these connection holes are short-circuited. The problem of doing so occurs.

[0006] The SAC technology is a miniaturized MISFE.
This technology eliminates the need for a margin for aligning the gate electrode and the connection hole by preventing the gate electrode of T from being scraped.
In the SRAM described in the above publication, gate electrodes of six MISFETs constituting a memory cell, a pair of local wirings,
Each of a power supply wiring (power supply voltage line and reference voltage line) and a data line are formed in different conductive layers. Therefore, the mask alignment margin when forming the connection hole in the interlayer insulating film using the photoresist as a mask increases, and the memory cell size increases. For example, when the gate electrode is formed of the first conductive film, the local wiring is formed of the second conductive film, and the power wiring is formed of the third conductive film, the power wiring is formed of MISF.
When forming a connection hole connecting to the semiconductor region of the ET,
It is necessary to secure a margin for both the gate electrode and the local wiring.

Further, the SRAM described in the above publication is
A pair of local wirings are formed of the same conductive film. Therefore, a space for arranging two local wirings side by side in the memory cell is required, and the memory cell size increases accordingly.

An object of the present invention is to prevent a short circuit between a connection hole for connecting a wiring to a source region and a connection hole for connecting a wiring to a drain region even when a MISFET is miniaturized. Is to provide.

Another object of the present invention is to provide a complete CMOS type SR.
An object of the present invention is to provide a technique for improving the α-ray soft error resistance of AM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device having a MISFET according to the present invention comprises the steps of (a) forming a semiconductor integrated circuit device on a semiconductor substrate;
After depositing a gate electrode material of an ISFET, and then depositing a first insulating film on the gate electrode material,
Forming a gate electrode by etching an insulating film and the gate electrode material; (b) ion-implanting impurities into the semiconductor substrate to form a source region of the MISFET;
Forming a sidewall spacer made of the first insulating film on a side wall of the gate electrode after forming the drain region or prior to forming the source region and the drain region; and (c) on the semiconductor substrate. The first
Depositing a second insulating film having an etching rate different from that of the insulating film, planarizing the second insulating film, and exposing the first insulating film on the gate electrode; (d)
Forming a first connection hole extending from the source region to the drain region by etching the second insulating film; and (e) depositing a first conductive film on the semiconductor substrate and then forming the first connection hole. Removing the first conductive film in a region other than the inside and exposing the first insulating film on the gate electrode, thereby forming the first conductive film on the source region and the upper region on the drain region. And separating the first conductive film from the first conductive film via the first insulating film above the gate electrode.

(2) A method of manufacturing a semiconductor integrated circuit device having an SRAM according to the present invention comprises the steps of: (a) forming a drive MISFET, a load MISFET, and a transfer MISFET on a semiconductor substrate;
Depositing a gate electrode material of the FET, and then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode; (b) The driving MISFET and the load MI are implanted by ion-implanting impurities into the semiconductor substrate.
After forming the source region and the drain region of the SFET and the transfer MISFET, or prior to the step of forming the source region and the drain region, a sidewall spacer made of the first insulating film is formed on a side wall of the gate electrode. And (c) etching the first insulating film and the sidewall spacer in a region electrically connecting the local wiring formed in the subsequent step and the gate electrode to expose a part of the gate electrode. And (d) depositing a second insulating film having a different etching rate from the first insulating film on the semiconductor substrate, planarizing the second insulating film, and forming the first insulating film on the gate electrode. Exposing the insulating film; and (e) etching the second insulating film to remove the source and drain regions of one driving MISFET from the other. A source region of use MISFET, a first connecting hole across the drain region, MIS for one load
From the source region and the drain region of the FET to the other load M
The second spans the source and drain regions of the ISFET.
Forming a connection hole, and (f) depositing a first conductive film on the semiconductor substrate, and then forming the first connection hole and the second
By removing the first conductive film in a region other than the inside of the connection hole and exposing the first insulating film on the gate electrode, the first conductive film on the source region of each of the pair of driving MISFETs is exposed. A first conductive film and the first conductive film above the drain region are separated from each other via the first insulating film above the gate electrode, and a first conductive film above the source region of the pair of load MISFETs is separated from each other. Separating the first conductive film and the first conductive film above the drain region via the first insulating film above the gate electrode.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In this embodiment, a CMO composed of one n-channel MISFET Qn and one p-channel MISFET Qp as shown in FIG.
This is applied to a method for manufacturing an S inverter.

First, FIG. 2 (a plan view of a CMOS inverter) and FIG. 3 (a) are cross-sectional views along the line AA 'in FIG. 2, and (b) is a cross-sectional view along the line BB' in FIG. As shown in (), an element isolation groove 2 is formed around an active region AR (element isolation region) of a semiconductor substrate 1 made of p ⁻ -type single crystal silicon. The element isolation groove 2 is formed by etching the semiconductor substrate 1 in the element isolation region to form a groove, burying an insulating film such as silicon oxide therein, and then etching back the surface of the insulating film (or chemical mechanical polishing). (CMP) method. Then, the n-channel type MISFET Q
A p-type impurity (B) is ion-implanted into the substrate of the active region AR where n is to be formed to form a p-type well 3, and the substrate of the active region AR where the p-channel MISFET Qp is to be formed is n-type.
An n-type well 4 is formed by ion-implanting a type impurity (P or As).

Next, as shown in FIGS. 4 and 5, after a gate oxide film 6 is formed on the substrate surface of the active region AR, a gate electrode 8 common to the n-channel MISFET Qn and the p-channel MISFET Qp is formed thereon. To form To form the gate electrode 8, for example, C
After a polycrystalline silicon film, a W (tungsten) silicide film, and a silicon nitride film (cap insulating film) 7 are sequentially deposited by the VD method, these films are patterned using a photoresist as a mask.

Next, as shown in FIG. 6, a p-type impurity (B) is ion-implanted into the n-type
The p-type semiconductor region 5 (source region, drain region) of the ISFET Qp is formed. Further, an n-type impurity (P) is ion-implanted into a p-type well 3 not shown in the figure to form an n-type semiconductor region (source region, drain region) of the n-channel MISFET Qn. Then, the gate electrode 8
Side wall spacers 9 are formed on the side walls. The sidewall spacer 9 is formed by processing a silicon nitride film deposited by a CVD method by a reactive ion etching (RIE) method. The cap insulating film on the gate electrode 8 and the sidewall spacer on the side wall are made of an insulating material other than the silicon nitride film (for example, alumina) as long as the insulating material is not easily etched when etching the silicon oxide film. You can also.

Next, as shown in FIG. 7, in a later step, the silicon nitride film 7 covering the gate electrode 8 in the region to which the input line is connected and the sidewall spacer 9 on the side wall are removed by etching. The gate electrode 8 is exposed.

Next, as shown in FIG. 8, after a thin silicon nitride film 10 and a thick silicon oxide film 11 are deposited on the semiconductor substrate 1 by the CVD method, the silicon oxide film 11 is subjected to chemical mechanical polishing (CMP). The surface is flattened by polishing. Polishing of the silicon oxide film 11 is performed until the silicon nitride film 10 on the gate electrode 8 is exposed.

Next, as shown in FIGS. 9 and 10, p
A silicon oxide film 11 and a silicon nitride film on the source region and the drain region of the channel MISFET Qp, on the source region and the drain region of the n-channel MISFET Qn, and on the gate electrode 8 in the region to which the input line is connected in a later step. The connection hole 12 extending from the source region to the drain region of the p-channel MISFET Qp by etching the film 10 and the n-channel MISFET Qp.
n connection hole 1 extending from the source region to the drain region
3. Connection hole 1 for connecting gate electrode 8 and input line
4 is formed.

The etching of the silicon oxide film 11 is performed under the condition that the silicon nitride films (the silicon nitride films 10 and 7 and the sidewall spacers 9) are hardly etched, and the etching of the silicon nitride film 10 is performed by the silicon oxide film (element isolation). The etching is performed under the condition that the silicon oxide film embedded in the groove 2 is hardly etched.

As a result, the silicon nitride film 7 covering the gate electrodes 8 inside the connection holes 12 and 13 and the sidewall spacers 9 on the side walls are hardly etched, so that the height of the silicon nitride film 7 and the height of the connection holes 12 and 13 are reduced. The height of the silicon oxide film 11 in the region other than 14 becomes substantially equal. On the other hand, the surface of the gate electrode 8 inside the connection hole 14 is exposed because the silicon nitride film 7 and the sidewall spacer 9 have been removed in advance.

Also, since the silicon oxide film buried in the element isolation trench 2 is hardly etched, the connection hole 1
Even when misalignment of the source and drain regions 2 and 13 occurs, there is no short circuit between the source and drain regions and the semiconductor substrate 1 (p-type well 3 or n-type well 4).

Next, as shown in FIG.
After depositing a TiN film 15 and a W film 16 thereon by a CVD method or a sputtering method, the TiN film 15 and the W film 16 are polished by a chemical mechanical polishing (CMP) method to form connection holes 12 and 14 (and a connection hole 13 not shown in the drawing). The TiN film 15 and the W film 16 in the regions other than the inside of () are removed. At this time, the connection hole 1
Silicon nitride film 7 covering gate electrode 8 inside 2, 13
And the height of the silicon oxide film 11 in regions other than the connection holes 12, 13, and 14 are substantially equal.
The surface of the silicon nitride film 7 inside and the connection holes 12, 13,
The surface of the silicon oxide film 11 in a region other than 14 is exposed almost simultaneously. As a result, the TiN film 15 and the W film 16 embedded in the connection holes 12 and 13 are separated from the source region side and the drain region side by self-alignment (self-alignment) by the silicon nitride film 7 on the gate electrode 8. . The conductive material embedded in the connection holes 12, 13, and 14 is not limited to the stacked film of the TiN film 15 and the W film 16, but may be other metal materials or polycrystalline silicon.

Next, as shown in FIG. 12 and FIG.
Sputtering method or C on the silicon oxide film 11
A conductive film (for example, a TiN film) deposited by the VD method is patterned to form an input line (IN) 17 and an output line 18 (OU
T) is formed. Part of the output line 18 (OUT) is electrically connected to one of the source region and drain region of the p-channel MISFET Qp through the connection hole 12, and the other part is connected to the n-channel MISFE through the connection hole 13.
It is electrically connected to one of the source region and the drain region of TQn. A part of the input line (IN) 17 is electrically connected to the gate electrode 8 common to the n-channel MISFET Qn and the p-channel MISFET Qp through the connection hole 14.

Next, as shown in FIGS. 14 and 15,
A silicon nitride film 19 and a silicon oxide film 20 are formed on the input line (IN) 17 and the output line 18 (OUT) by CVD.
After the silicon oxide film 20 and the silicon nitride film 19 are etched, a connection hole 21 is formed in the other upper part of the source region and the drain region of the p-channel MISFET Qp, and the n-channel MISFET
A connection hole 22 is formed above the other of the source and drain regions of Qn.

Next, as shown in FIGS. 16 and 17,
After the plug 23 is embedded in the connection holes 21 and 22,
A power supply voltage (Vcc) line 24 and a reference voltage (Vss) line 25 are formed on the silicon oxide film 20. Connection hole 21,
In order to embed the plug 23 in the inside of the silicon oxide film 20, a TiN film and a W film are deposited on the silicon oxide film 20 by a CVD method or a sputtering method, and the TiN film and the W The film is removed by etch back. Further, the power supply voltage (Vcc) line 24 and the reference voltage (V
To form the ss) line 25, a conductive film (for example, a TiN film, A
After depositing a three-layer film (i. film and TiN film), the conductive film is patterned using a photoresist as a mask.

As a result, the power supply voltage (Vcc) line 24 is electrically connected to the other of the source region and the drain region of the p-channel type MISFET Qp through the connection hole 21 and the connection hole 12. The reference voltage (Vss) line 25 is electrically connected to the other of the source region and the drain region of the n-channel MISFET Qn through the connection hole 13. Through the above steps, the CMOS inverter of the present embodiment is completed.

(Embodiment 2) In the present embodiment, FIG.
This is applied to a method for manufacturing an SRAM memory cell composed of four n-channel MISFETs and two p-channel MISFETs as shown in FIG.

As shown, the memory cell includes a pair of complementary data lines (data line DL, data line / (bar) D).
L) and a pair of drive MISFETs Qd ₁ and Qd ₂ , and a pair of load MISs
FETs Qp ₁ and Qp ₂ and a pair of transfer MISFETs Q
It is composed of t ₁ and Qt ₂ . Among these MISFETs, the driving MISFETs Qd ₁ , Qd ₂ and the transfer M
The ISFETs Qt ₁ and Qt ₂ are of an n-channel type, and the load MISFETs Qp ₁ and Qp ₂ are of a p-channel type. That is, this memory cell has four n-channel MISFETs and two p-channel MISFETs.
And a complete CMOS type using the same.

Six MISFs constituting the memory cell
In the ET, a pair of driving MISFETs Qd ₁ and Qd ₂ and a pair of load MISFETs Qp ₁ and Qp ₂ constitute a flip-flop circuit as an information storage unit that stores 1-bit information. One input / output terminal (accumulation node) of this flip-flop circuit is a transfer MISFET Qt ₁
And the other input / output terminal (accumulation node) is connected to the transfer MISFET Q
The source of t _2, and is electrically connected to one of the drain region.

A data line DL is electrically connected to the other of the source and drain regions of the transfer MISFET Qt ₁ .
The source of the transfer MISFET Qt _2, on the other drain region data line / DL is electrically connected. Also, one end of the flip-flop circuit (MISFET for load)
The source regions of Qp ₁ and Qp ₂ are connected to the power supply voltage (Vcc), and the other end (the source regions of the driving MISFETs Qd ₁ and Qd ₂ ) is connected to the reference voltage (Vss). The power supply voltage (Vcc) is, for example, 3 V, and the reference voltage (Vss) is, for example, 0 V (GND). The input / output terminals of the flip-flop circuit are cross-coupled via a pair of local wirings L ₁ and L ₂ .

To manufacture the SRAM memory cell of the present embodiment, first, as shown in FIG. 19 (a plan view of the memory cell) and FIG. 20 (a cross-sectional view taken along the line CC 'in FIG. 19). After forming the element isolation groove 2 around the active region AR (element isolation region) of the semiconductor substrate 1, the driving MISFET is formed.
Forming a p-type well 3 on the substrate of the active region AR where the Qd ₁ , Qd ₂ and the transfer MISFETs Qt ₁ , Qt ₂ are formed;
Active region A forming load MISFETs Qp ₁ and Qp ₂
An n-type impurity (P or As) is ion-implanted into the R substrate to form an n-type well 4.

Next, after a gate oxide film 6 is formed on the substrate surface of the active region AR, a driving MISFET Q
d ₁ and the load MISFET Qp ₁ , a common gate electrode 8, the drive MISFET Qd ₂ and the load MIS
A common gate electrode 8 in FETQp _2, transfer MISF
A common gate electrode 8 (word line WL) is formed for ETQt ₁ and transfer MISFET Qt ₂ . In order to form the gate electrode 8, for example, a polycrystalline silicon film, a W silicide film, and a silicon nitride film (cap insulating film) 7 are sequentially deposited on the semiconductor substrate 1 by a CVD method, and then these are formed using a photoresist as a mask. Pattern the film.

Next, as shown in FIG.
MIS for driving by ion-implanting n-type impurity (P)
FETQd _1, Qd ₂ (and the transfer MISFETQt _1, Q
An n-type semiconductor region 30 (source region, drain region) at t ₂ ) is formed. Also, an n-type well 4 not shown in FIG.
MIS for load by ion implantation of p-type impurity (B)
The p-type semiconductor regions (source region, drain region) of the FETs Qp ₁ and Qp ₂ are formed.

Next, as shown in FIG.
A sidewall spacer 9 of silicon nitride is formed on the side wall of the MISFETs Qd ₁ and Qd ₂ (and the transfer MISFETs Qt ₁ and Qt ₂ ).
The gate oxide film 6 covering the surfaces of the (source and drain regions) and the gate oxide film 6 covering the surfaces of the p-type semiconductor regions (source and drain regions) of the load MISFETs Qp ₁ and Qp ₂ were removed by etching. Thereafter, a Ti silicide layer 31 is formed on those surfaces. Ti silicide layer 3
To form 1, a Ti film deposited on the semiconductor substrate 1 by a sputtering method is annealed (heat treated) to react with the semiconductor substrate 1, and then the unreacted Ti film is removed by etching.

Next, as shown in FIGS. 22 and 23,
The connection hole 32 is formed by etching a part of the silicon nitride film 7 and the side wall spacer 9 on the gate electrode 8 of the driving MISFET Qd ₂ (load MISFET Qp ₂ ).
To form At the same time, a connection hole 33 is formed by etching each part of the silicon nitride film 7 and the side wall spacer 9 above the gate electrode 8 of the driving MISFET Qd ₁ (load MISFET Qp ₁ ).

Next, as shown in FIG.
After a thin silicon nitride film 10 and a thick silicon oxide film 11 are deposited thereon by the CVD method, the silicon oxide film 11 is polished by a chemical mechanical polishing (CMP) method to flatten its surface. Polishing of the silicon oxide film 11 is performed until the silicon nitride film 10 on the gate electrode 8 is exposed.

Next, as shown in FIGS. 25 and 26,
Each n-type semiconductor region 3 of the driving MISFETs Qd ₁ and Qd ₂
0 (source region, drain region) and the silicon oxide film 11 and the silicon nitride film 1 above the connection hole 32.
MISFET for driving by etching 0
From the n-type semiconductor region 30 of Qd ₁ (source region, drain region) to the n-type semiconductor region 3 of the driving MISFET Qd ₂
0 (source region, drain region) connection hole 34
To form At the same time, the load MISFETs Qp ₁ , Qp ₁
Each p-type semiconductor region of p ₂ (source region, drain region)
Oxide film 1 on the top of connection hole 33 and on connection hole 33
1 and by the silicon film 10 nitride is etched, p-type semiconductor region (source region, drain region) of the load MISFET Qp ₁ load MISFET Qp ₂ from
A connection hole 35 is formed over the p-type semiconductor region (source region, drain region). At the same time, the transfer MIS
Silicon oxide film 1 of the upper portion of the drain region of FETQt ₁
A 1 and a silicon nitride film 10 to form a contact hole 36 by etching, to form the connection hole 37 by etching the silicon oxide film 11 and the silicon nitride film 10 upper part of the drain region of the transfer MISFET Qt ₂ .

The etching of the silicon oxide film 11 is performed under the condition that the silicon nitride films (the silicon nitride films 10 and 7 and the sidewall spacers 9) are hardly etched, and the etching of the silicon nitride film 10 is performed by the silicon oxide film (element isolation). The etching is performed under the condition that the silicon oxide film embedded in the groove 2 is hardly etched.

As a result, the silicon nitride film 7 covering the gate electrode 8 inside the connection holes 34 and 35 and the sidewall spacers 9 on the side walls are hardly etched, so that the height of the silicon nitride film 7 and the portions other than the connection holes 34 and 35 are not etched. The height of the silicon oxide film 11 in the region becomes substantially equal. The surface of the gate electrode 8 inside the connection holes 32 and 33 is exposed because the silicon nitride film 7 and the sidewall spacer 9 have been removed in advance.

On the other hand, since the silicon oxide film buried in the element isolation trench 2 is hardly etched, the driving M
Even when misalignment between the n-type semiconductor regions 30 (source region and drain region) of the ISFETs Qd ₁ and Qd ₂ and the connection holes 34 occurs, the n-type semiconductor region 30 (source region and drain region) and the semiconductor substrate 1 ( There is no short circuit with the p-type well 3). Similarly, load MISFETs Qp ₁ , Qp
Each p-type semiconductor region of p ₂ (source region, drain region)
Even if misalignment between the semiconductor substrate 1 and the connection hole 35 occurs, the p-type semiconductor region (source region, drain region) and the semiconductor substrate 1
(N-type well 4) is not short-circuited.

Next, as shown in FIG.
After depositing the TiN film 15 and the W film 16 thereon by the CVD method or the sputtering method, the TiN film 15 and the W film 16 are polished by a chemical mechanical polishing (CMP) method, and the connection holes 34, 35, 36, and 37 are formed.
Then, the TiN film 15 and the W film 16 in the region other than the inside are removed.

At this time, the height of the silicon nitride film 7 covering the gate electrode 8 inside the connection holes 34 and 35 and the height of the connection holes 34
Since the heights of the silicon oxide film 11 in regions other than the regions 35, 36, and 37 are substantially equal, the surface of the silicon nitride film 7 inside the connection holes 34, 35 and the regions other than the connection holes 34, 35, 36, and 37 are oxidized. The surface of the silicon film 11 is exposed almost simultaneously. Thus, the TiN film 1 embedded in the connection hole 34
5 and W film 16, the source region side and the drain region side of drive MISFET Qd ₁ are separated by self-alignment (self-alignment) via silicon nitride film 7 on gate electrode 8, and the source region of drive MISFET Qd ₂ The side and the drain region side are separated by self-alignment (self-alignment) via the silicon nitride film 7 on the gate electrode 8. Similarly, TiN film 15 and W film 16 is buried in the connection hole 35 is self-aligned (self-align the source region side and drain region side of the load MISFET Qp ₁ via the silicon nitride film 7 on the gate electrode 8 ), The source region side and the drain region side of the load MISFET Qp ₂ are separated by self-alignment (self-alignment) via the silicon nitride film 7 on the gate electrode 8.

Next, as shown in FIGS. 28 and 29,
Local wirings L ₁ and L ₂ are formed on the silicon nitride film 13. The local wirings L ₁ and L ₂ are formed by patterning a TiN film deposited on the semiconductor substrate 1 by a sputtering method or a CVD method by dry etching using a photoresist as a mask. The local wiring L ₁ is connected to the load MISFET Qp ₂ and the drive MISFET Qd through the connection hole 32.
₂ are electrically connected to a gate electrode 8 common to
4 and is electrically connected to the n-type semiconductor region 30 (drain region) of the driving MISFET Qd ₁ through the connection hole 35.
It is electrically connected to the p-type semiconductor region of the load MISFET Qp ₁ (drain region) through. The local wiring L ₂ is connected to the load MISFET Qp through the connection hole 33.
₁ and the driving MISFET Qd ₁ are electrically connected to the gate electrode 8 common to the driving MISFET Qd _1.
N-type semiconductor region 30 (drain region) of SFET Qd ₂
Is electrically connected to the load MIS through the connection hole 35.
P-type semiconductor region FETQp ₂ and (drain region) is electrically connected.

Next, as shown in FIGS. 30 and 31,
A silicon oxide film 3 is formed on the local wirings L ₁ and L ₂ by CVD.
8 is deposited, and the silicon oxide film 38 on the respective n-type semiconductor regions 30 and 30 (source regions) of the driving MISFETs Qd ₁ and Qd ₂ is etched by dry etching using a photoresist as a mask to form connection holes 39. , 39
To form At the same time, the load MISFETs Qp ₁ , Qp ₁
The silicon oxide film 38 above the respective p-type semiconductor regions (source regions) of p ₂ is etched to form connection holes 40, 4.
0 is formed, and the silicon oxide film 38 above the n-type semiconductor region (drain region) of each of the transfer MISFETs Qt ₁ and Qt ₂ is etched to form connection holes 41 and 41.

Next, a conductive film (for example, a TiN film and a W film) is buried in the connection holes 39, 40, 41 to form a plug 42.
Is formed, a power supply voltage (Vcc) line 43, a reference voltage line (Vss) 44, and a pad layer 45 are formed on the silicon oxide film 38. The power supply voltage (Vcc) line 43, the reference voltage line (Vss) 44, and the pad layer 45 were formed by sequentially depositing a TiN film, an Al film, and a TiN film on the oxide film 8 by, for example, a sputtering method, and then using a photoresist as a mask. These films are formed by patterning by dry etching.
The power supply voltage (Vcc) line 43 is electrically connected to each of the p-type semiconductor regions (source regions) of the load MISFETs Qp ₁ and Qp ₂ through the connection holes 40 and 40, and the reference voltage line (Vs
s) 44 is the driving MISF through the connection holes 39, 39.
It is electrically connected to each of the n-type semiconductor regions 30 and 30 (source region) of ETQd ₁ and Qd ₂ . Further, one pad layer 45 is connected to the transfer MISFET through one connection hole 41.
Qt ₁ of n-type semiconductor region and (drain region) is electrically connected to the other pad layer 45 is electrically connected to the n-type semiconductor region of the transfer MISFET Qt ₂ (drain region) through the other connection hole 41 You.

Thereafter, although not shown, the power supply voltage (V
cc) line 43, reference voltage line (Vss) 44 and pad layer 4
After depositing an interlayer insulating film such as silicon oxide on the upper part of 5, the data lines DL and / DL are formed on the upper part. Through the above steps, the SRAM memory cell of the present embodiment is substantially completed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

In the above embodiment, the case where the present invention is applied to the method of manufacturing the memory cell of the CMOS inverter and the SRAM has been described. However, the present invention relates to a miniaturized MISFE.
The present invention can be generally applied to a process of connecting a wiring to a source region and a drain region of T.

[0052]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the manufacturing method of the present invention, the MISFET
Since the conductive film formed in the connection hole on the source region and the conductive film formed in the connection hole on the drain region can be separated in a self-alignment manner by the insulating film on the gate electrode, the MISFET is Even in the case of miniaturization, a short circuit between the source region and the drain region can be reliably prevented.

According to the manufacturing method of the present invention, the MISFET
MISFETs are miniaturized by using the cap insulating film on top of the gate electrode and the sidewall spacers on the side walls as etching stoppers when forming contact holes on the source and drain regions. Even in this case, a short circuit between the gate electrode and the source and drain regions can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a CMOS inverter according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 4 is a plan view showing the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 9 is a plan view showing the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 11 is a sectional view illustrating the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 12 is a plan view showing the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing the method of manufacturing the CMOS inverter according to the first embodiment of the present invention;

FIG. 14 is a plan view illustrating the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 15 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 16 is a plan view showing the method for manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 17 is a sectional view illustrating the method of manufacturing the CMOS inverter according to the first embodiment of the present invention.

FIG. 18 is an equivalent circuit diagram of a memory cell of the SRAM according to the second embodiment of the present invention;

FIG. 19 is a plan view illustrating the method for manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 20 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 21 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 22 is a plan view illustrating the method for manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 23 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 24 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 25 is a plan view illustrating the method for manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 26 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 27 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 28 is a plan view illustrating the method for manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 29 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 30 is a plan view illustrating the method for manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

FIG. 31 is a sectional view illustrating the method of manufacturing the memory cell of the SRAM according to the second embodiment of the present invention

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 n-type well 5 p-type semiconductor region (source region, drain region) 6 gate oxide film 7 silicon nitride film 8 gate electrode 9 sidewall spacer 10 silicon nitride film 11 silicon oxide film DESCRIPTION OF SYMBOLS 12 Connection hole 13 Connection hole 14 Connection hole 15 TiN film 16 W film 17 Input line (IN) 18 Output line (OUT) 19 Silicon nitride film 20 Silicon oxide film 21 Connection hole 22 Connection hole 23 Plug 24 Power supply voltage (Vcc) line 25 Reference voltage (Vss) line 30 n-type semiconductor region (source region, drain region) 31 Ti silicide layer 32 connection hole 33 connection hole 34 connection hole 35 connection hole 36 connection hole 37 connection hole 38 silicon oxide film 39 connection hole 40 connection Hole 41 Connection hole 42 Plug 43 Power supply voltage (Vcc) line 44 Reference voltage (Vss) Line 45 pad layer AR active region DL, / DL data lines L _1, L ₂ local interconnection Qn n-channel type MISFET Qp p-channel type MISFET Qd _1, Qd ₂ driving MISFET Qp _1, Qp ₂ for load MISFET Qt _1, Qt MISFET for transfer ₂ WL word line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/11

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising: (a) forming a MISFET on a semiconductor substrate;
Depositing a gate electrode material of ET and then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode; (b) After forming a source region and a drain region of the MISFET by ion-implanting impurities into the semiconductor substrate, or prior to a step of forming the source region and the drain region, the first insulating film is formed on a sidewall of the gate electrode. (C) depositing a second insulating film having a different etching rate from the first insulating film on the semiconductor substrate,
Flattening the second insulating film and exposing the first insulating film above the gate electrode; and (d) etching the second insulating film to cover the second insulating film from the source region to the drain region. (1) forming a connection hole;
(E) After depositing the first conductive film on the semiconductor substrate, removing the first conductive film in a region other than the inside of the first connection hole and removing the first insulating film on the gate electrode. Exposing the first conductive film above the source region and the first conductive film above the drain region via the first insulating film above the gate electrode. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising: (a) forming a MISFET on a semiconductor substrate;
Depositing a gate electrode material of ET and then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode; (b) After forming a source region and a drain region of the MISFET by ion-implanting impurities into the semiconductor substrate, or prior to a step of forming the source region and the drain region, the first insulating film is formed on a sidewall of the gate electrode. Forming the side wall spacer, and (c) etching the first insulating film and the side wall spacer in a region for electrically connecting the wiring formed in the subsequent step and the gate electrode to form the gate electrode. (D) depositing a second insulating film having an etching rate different from that of the first insulating film on the semiconductor substrate. Thereafter, a step of flattening the second insulating film and exposing the first insulating film on the gate electrode, and (e) etching the second insulating film so that the second insulating film is etched from the source region to the drain region. (F) forming a first connection hole that spans, and a second connection hole that electrically connects a wiring formed in a later step and the gate electrode.
After depositing a first conductive film on the semiconductor substrate, the first conductive film
By removing the first conductive film in a region other than the inside of the connection hole and the second connection hole and exposing the first insulating film on the gate electrode, the first conductive film on the source region is removed. Isolating the conductive film and the first conductive film above the drain region from each other via the first insulating film above the gate electrode. 3. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising: (a) forming a MISFET on a semiconductor substrate;
Depositing a gate electrode material of ET and then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode; (b) After forming a source region and a drain region of the MISFET by ion-implanting impurities into the semiconductor substrate, or prior to a step of forming the source region and the drain region, the first insulating film is formed on a sidewall of the gate electrode. (C) depositing a second insulating film having a different etching rate from the first insulating film on the semiconductor substrate,
Flattening the second insulating film and exposing the first insulating film above the gate electrode; and (d) etching the second insulating film to cover the second insulating film from the source region to the drain region. (1) forming a connection hole;
(E) After depositing the first conductive film on the semiconductor substrate, removing the first conductive film in a region other than the inside of the first connection hole and removing the first insulating film on the gate electrode. Exposing the first conductive film above the source region and the first conductive film above the drain region via the first insulating film above the gate electrode; (f) forming a first wiring on one of the source region and the drain region, and electrically connecting one of the source region and the drain region to the first wiring through the first connection hole; A) forming a second connection hole in the third insulating film on the other of the source region and the drain region after depositing a third insulating film on the first wiring; Forming a second wiring on the film; The method of manufacturing a semiconductor integrated circuit device, which comprises a step, for electrically connecting the other and the second wiring of the source region, the drain region through the connection hole and the first connection hole. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the step (b), the first insulating film is deposited on the semiconductor substrate, and then the first insulating film is formed. After depositing a second insulating film having a different etching rate from the first insulating film on the first insulating film, the second insulating film is planarized and the first insulating film on the gate electrode is exposed. A method of manufacturing a semiconductor integrated circuit device, comprising: 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film is a silicon nitride film, and said second insulating film is a silicon oxide film. A method for manufacturing a semiconductor integrated circuit device. 6. An SR in which a memory cell is constituted by a flip-flop circuit including a pair of driving MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs.
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) MISFET for driving and MI for load on a semiconductor substrate
Depositing the gate electrode material of the SFET and the transfer MISFET, then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode , (B)
The drive MISFET, the load MISFET and the transfer MI
Forming a sidewall spacer made of the first insulating film on a side wall of the gate electrode after forming the source region and the drain region of the SFET or prior to the step of forming the source region and the drain region; (c (D) etching the first insulating film and the sidewall spacer in a region for electrically connecting a local wiring formed in a later step and the gate electrode, to expose a part of the gate electrode; After depositing a second insulating film having a different etching rate from the first insulating film on the semiconductor substrate, planarizing the second insulating film and exposing the first insulating film on the gate electrode. (E) etching the second insulating film to form one driving MISF
From the source and drain regions of the ET to the other driving MI
A first connection hole extending over a source region and a drain region of the SFET, a source region and a drain region of one load MISFET, and a source region of the other load MISFET;
Forming a second connection hole over the drain region;
(F) After depositing a first conductive film on the semiconductor substrate, the first conductive film in a region other than the inside of the first connection hole and the second connection hole is removed, and an upper portion of the gate electrode is removed. By exposing the first insulating film, the first conductive film above the source region and the first conductive film above the drain region of the pair of driving MISFETs are connected to the first conductive film above the gate electrode. The first conductive film above the source region and the first conductive film above the drain region of each of the pair of load MISFETs are separated from each other via the first insulating film. Separating the semiconductor integrated circuit device from each other via the first insulating film. 7. An SR in which a flip-flop circuit including a pair of driving MISFETs and a pair of load MISFETs and a pair of transfer MISFETs constitute a memory cell.
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) MISFET for driving and MI for load on a semiconductor substrate
Depositing the gate electrode material of the SFET and the transfer MISFET, then depositing a first insulating film on the gate electrode material, and then etching the first insulating film and the gate electrode material to form a gate electrode , (B)
The drive MISFET, the load MISFET and the transfer MI
Forming a sidewall spacer made of the first insulating film on a side wall of the gate electrode after forming the source region and the drain region of the SFET or prior to the step of forming the source region and the drain region; (c (D) etching the first insulating film and the sidewall spacer in a region for electrically connecting a local wiring formed in a later step and the gate electrode, to expose a part of the gate electrode; After depositing a second insulating film having a different etching rate from the first insulating film on the semiconductor substrate, planarizing the second insulating film and exposing the first insulating film on the gate electrode. (E) etching the second insulating film to form one driving MISF
From the source and drain regions of the ET to the other driving MI
A first connection hole extending over a source region and a drain region of the SFET, a source region and a drain region of one load MISFET, and a source region of the other load MISFET;
Forming a second connection hole over the drain region;
(F) After depositing a first conductive film on the semiconductor substrate, the first conductive film in a region other than the inside of the first connection hole and the second connection hole is removed, and an upper portion of the gate electrode is removed. By exposing the first insulating film, the first conductive film above the source region and the first conductive film above the drain region of the pair of driving MISFETs are connected to the first conductive film above the gate electrode. The first conductive film above the source region and the first conductive film above the drain region of each of the pair of load MISFETs are separated from each other via the first insulating film. Separating from each other via the first insulating film;
(G) forming a pair of local interconnects cross-coupled between input and output terminals of the flip-flop circuit on the second insulating film; (h) forming a pair of local interconnects on the pair of local interconnects; Forming a wiring for supplying a power supply voltage to one end and a wiring for supplying a reference voltage to the other end of the flip-flop circuit. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein after the step (c), the first insulating film is deposited on the semiconductor substrate, and then the first insulating film is formed.
Depositing a second insulating film having an etching rate different from that of the first insulating film on the insulating film, planarizing the second insulating film, and exposing the first insulating film on the gate electrode And a method for manufacturing a semiconductor integrated circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film. A method for manufacturing a semiconductor integrated circuit device.