JP2877069B2 - Static semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a static semiconductor memory device, and more particularly to a structure of an SRAM memory cell.

[0002]

2. Description of the Related Art As a large-capacity semiconductor memory, a DRAM using one MOS transistor and one capacitor in a unit memory cell is frequently used. Particularly, in an application requiring high-speed operation, an SRAM is used. Is used.

In this SRAM memory cell, generally, 1
A flip-flop circuit formed by cross-connecting a pair of inverters is used. In such an inverter configuration, a CMOS inverter composed of both N-channel and P-channel MOS transistors is used, or a resistance load type inverter in which the P-channel MOS transistor is replaced with a resistance element is used.

[0004] The former CMOS inverter is not suitable for a large-capacity semiconductor memory since six MOS transistors are required per unit memory cell. Therefore,
In order to solve this problem, the P-channel MOS transistor is formed of a thin film transistor on an upper layer of a semiconductor substrate, and the area of the memory cell has been reduced. In a large-capacity memory using this thin-film transistor, the leakage current of the memory cell is controlled by the cut-off characteristics of the thin-film transistor. This is effective for applications that strongly demand.

On the other hand, an SRAM using a resistive load type inverter is a personal computer, an engineering workstation, or the like, and has a high-speed CPU,
It is often used as an application of a cache memory arranged between a low-speed large-capacity DRAM and a main storage device.

As a conventional technique, a resistive load type SRA
FIG. 10 shows an equivalent circuit of the M memory cell, and its operation will be described. As shown in FIG. 10, an N-channel driving MO
N composed of S transistor Q1 and load resistance element R1
The MOS inverter and the NMOS inverter comprising the driving MOS transistor Q2 and the load resistance element R2 are cross-connected to form a flip-flop circuit. The node N of the flip-flop is connected via the transfer MOS transistors Q3 and Q4 sharing the word line WL.
1 and N2 are connected to bit lines BL1 and BL2, respectively.

Further, the wiring of the power supply Vcc is connected to the load resistance elements R1 and R2, and is grounded or grounded (GN).
D) The wiring is connected to the source side of the driving MOS transistors Q1 and Q2.

Next, the structure of a memory cell of a conventional resistive load type SRAM will be described with reference to FIGS. 11 and 12. FIG. FIG. 11A and FIG. 11B show S
FIG. 2 is a plan layout diagram of a memory cell of a RAM. Here, FIG. 11A shows a driving MOS transistor and a transfer MOS transistor unit, and FIG. 11B shows a load resistance unit. FIG. 12 is a diagram of FIG.
FIG. 3 is a cross-sectional view taken along A′-B ′.

As shown in FIG. 12, a field oxide film 102 is formed on the surface of a P-type silicon substrate 101, and a gate insulating film 103 is formed in an element active region on the surface of the silicon substrate 101. . And FIG.
As shown in FIG. 12A and FIG. 12, gate electrodes 104 and 104a of a driving MOS transistor are provided. Similarly, gate electrodes of the transfer MOS transistors, that is, word lines 105 and 105a are formed. Further, N ⁺ diffusion layers 106, 106a, 107 and the like are formed. Here, the word lines 105 and 105a
Are electrically connected to N ⁺ diffusion layers 106 and 106a, respectively. Thus, one set of drive MOS transistors and one set of transfer MOS transistors are configured.

Then, as shown in FIG. 12, a first interlayer insulating film 108 is formed, and a gate electrode contact 109 is formed in a predetermined region of the first interlayer insulating film 108, that is, a region on the gate electrode 104. Similarly, FIG.
As shown in (a), a gate electrode contact 109a is formed on the gate electrode 104a.

Then, as shown in FIGS. 11B and 12, the connection layer 110 in the cell of the load resistance element is electrically connected to the gate electrode 104 of the driving MOS transistor through the gate electrode contact 109. further,
The intra-cell connection layer 110 is connected to the high resistance layer 111, and the high resistance layer 111 is connected to the Vcc wiring layer 112. Similarly, another load resistance element is formed. Here, the Vcc wiring layer 112a is a part of the other load resistance element. Thus, a set of load resistance elements connected to each driving MOS transistor is formed.

Then, a second interlayer insulating film 113 shown in FIG. 12 is formed so as to cover these load resistance elements. A ground wiring 115 connected to the N ⁺ diffusion layer through a ground wiring contact 114 formed on the second interlayer insulating film 113 is formed. Further, a bit line 118 made of aluminum metal is formed on the ground wiring 115 via a third interlayer insulating film 116, and a fourth interlayer insulating film 119 is deposited on the bit line 118. Here, the bit line 118 is a bit line contact 1
17 is connected to the N ⁺ diffusion layer 107. Further, as shown in FIG.
Are formed through the bit line contacts 117a.
As described above, the resistive load type SRAM memory cell is configured.

[0013]

A first problem with such a conventional technique is that it is difficult to cope with the low-voltage operation of the above-mentioned static memory cell as the size of the semiconductor element is reduced. That is.

In order to reduce a soft error, which is a data retention defect due to radiation or the like, the driving capability ratio between the driving MOS transistor and the transfer MOS transistor (cell / cell)
Ratio) is needed. In order to solve such a problem, conventionally, generally, a gate width is adjusted on a pattern layout. However, such a method limits the miniaturization of a semiconductor device.

In addition, the thickness of the gate insulating film has been changed. For changing the gate insulating film,
This is known in Japanese Patent Application Laid-Open No. Sho 60-246553. However, in this method, since the gate oxidation step is performed twice, the yield of the MOS transistor is low, and the film thickness control is difficult. The reason is that the gate insulating film is selectively removed using a resist or the like as a mask in the middle of the two oxidation steps, so that the gate insulating film is susceptible to particle contamination. This is because, if the film is oxidized in two steps, the film thickness control will increase in variation.

Further, a second problem with the conventional technique is that:
When the high-resistance layer 111 is set planarly as in the case of the conventional example, the resistance value tends to fluctuate under the influence of the surrounding electric field.

An object of the present invention is to provide a static semiconductor memory device which solves the above problems, facilitates high integration or high density of memory cells, and further promotes high speed operation.

[0018]

For this purpose, a semiconductor memory device according to the present invention has a static memory cell structure formed on an SOI substrate, and a P-type and an N-type region are formed on a base substrate of the SOI substrate. And different voltages are respectively applied to the P-type and N-type regions, and different backs corresponding to the different voltages are applied to a plurality of insulated gate field effect transistors formed on the SOI layer of the SOI substrate. A gate bias is applied, respectively, to provide a difference in the driving capability of the plurality of insulated gate field effect transistors.

The back gate bias for the transfer MOS transistor of the static memory cell is set to the ground potential, and the back gate bias for the drive MOS transistor is set to the power supply potential.

Here, the base substrate is composed of a semiconductor substrate of one conductivity type containing high concentration impurities and an epitaxial layer of the same conductivity type formed on the surface thereof.

Further, the load resistance element of the flip-flop circuit of the static memory cell is connected to the N-type region of the undersubstrate through an opening reaching the undersubstrate of the SOI substrate, and a sidewall insulating film provided on the side wall of the opening. And the high-resistance layer is formed of S
It is connected to the drain region of an insulated gate field effect transistor formed on the OI layer.

Here, the N-type region of the undersubstrate to which the high-resistance layer is connected is set to have a power supply potential.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 1A and FIG. 1B are plan layout diagrams of an SRAM memory cell of the present invention. Here, FIG.
Set of driving MOS transistor sections and one set of transfer M
FIG. 1B shows an OS transistor section, and FIG. 1B shows a set of load resistance element sections and a set of bit line sections. FIG. 2 shows FIG.
It is sectional drawing in AB described in FIG. In this case, SR
The equivalent circuit of the AM memory cell is the same as that shown in FIG.

As shown in FIG. 2, an N-type epitaxial layer 2 is formed on the surface of an N ⁺ -type silicon substrate 1. And this epitaxial layer 2
P ⁺ diffusion layer 3 is formed in a predetermined region on the surface. An insulator layer 4 is formed on the epitaxial layer 2, and a driving MOS transistor is formed on the SOI layer provided on the insulator layer 4, as shown in FIG. 1A or FIG. . That is, SOI channel region 5, gate insulating film 6, gate electrode 7, and SOIN ⁺ regions 9 and 10 constitute one of a set of driving MOS transistors. Similarly, the other driving MOS transistor is configured. In FIG. 1A, the gate electrode 7a,
SOIN ⁺ regions 9a and 10a are shown.

Similarly, a set of transfer MOS transistors is formed on the SOI layer. This transfer MOS
Word lines 8 and 8a which are gate electrodes of transistors
Are formed on P ⁺ diffusion layers 3 and 3a, respectively, with an insulator layer 4 interposed therebetween, as shown in FIG.

Then, as shown in FIG. 2, the first interlayer insulating film 11 is formed so as to cover the gate electrode 7 or 7a and the word line 8. On the first interlayer insulating film 11, an intra-cell connection layer 12 is formed.
Is the other drive M through the gate electrode contact 13.
Connected to the gate electrode 7a of the OS transistor. Here, the intra-cell connection layer 12 is made of a low-resistance conductive material.

As shown in FIG. 2, predetermined regions of the epitaxial layer 2 and the insulator layer 4 are opened, and a side wall insulating film 14 is formed on a side wall of the opening. further,
A high-resistance layer 15 is formed along the side wall insulating film 14 and is electrically connected to the silicon substrate 1. The high resistance layer 15 is electrically connected to the intra-cell connection layer 12. Further, it is electrically connected to the SOIN ⁺ region 9 of the driving MOS transistor through the intra-cell connection layer 12. As shown in FIG. 1B, another high resistance layer 15a is similarly formed, and is connected to the gate electrode 7 of one driving MOS transistor through the intra-cell connection layer 12a. Thus, a set of load resistance element sections is formed.

Then, as shown in FIG. 2, a second interlayer insulating film 17 is formed so as to cover these load resistance elements. A ground wiring 19 connected to the SOIN ⁺ diffusion layer is formed through a ground wiring contact 18 formed on the second interlayer insulating film 17. Further, a bit line 22 made of aluminum metal is formed on the ground wiring 19 via a third interlayer insulating film 20, and a fourth interlayer insulating film 23 is deposited on the bit line 22. Here, the bit line 22 is connected to the bit line contact 21.
Through to the SOIN ⁺ diffusion layer. FIG.
As shown in (b), the other bit line 22a is also formed on the bit line contact 21a. Thus, the resistive load type SRAM memory cell of the present invention is formed.

Next, a method of manufacturing the SRAM memory cell according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view in the order of the manufacturing steps of the SRAM memory cell.

As shown in FIG. 3A, an N-conductivity type epitaxial layer 2 having a thickness of 1.5 μm is formed on a silicon substrate 1 of N ⁺ conductivity type. Insulator layer 4 and 50 nm-thick SOI layer 5 '
Are formed. Hereinafter, such a substrate is referred to as an SOI substrate. The silicon substrate 1 and the epitaxial layer 2 are the base substrates of the SOI substrate. Here, the SOI layer 5 'is a P-type silicon film.

Next, the resist mask 24 is used as a mask for ion implantation, and boron ions are implanted. Here, the energy of the ion implantation is 50 to 100 keV, and the dose is 10 ¹⁵ ions / cm ² . Then, heat treatment is performed to form P ⁺ diffusion layer 3.

Next, the SOI layer 5 'is processed into a predetermined pattern by a known photolithography technique and a dry etching technique. Then, the patterned S
The entire surface of the OI layer is thermally oxidized at 800 ° C. to form a silicon oxide film having a thickness of 10 nm. Further, after a polysilicon having a thickness of 250 nm is sequentially deposited, pattern processing is performed, and a gate insulating film 6 and a gate electrode 7 are formed as shown in FIG. Here, the polysilicon contains 1 × 10 ²⁰ atoms / cm ² of phosphorus impurities. Then, arsenic ions are implanted into the entire surface. The implantation energy is 30 keV, and the dose is 10 ¹⁵ ions / cm ² .

Then, as shown in FIG.
N ⁺ regions 9 and 10 are formed. Also, an SOI channel region 5 is formed. Thus, one driving MOS transistor is formed in the SOI layer.

Next, 200 pressure is applied to the entire surface by a low pressure CVD method.
1 nm thick silicon oxide film is deposited to form a first interlayer insulating film 1
1 is formed. Then, as shown in FIG. 3C, a gate electrode contact 13 is formed on the gate electrode 7a.

Further, predetermined regions of SOIN ⁺ region 9, insulator layer 4 and epitaxial layer 2 are etched, and base contact 25 reaching the surface of silicon base 1 is formed.
Is opened.

Next, a silicon oxide film having a thickness of 30 nm is deposited on the entire surface by a low pressure CVD method, and an etch back process is performed. Thus, the sidewall insulating film 14 is formed on the inner peripheral sidewall of the base contact 25.

Next, 50 n is applied to the entire surface by low pressure CVD.
An m-thick polysilicon layer is deposited. Then, phosphorus impurities are ion-implanted into the polysilicon layer. here,
The concentration of the phosphorus impurity is set to be about 10 ¹⁴ atoms / cm ³ . Thus, the high resistance layer 15 is formed.

Next, the intra-cell connection layer 12 is formed. The intra-cell connection layer 12 is made of a titanium nitride thin film. Alternatively, the intra-cell connection layer 12 may be composed of the polysilicon layer. In this case, after the polysilicon layer is deposited, vertical ion implantation of a phosphorus impurity is performed and patterning is performed. In this case, almost no ions are implanted into the high resistance layer 15. However, ions are implanted into the intra-cell connection layer 12, and the resistance in this region decreases.

Here, the intra-cell connection layer 12 is connected to the high-resistance layer 15, the SOIN ⁺ region 9 of the driving MOS transistor, and the gate electrode 7a.

Then, as shown in FIG.
A second interlayer film 17 is formed of a silicon oxide film having a thickness of nm. Next, a 150 nm-thick tungsten silicide is deposited and patterned to form a ground wiring 19. Next, a boron and phosphorus-doped silicon oxide film is deposited to a thickness of 400 nm to form a third interlayer insulating film 20. Thereafter, a bit line contact and a bit line are formed, and thereafter, an 800 nm-thick silicon oxynitride film is deposited by a plasma CVD method, and a fourth interlayer insulating film 23 is formed. As described above, the SRAM memory cell of the present invention is completed.

Next, the features and effects of the operation of the memory cell will be described. The operation of the flip-flop circuit of the memory cell, shea ^Li Gong substrate 1 and the epitaxial layer 2 is biased to Vcc potential. Further, the P ⁺ diffusion layer 3 is biased to the GND potential.

Therefore, in the driving MOS transistor formed on the epitaxial layer 2 via the insulator layer 4, the back gate bias effect of the transistor occurs, and the threshold value shifts to the negative side. The shift amount at this time depends on the structural parameters of the MOS transistor on the SOI layer. In particular, it is sensitive to the thicknesses of the gate insulating film 6 and the insulator layer 4. Here, when the power supply voltage is 2 V,
A threshold shift of 0.5V occurred. The shift in the threshold value causes a difference in drive capability between the drive MOS transistor and the transfer MOS transistor, and the cell ratio increases.

The load resistance element is composed of a high-resistance layer 15, which is formed so as to be embedded in an SOI substrate. Then, it is connected to the silicon substrate 1 at the Vcc potential. For this reason, the influence of the surrounding electric field of the high resistance layer is reduced, and the resistance value is stabilized.
Since the Vcc potential is connected to the silicon substrate 1, the power supply potential is also stabilized. This is because the parasitic capacitance of the silicon substrate 1 is large.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIGS. 4A and 4B are plan layout views of the SRAM memory cell of the present invention. Here, FIG. 4A shows one set of a driving MOS transistor part and one set of a transfer MOS transistor part, and FIG. 4B shows one set of a load resistance element part and one set of a bit line part. Show. FIG. 5 is a diagram showing C shown in FIG.
It is a sectional view at -D.

As shown in FIG. 5, an epitaxial layer 2 having a P-type conductivity is formed on the surface of a silicon substrate 1 having a P ⁺ -type conductivity. And this epitaxial layer 2
An N ⁺ diffusion layer 31 is formed in a predetermined region on the surface.
An insulator layer 4 is formed on the epitaxial layer 2,
The SOI layer provided on the insulator layer 4 has a structure shown in FIG.
Alternatively, as shown in FIG. 5, a driving MOS transistor is formed. That is, SOI channel region 5, gate insulating film 6, gate electrode 7, and SOIN ⁺ regions 9 and 10 constitute one of a set of driving MOS transistors. Similarly, the other driving MOS transistor is configured. In FIG. 4A and FIG.
The gate electrode 7a is shown.

Similarly, a set of transfer MOS transistors is formed on the SOI layer. This transfer MOS
Word lines 8 and 8a which are gate electrodes of transistors
Is formed on the epitaxial layer 2 via the insulator layer 4 as shown in FIG.

Then, as shown in FIG. 5, the first interlayer insulating film 11 is formed so as to cover the gate electrode 7 or 7a. An intra-cell connection layer 12 is formed on the first interlayer insulating film 11, and the intra-cell connection layer 12 is connected to the gate electrode 7a of the other driving MOS transistor through the gate electrode contact 13.

As shown in FIG. 5, predetermined regions of the epitaxial layer 2 and the insulator layer 4 are opened, and a side wall insulating film 14 is formed on a side wall of the opening. further,
A high resistance layer 15 is formed along the side wall insulating film 14 and is electrically connected to the intra-cell connection layer 12. And
This intra-cell connection layer 12 is electrically connected to the SOIN ⁺ region 9 of the driving MOS transistor through the SOI active layer contact 16.

Further, on the surface of the opening of the epitaxial layer 2, a base contact N ⁺ region 32 of N-type conductivity is provided.
Is formed and connected to the N ⁺ diffusion layer 31. Then, the high-resistance layer 15 is connected to the base contact N ⁺ region 32.

Then, a second interlayer insulating film 17 is formed so as to cover these load resistance elements. A ground wiring 19 connected to the SOIN ⁺ diffusion layer is formed through a ground wiring contact 18 formed on the second interlayer insulating film 17. Further, a bit line 22 is formed on the ground wiring 19 via a third interlayer insulating film 20, and a fourth interlayer insulating film 23 is deposited on the bit line 22. Here, the bit line 22 is connected to the SOIN through the bit line contact 21 as shown in FIG.
⁺ Connected to the diffusion layer. Also, the other bit line 22
a is similarly formed on the bit line contact 21a. Thus, the resistive load type SRAM memory cell of the present invention is formed.

Next, a method for manufacturing the SRAM memory cell according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a sectional view of the SRAM memory cell in the order of manufacturing steps.

As shown in FIG. 6A, an N-type epitaxial layer 2 having a thickness of 2 μm is formed on a P ⁺ -type silicon substrate 1.
An insulator layer 4 having a thickness of 00 nm and an SOI layer 5 'having a thickness of 80 nm are formed.

Next, the resist mask 33 is used as a mask for ion implantation, and phosphorus ions are implanted. here,
The energy of the ion implantation is 700 keV, and the dose is 10 ¹⁵ ions / cm ² . Then, heat treatment is performed to form N ⁺ diffusion layer 31.

Next, the SOI layer 5 'is processed into a predetermined pattern in the same manner as described with reference to FIG.
As shown in FIG. 7, a gate insulating film 6 and a gate electrode 7 are formed. Further, SOI channel region 5 and SOIN ⁺ regions 9 and 10 are also formed. Then, one driving MOS transistor is formed in the SOI layer.

Next, as shown in FIG. 6C, a first interlayer insulating film 11 is formed. Then, gate electrode contact 13 is formed on gate electrode 7a, and SOI active layer contact 16 is formed in SOIN ⁺ region 9. further,
Predetermined regions of gate electrode 7a, insulator layer 4, epitaxial layer 2 and N ⁺ diffusion layer 31 are etched to form base contact 34. Next, arsenic ion implantation and heat treatment are performed to form a base contact N ⁺ region 32. Here, the base contact N ⁺ region 32 is electrically connected to the N ⁺ diffusion layer 31.

Next, as shown in FIG. 3, a sidewall insulating film 14 is formed on the inner peripheral sidewall of the base contact 34 as shown in FIG. 6D. In addition, the intra-cell connection layer 12 and the high resistance layer 15 are formed.

Then, as shown in FIG. 5, a second interlayer insulating film 17, a ground wiring 19, a third interlayer insulating film 20, a bit line 22, and a fourth interlayer insulating film 23 are formed. As described above, the SRAM memory cell of the present invention is completed.

In the operation of this memory cell, silicon substrate 1 and epitaxial layer 2 are biased to the GND potential. Then, the N ⁺ diffusion layer 31 and the base contact N
⁺ Region 32 is biased to the Vcc potential. Then, a driving MOS transistor is provided on the N ⁺ diffusion layer via the insulator layer 4. Therefore, the same effect as described in the first embodiment is obtained.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIGS. 7A and 7B are plan layout views of the SRAM memory cell of the present invention. Here, FIG. 7A shows one set of a driving MOS transistor part and one set of a transfer MOS transistor part, and FIG. 7B shows one set of a load resistance element part and one set of a bit line part. Show. FIG. 8 is a diagram showing E shown in FIG.
It is a sectional view at -F.

As shown in FIG. 8, an N-type epitaxial layer 2 is formed on the surface of a silicon substrate 1 having an N ⁺ conductivity type. And this epitaxial layer 2
P ⁺ diffusion layer 3 is formed in a predetermined region on the surface. On the epitaxial layer 2, an insulator layer 4 and an SOI layer are provided. Then, as shown in FIG. 7A or FIG. 8, a transfer MOS transistor is formed. That is, the SOI channel region 42, the gate insulating film 6, the word line 8, and the SOIN ⁺ regions 9 and 41 constitute one of a set of transfer MOS transistors. Similarly, the other transfer MOS transistor is formed. These transfer MOS transistors are provided above P ⁺ diffusion layer 3, as shown in FIG. Further, one driving MOS transistor is formed, and in FIG.
I channel region 5, gate insulating film 6, and gate electrode 7
It is shown. Similarly, the other driving MOS transistor is formed.

Then, as shown in FIG. 8, first interlayer insulating film 11 is formed so as to cover gate electrode 7 and word line 8. On the first interlayer insulating film 11, an intra-cell connection layer 12 is formed, and the intra-cell connection layer 12 is connected to the gate electrode 7 of the driving MOS transistor and the SOIN ⁺ region 9 through the common contact 43.

As shown in FIG. 8, the gate electrode 7,
An opening is provided in a predetermined region on the surface of the SOIN ⁺ region 9, the insulator layer 4, the epitaxial layer 2, and the silicon substrate 1, and a side wall insulating film 14 is formed on a side wall of the opening. Further, the high resistance layer 1 is formed along the side wall insulating film 14.
5 are formed and electrically connected to the silicon substrate 1. The high resistance layer 15 is electrically connected to the intra-cell connection layer 12.

Then, a second interlayer insulating film 17 is formed. A ground wiring 19 is formed on the second interlayer insulating film 17, and a third interlayer insulating film 20 is formed on the ground wiring 19. Then, a bit line contact 21 is formed on these interlayer insulating films. Bit line 22 is connected to SOIN ⁺ region 41 through bit line contact 21, and a fourth interlayer insulating film 23 is deposited on bit line 22.

Thus, a resistive load type SRAM memory cell according to the third embodiment of the present invention is formed.

Next, a method of manufacturing the SRAM memory cell according to the third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a sectional view of the SRAM memory cell in the order of manufacturing steps.

As shown in FIG. 9A, an N-type epitaxial layer 2 having a thickness of 1.0 μm is formed on an N ⁺ conductive type silicon substrate 1, and a 40 nm-thick epitaxial layer 2 is formed on the epitaxial layer 2. An insulator layer 4 and a 50 nm-thick SOI layer are formed.

Then, P ⁺ diffusion layer 3 is formed in a predetermined region on the surface of epitaxial layer 2. Next, the SOI layer
In the same manner as described with reference to FIG. 3, processing is performed into a predetermined pattern, and a gate insulating film 6 and a word line 8 are formed as shown in FIG. Also, the SOI channel region 4
2, SOIN ⁺ regions 9 and 41 are also formed. Thus, one transfer MOS transistor is formed in the region of the SOI layer located above P ⁺ diffusion layer 3. Similarly, the SOI channel region 5, the gate insulating film 6, and the gate electrode 7 of the driving MOS transistor are formed.

Next, a first interlayer insulating film 11 is deposited, and a common contact 43 is formed using the resist mask 45 as an etching mask. Further, SOIN ⁺ region 9,
The gate electrode 7, the insulator layer 4, the epitaxial layer 2 and a predetermined region of the silicon substrate 1 are etched, and FIG.
The base contact 46 shown in FIG.

Next, in the same manner as described with reference to FIG.
The sidewall insulating film 14 is formed on the inner peripheral sidewall of the base contact 46. Further, as shown in FIG. 9C, the intra-cell connection layer 12 and the high-resistance layer 15 are formed. This high resistance layer 15 is connected to the silicon substrate 1.

Then, as shown in FIG. 8, the second interlayer insulating film 17, the ground wiring 19, and the third interlayer insulating film 20
Is formed. Then, a bit line contact 21 is formed on the first interlayer insulating film 11, the second interlayer insulating film 17, and the third interlayer insulating film 20. Further, bit line 22 is connected to SOIN ⁺ region 41 through bit line contact 21. Then, a fourth interlayer insulating film 23 is formed. In the third embodiment, the gate electrode 7 and the SOIN ⁺ region 9 are arranged so as to be close to each other. Then, a common contact 43 is formed in the adjacent portion, and the intra-cell connection layer 1 is formed.
2 can be formed very locally. Therefore, the size of the SRAM memory cell can be easily reduced as compared with the first embodiment.

[0071]

According to the static memory cell structure of the present invention, a conductive P-type region and an N-type region are formed on a base substrate of an SOI substrate, and different voltages are respectively applied to the P-type region and the N-type region. You. Different back gate biases corresponding to the different voltages are respectively applied to the plurality of insulated gate field effect transistors formed on the SOI layer of the SOI substrate, and the driving capability of the plurality of insulated gate field effect transistors is Is provided.

As described above, the first structure which is formed by the structure of the present invention in which the SRAM is formed on the SOI substrate,
The effect of this is that the cell ratio increases significantly and easily.

In the memory cell layout, the driving MOS
A ratio of about 2.2 times was obtained by setting the gate width pattern of the transistor and the transfer MOS transistor, and a cell ratio of 4 or more was easily obtained by using the back gate bias effect of the present invention. Can be The reason is that the SOI substrate region in the lower layer of the driving MOS transistor is set to the Vcc potential, and the threshold value is shifted low. For example, when the threshold voltage of the transfer MOS transistor is 0.7 V and the threshold voltage shift of 0.5 V is generated when the power supply voltage Vcc is 2 V, the driving capability ratio becomes about 1.9 times. This is to obtain a cell ratio of about 4 as a whole.

A second effect of the present invention is that the effect of the peripheral electric field of the SOI structure is reduced by forming the load resistance element in a vertical type using a sidewall insulating film in the SOI substrate. . The reason is that the conductor layers at both ends of the load resistance element are arranged at the top and bottom of the opening, and are arranged in a vertical structure in the direction perpendicular to the electric field in the direction of the substrate surface.

A third effect of the present invention is that, in forming a vertical load resistance element, the dimensions can be set without being limited by the thickness of the insulator layer of the SOI substrate. It is. The reason is that when the vertical load resistance element is formed, the side wall insulating film is provided on the outer periphery of the resistance element, so that the material of the outer peripheral portion can be disposed regardless of the insulator or the conductor. That's why.

Further, the static memory cell structure of the present invention enables a semiconductor memory device to have both high integration and low voltage and high speed.

[Brief description of the drawings]

FIG. 1 is a plan view of a memory cell for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the memory cell.

FIG. 3 is a sectional view of the memory cell in a manufacturing process order.

FIG. 4 is a plan view of a memory cell for explaining a second embodiment of the present invention.

FIG. 5 is a sectional view of the memory cell.

FIG. 6 is a sectional view of the memory cell in a manufacturing process order.

FIG. 7 is a plan view of a memory cell for explaining a third embodiment of the present invention.

FIG. 8 is a sectional view of the memory cell.

FIG. 9 is a sectional view of the memory cell in a manufacturing process order.

FIG. 10 is an equivalent circuit diagram of an SRAM memory cell.

FIG. 11 is a plan view of a conventional memory cell.

FIG. 12 is a sectional view of the memory cell.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 epitaxial layer 3, 3a P ⁺ diffusion layer 4 insulator layer 5, 42 SOI channel region 5 'SOI layer 6, 103 gate insulating film 7, 7a, 104 gate electrode 8, 8a, 105, 105a word line 9 , 9a, 10, 10a, 41 SOIN ⁺ region 11, 108 First interlayer insulating film 12, 12a, 110 In-cell connection layer 13, 13a, 109 Gate electrode contact 14 Side wall insulating film 15, 15a, 111 High-resistance layer 16 , 16a SOI active layer contact 17, 113 second interlayer insulating film 18, 114 ground wiring contact 19, 115 ground wiring 20, 116 third interlayer insulating film 21, 21a, 117, 117a bit line contact 22, 22, a, 118, 118a Bit line 23, 119 Fourth interlayer insulating film 24, 33, 45 Dist mask 25, 34, 46 Base contact 31 N ⁺ diffusion layer 32 Base contact N ⁺ region 43 Common contact 44, 44a P ⁺ diffusion layer contact Q1, Q2 Driving MOS transistor Q3, Q4 Transfer MOS transistor R1, R2 Load resistance Element N1, N2 Node BL1, BL2 Bit line WL Word line Vcc Power supply GND Ground potential 101 Silicon substrate 102 Field oxide film 106, 107 N ⁺ region 112, 112a Vcc wiring layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/12 29/786

Claims (5)

(57) [Claims] 1. A static memory cell structure formed on an SOI substrate, wherein a conductive P-type region and an N-type region are formed on a base substrate of the SOI substrate, and the P-type region and the N-type region are formed. Different voltages are respectively applied to the plurality of insulated gate field effect transistors formed on the SOI layer of the SOI substrate, and different back gate biases corresponding to the different voltages are respectively applied to the plurality of insulated gate field effect transistors. Wherein the driving capability of the insulated gate field effect transistor is different. 2. An MO for transferring a static type memory cell.
2. The static semiconductor memory device according to claim 1, wherein said back gate bias for an S transistor is set to a ground potential, and said back gate bias for a driving MOS transistor is set to a power supply potential. . 3. The semiconductor device according to claim 1, wherein said base substrate comprises a semiconductor substrate of one conductivity type containing a high concentration impurity and an epitaxial layer of the same conductivity type formed on a surface thereof. 3. The static semiconductor memory device according to 2. 4. A side wall insulating film provided on a side wall of the opening, wherein the load resistance element of the flip-flop circuit of the static memory cell is connected to the N-type region of the base substrate through the opening reaching the base substrate of the SOI substrate. And a high-resistance layer formed on the SOI layer, wherein the high-resistance layer is connected to a drain region of an insulated gate field-effect transistor formed on the SOI layer. The static semiconductor memory device according to claim 3. 5. The static memory device according to claim 4, wherein an N-type region of said base substrate to which said high-resistance layer is connected is set to a power supply potential.