JP3168617B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a nonvolatile memory transistor having a two-layer gate electrode structure including a floating gate electrode and a control gate electrode, and a single gate electrode structure. And a method of manufacturing a nonvolatile semiconductor memory device for forming the peripheral circuit MOS transistor on the same semiconductor substrate.

[0002]

2. Description of the Related Art In a nonvolatile memory transistor having a two-layer gate electrode structure including a floating gate electrode and a control gate electrode, it is important to increase the capacitive coupling between the two-layer gate electrodes to achieve high performance. It is one.

As an interlayer insulating film between two-layer gate electrodes,
The thermal oxide film of polysilicon constituting the floating gate electrode has been widely used so far. However, in order to increase the capacitive coupling without sacrificing the memory cell area, it is necessary to reduce the thickness of the thermal oxide film. . However, it is difficult to reduce the thickness of the polysilicon oxide film because the current flows more easily and the dielectric strength is lower than that of the thermal oxide film of single crystal silicon.

On the other hand, if the interlayer insulating film can be made of a material having a higher dielectric constant than the oxide film, it is possible to increase the capacitive coupling without reducing the thickness. Therefore, in Japanese Patent Application Laid-Open No. 60-145666 or Japanese Patent Application Laid-Open No. 61-229368, based on the above idea, an interlayer insulating film is constituted by a two-layer film of a thin silicon oxide film and a silicon nitride film having a high dielectric constant. A non-volatile storage device is disclosed. In addition, Tokuhei 2-2310
Japanese Patent Application Publication No. JP-B-Heisei 2-2311 and JP-B-2-2311 disclose a nonvolatile memory device in which a thin silicon oxide film is provided above and below a silicon nitride film to form an interlayer insulating film, and a method of manufacturing the same.

[0005] The method of using a high dielectric constant material for the interlayer insulating film as described above is also advantageous in terms of lowering the manufacturing process temperature.
In the case where a thermal oxide film of polysilicon is used as an interlayer insulating film, high-temperature oxidation of about 1000 ° C. to 1150 ° C. is required to suppress a leak current within an allowable range of data retention characteristics. On the other hand, in the above-mentioned known example, it is shown that if a silicon nitride film formed by a chemical vapor deposition method (CVD method) is used, the temperature of the process can be lowered to about 800 ° C. to 920 ° C. including formation of a thin silicon oxide film. Have been.

On the other hand, a method for forming a nonvolatile memory transistor using a polysilicon oxide film as an interlayer insulating film on the same semiconductor substrate as a MOS transistor for a peripheral circuit having a single gate electrode structure is disclosed in Japanese Unexamined Patent Application Publication No. H10-157,197. These are disclosed in JP-A-61-42171 and JP-A-62-150781, respectively.

In Japanese Patent Application Laid-Open No. 61-42171, a two-layer gate electrode of a memory transistor is formed by using a first conductive layer and a second conductive layer (for example, a polysilicon film). In addition, a manufacturing method is disclosed in which a single gate electrode of a peripheral circuit MOS transistor is formed using the same second conductive layer.

In Japanese Patent Application Laid-Open No. 62-150781, a three-layered conductive layer is used, a first-layer and a second-layer conductive layer are used to form a two-layer gate electrode of a memory transistor. A manufacturing method is disclosed in which a single gate electrode of a peripheral circuit MOS transistor is formed in each of the first and third conductive layers.

In order to operate a non-volatile memory transistor having a two-layer gate electrode structure as a memory cell of a non-volatile memory device, it is necessary to form a peripheral circuit MOS transistor for driving the non-volatile memory transistor on the same semiconductor substrate.

As described above, when an interlayer insulating film of a nonvolatile memory transistor is formed of a polysilicon oxide film, a manufacturing method suitable for the polysilicon oxide film has been disclosed as a known example. However, when an attempt is made to use a high dielectric constant material such as the silicon nitride film described in the related art for at least a part of the interlayer insulating film, the combination of the related arts causes the following problems.

That is, when a high dielectric constant material such as a silicon nitride film is used for the interlayer insulating film, the interlayer insulating film and the gate oxide film of the peripheral circuit MOS transistor must be formed in different steps. The two processes adversely affect each other, so that it is difficult to ensure the reliability of the interlayer insulating film and the gate oxide film.

Specifically, on the substrate in the region where the MOS transistor for the peripheral circuit is to be formed, gate oxidation is performed after removing the high dielectric constant film provided as the interlayer insulating film of the memory transistor. It is said that contamination or damage given to the exposed substrate when removing the dielectric constant film lowers the reliability of the gate oxide film.

That is, when the photoresist is coated only on the silicon nitride film in the memory transistor region and the silicon nitride film in the peripheral circuit MOS transistor portion is removed by dry etching, the etching of the silicon nitride film and the silicon oxide film is performed. Since the rate ratio cannot be sufficiently obtained, the silicon oxide film under the silicon nitride film in the MOS transistor portion for the peripheral circuit is also subjected to dry etching, so that the surface of the silicon substrate under the silicon oxide film may be damaged or the dry etching device may not be used. It is said that heavy metal or the like is introduced into the surface of the silicon substrate underneath, and the surface is contaminated.

The interlayer insulating film in the memory / transistor region is also coated with a photoresist film in the step of removing the silicon nitride film or exposed to a cleaning step before forming a gate oxide film in the peripheral circuit region. Or
There are also problems that a leak current in a low electric field increases and that it is difficult to secure a withstand voltage.

On the other hand, Japanese Patent Application Laid-Open No. 2-84776 discloses a method for solving plasma damage caused by dry etching on a gate insulating film of a MOS transistor in a peripheral circuit portion and an interlayer insulating film of a two-layer gate electrode structure in a memory transistor portion. Discloses the following method for manufacturing a nonvolatile semiconductor memory device.

According to this method, a three-layered interlayer insulating film of a silicon oxide film, a silicon nitride film and a silicon oxide film which is an interlayer insulating film having a two-layer gate electrode structure in a memory transistor portion of a nonvolatile semiconductor memory device is formed. After a silicon nitride film is further formed, the photoresist pattern is partially left in the memory cell portion, and four layers of a silicon nitride film, a silicon oxide film, a silicon nitride film, and a silicon oxide film of the MOS transistor portion of the peripheral circuit portion are formed. Are sequentially etched from the top and the photoresist pattern is removed by asher processing while leaving a lower silicon oxide film on the substrate to a certain extent, so that the silicon oxide film, the silicon nitride film, and the silicon oxide film are Cover with a silicon oxide film on the surface of the silicon substrate surface of the MOS transistor in the peripheral circuit area Te is obtained so as not to be affected by the plasma asher.

[0017]

However, studies by the present inventors have revealed that the production method described in Japanese Patent Application Laid-Open No. 2-84776 further has the following problems.

That is, the problem is that when the fourth silicon nitride film in the memory transistor portion is removed by wet etching with hot phosphoric acid, a silicon oxide film,
An interlayer insulating film of a memory transistor portion including three layers of a silicon nitride film and a silicon oxide film and an MO of a peripheral circuit portion.
This is because the underlying silicon oxide film of the S transistor portion is damaged by the hot phosphoric acid, and the reliability of the nonvolatile semiconductor memory device cannot be improved.

Accordingly, the present invention provides a nonvolatile semiconductor memory device having a two-layer gate electrode structure and a MOS transistor for a peripheral circuit for driving the same on the same semiconductor substrate when developing a nonvolatile semiconductor memory device as described above. The purpose of this study is to use a peripheral circuit when a high-dielectric-constant film material other than a silicon thermal oxide film is used for at least a part of the interlayer insulating film of a memory transistor. It is an object of the present invention to provide a method of manufacturing a nonvolatile semiconductor memory device which can maintain the reliability of a gate oxide film of a MOS transistor at a high level.

Another object of the present invention is as follows.
It is an object of the present invention to provide a method for manufacturing a nonvolatile semiconductor memory device that can maintain both the reliability of an interlayer insulating film of a nonvolatile memory transistor having a two-layer gate electrode structure at a high level.

[0021]

The above object can be achieved by the following solution.

As a first solution, before forming a high dielectric constant interlayer insulating film (6) of a nonvolatile memory transistor having a two-layer gate electrode structure (5, 7), a MOS transistor for a peripheral circuit is formed. The substrate in the region to be formed is sequentially covered with a thermal oxide film (3) of the substrate and a conductive film (for example, a polycrystalline silicon film) (5) formed by chemical vapor deposition (see FIG. 1). ).

Further, as a second solution, an insulating film (6) formed simultaneously with a high dielectric constant interlayer insulating film (6) of a nonvolatile memory transistor having a two-layer gate electrode structure (5, 7) Before selectively removing on the peripheral circuit MOS transistor region, a conductive film (for example, a polycrystalline silicon film) which finally becomes at least a part of a control gate electrode of a nonvolatile memory transistor having a two-layer gate electrode structure
In (7), the surface of the high dielectric constant interlayer insulating film (6) of the nonvolatile memory transistor is covered (FIG. 1).
reference).

[0024]

According to the first solution, when the interlayer insulating film (6) in the peripheral circuit MOS transistor region is removed, the underlying conductive film (5) in the peripheral circuit MOS transistor region is removed.
Acts as a buffer layer against contamination or damage due to etching. Further, even when it is necessary to remove the conductive film (5), the etching selectivity between the conductive film (5) and the underlying thermal oxide film (3) can usually be sufficiently increased. The semiconductor substrate in the peripheral circuit MOS transistor region is not exposed and is not contaminated or damaged. Thus, the reliability of the gate oxide film in the MOS transistor region for the peripheral circuit can be improved, and the original object can be achieved.

According to the second solution, since the surface of the interlayer insulating film (6) of the nonvolatile memory transistor portion is covered with the upper conductive film (7), this interlayer insulating film (6)
Is exposed to an atmosphere for direct application of photoresist or removal of asher, or a subsequent thermal oxidation step (formation of gate oxide film (8) in MOS transistor region for peripheral circuit)
And the influence of the pre-cleaning can be avoided. As a result, the low electric field leakage current and dielectric breakdown resistance of the interlayer insulating film (6) are remarkably improved, and the original object can be achieved.

[0026] Other features and other objects of the present invention are as follows.
This will become apparent from the embodiments described in detail below.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of a manufacturing process using three deposited conductive films as a preferred example of a manufacturing process combining the above two solutions.

Hereinafter, for simplicity, the region on the semiconductor substrate where the non-volatile memory transistor is formed is called a first region, and the region where the peripheral circuit MOS transistor is formed is called a second region.

Hereinafter, the manufacturing process according to the embodiment of FIG. 1 will be described in detail.

FIG. 1A: After a field oxide film 2 for element isolation and a gate oxide film 3 of a memory transistor are formed on a semiconductor substrate 1, a first conductive film 5 of a polycrystalline silicon film is formed. accumulate. The conductive film 5 serves as a floating gate electrode of the memory transistor in the first region, and serves as a protective film on the surface of the semiconductor substrate in the second region as described later.

Thus, prior to the formation of the subsequent interlayer insulating film 6, the conductive film 5 covering the surface of the semiconductor substrate in the second region can be formed of the same conductive film as the floating gate electrode 5.

FIG. 1B: After an interlayer insulating film 6 having a higher dielectric constant than the gate oxide film 3 is formed, a second conductive film 7 (which serves as a control gate electrode of a memory transistor) is formed thereon. A polycrystalline silicon film is formed.

FIG. 1C: The second conductive film 7 and the first conductive film 5 on the second region are sequentially removed by lithography.

When the interlayer insulating film 6 is removed in the second region by etching, the underlying polycrystalline silicon film 5 is
Serves as a buffer layer for preventing the semiconductor surface in the region from being contaminated or damaged.

When removing the interlayer insulating film 6 in the second region by etching, the polycrystalline silicon film 7 in the upper part of the memory cell portion is formed by directly applying a photoresist to the interlayer insulating film 6 in the first region. It acts as a buffer layer so that it is not affected by the atmosphere and pre-cleaning.

When the first conductive film 5 is etched, it is desirable to give the selectivity to the underlying gate oxide film 3 so as to avoid exposing the semiconductor substrate 1. For example, when dry etching is used, the etching selectivity between the polycrystalline silicon film 5 and the silicon oxide film 3 is 50: 1, and when wet is used, the etching selectivity between the polycrystalline silicon film 5 and the silicon oxide film 3 is Further, the semiconductor substrate 1 can be prevented from being exposed.

FIG. 1D: After the surface of the semiconductor substrate in the second region is newly thermally oxidized to form the gate oxide film 8 of the peripheral circuit MOS transistor, the third conductive film 10 (polycrystalline silicon film) is formed. ) Are formed continuously.

FIG. 1E: In the first region, the third conductive film 10 is completely removed, and in the second region, the same third conductive film 10 is processed to form a peripheral circuit MOS transistor. A single-layer gate electrode is formed. In removing the third conductive film 10 in the first region, the oxide film 9 formed on the second conductive film 7 during the thermal oxidation in FIG. 1D is used as a stopper. Subsequently, the second conductive film 7, the interlayer insulating film 6, and the first conductive film 5 are sequentially processed in the first region to form a two-layer gate electrode of the memory transistor. The process continues to the step of forming the drain region.

FIG. 2 is a cross-sectional view of a manufacturing process using two deposited conductive films as another preferred example of the manufacturing process in which the above two solutions are combined.

FIG. 2A: After a field oxide film 2 for element isolation, a gate oxide film 3 of a memory transistor and a gate oxide film 4 of a MOS transistor for a peripheral circuit are formed on a semiconductor substrate 1, Is deposited.

The conductive film 5 has a memory region in the first region.
The second region serves as a protective film on the surface of the semiconductor substrate, as will be described later, while serving as a floating gate electrode of the transistor.

Thus, prior to the formation of the subsequent interlayer insulating film 6, the conductive film 5 covering the surface of the semiconductor substrate in the second region can be formed of the same layer as the floating gate electrode 5.

FIG. 2B: After forming the interlayer insulating film 6,
A second conductive film 7 serving as a control gate electrode of the memory transistor is continuously formed thereon.

FIG. 2C: The second conductive film 7 and the interlayer insulating film 6 on the second region are sequentially removed by lithography.

FIG. 2D: The second conductive film 7, the interlayer insulating film 6, and the first conductive film 5 are sequentially processed in the first region to form a two-layer gate electrode of the memory transistor. At the same time, in the second region, the first conductive film 5 is processed to form the gate electrode of the peripheral circuit MOS transistor. Thereafter, the process proceeds to a normal source / drain region forming process.

FIG. 3 shows another preferred example of the manufacturing process in which the above two solutions are combined, in which a step of reducing the resistance of the gate electrode material is added to the manufacturing process of FIG.

FIGS. 3A, 3B, and 3C show FIGS.
This is exactly the same as each of the steps (A), (B) and (C). After this, the following steps are added.

FIG. 3 (D ′): Third conductive film 10 a electrically integrated with first and second conductive films 5 and 7 (for example, as compared with polycrystalline silicon such as a metal silicide film). A low-resistance conductive film is formed on the entire surface.

FIG. 3E: Third conductive films 10a and 10a
After forming the gate electrode of the peripheral circuit MOS transistor by processing the conductive film 5 of the layer, the conductive film 10a of the third layer, the conductive film 7 of the second layer, the interlayer insulating film 6, and the first layer The two-layer gate electrode of the non-volatile memory transistor is formed by overlapping and cutting the conductive film 5 of FIG. Thereafter, the process proceeds to a normal source / drain region forming process.

FIG. 4 is a cross-sectional view of an integrated circuit device including a nonvolatile memory transistor and a peripheral circuit MOS transistor formed on the same semiconductor substrate by the manufacturing method described in this embodiment.

Although not particularly limited, the integrated circuit device of FIG. 4 is formed on a semiconductor substrate 11 made of single crystal p-type silicon. The n-channel MOS transistor has n-type source and drain regions 29 and 30 formed on the surface of a p-type well region 12 of the same conductivity type as the semiconductor substrate 11, and a thin gate formed on a channel between the source region and the drain region. An oxide film 27 and a gate electrode 28 made of a third conductive film (a tungsten polycide film, that is, a two-layer film of polysilicon and tungsten silicide) are formed.

On the other hand, the p-channel MOS transistor is formed in an n-type well region 13 of a conductivity type opposite to that of the semiconductor substrate 11. P-type source and drain regions 31 and 32 formed on the surface of the n-type well region 13, a thin gate oxide film 27 formed on a channel between the source region and the drain region, and a third conductive film (tungsten polysilicon) The gate electrode 28 is formed of a side film, that is, a two-layer film of polysilicon and tungsten silicide.

Although not particularly limited, the n-channel and p-channel MOS transistors of this embodiment are so-called LDD
(Lightly Doped Drain) structure is used.

The non-volatile memory transistor is, like the n-channel MOS transistor, a p-type well region 12
Is formed on. This non-volatile memory transistor has a gate oxide film (tunnel oxide film) 16 and a floating gate electrode 1 made of a first conductive film (polycrystalline silicon film).
7. Thin silicon oxide films 18 and 20 and silicon nitride film 1
9, a control gate electrode 21 made of a second conductive film (also a polycrystalline silicon film), a source region 24, a drain region 22, and a drain formed before the formation of the sidewall spacer 26. Shield area 2
3 Floating gate electrode 17, interlayer insulating film 1
8, 19, and 20, and the control gate electrode 21 are overlapped and cut in the gate length direction in one lithography process, thereby realizing a stacked two-layer gate electrode structure.

The gate oxide film 16 is formed of a silicon oxide film formed by thermally oxidizing the surface of the semiconductor substrate 11, and has a thickness of about 10 nm.

As described above, the interlayer insulating film is a composite film of a silicon oxide film and a silicon nitride film, and a thermal oxide film 18 having a thickness of about 4 nm is formed on the surface of the polysilicon floating gate electrode 17.
Is formed, and a film thickness of 20 nm is formed by a chemical vapor deposition method.
A thermal oxide film 20 having a thickness of about 4 nm is further formed on the surface of the silicon nitride film 19 of FIG.
8 nm.

The polycrystalline silicon control gate electrode 21 functions to control the potential of the floating gate electrode 17 by the capacitive coupling of the interlayer insulating films 18, 19, 20. The ends of the control gate electrode 21 and the floating gate electrode 17 in the channel length direction are processed by one lithography step as described above, and the gate length is about 1.0 μm. The control gate electrode 21 is integrated with a word line W described later.

Drain region 22 is formed of an n + type semiconductor region, and is connected to data line D formed of aluminum wiring 35 via a contact hole.

A drain shield region 23 is formed of ap + -type semiconductor region so as to surround the drain region 22. The threshold voltage is set in a thermal equilibrium state, the channel hot electron injection efficiency in a write operation described later is improved, And punch-through prevention.

The source region is made of n containing arsenic (As) as an impurity.
It comprises a + type semiconductor region 24 and further forms a source line SL described later.

Reference numeral 14 denotes a field oxide film formed by a LOCOS method for element isolation, 15 denotes a channel stopper for preventing a parasitic channel formed of a p + type semiconductor region, 35 aluminum wiring, and 33 and 34 denote two interlayer layers for the aluminum wiring 35. It is an insulating film. Contact holes are formed on the drain region of the nonvolatile memory transistor, on the source and drain regions of the MOS transistor for the peripheral circuit, and on each gate electrode of the element isolation region (not shown in FIG. 4). I have.

Although omitted in FIG. 4, a P layer formed by a chemical vapor deposition method is formed on the aluminum wiring 35.
A final passivation film made of an SG (phosphorus silicate glass) film and a plasma silicon nitride film thereon is provided.

FIG. 5 is an internal block diagram showing an example of an electrically rewritable nonvolatile semiconductor memory device realized by the manufacturing method of this embodiment.

In the memory array M-ARRAY, one element of the nonvolatile memory transistor structure shown in FIG.
Bits are configured.

An X decoder (XDCR) and a Y decoder (Y
DCR), a high voltage generating circuit (ED) for supplying a high voltage to the source of the non-volatile memory transistor and performing programming, and the like constitute a peripheral circuit of the present invention. This peripheral circuit has a CMOS structure shown in FIG. Be composed.

FIG. 6 is a plan view showing a layout of 4 bits of the memory cell array according to the embodiment of the present invention.

The numbers in FIG. 6 basically correspond to those in FIG. 4, but as a new one, 37 is a LOCOS for element isolation.
The boundary line between the region 14 and the active region, 38 is a data line 35 (D) made of metal wiring and the drain region 22 of the memory cell.
Is a contact hole for connecting. The polysilicon control gate electrode 21 extends in a direction orthogonal to the metal data line 35 (D) to form a word line.

The details of the operation of this nonvolatile semiconductor memory device are basically the same as those described in US Pat. No. 4,698,787, and therefore will not be described here.

In order to explain the flow of the manufacturing process according to the embodiment of the present invention, a detailed description will be given with reference to cross-sectional views and plan views of the manufacturing process shown in FIGS.

As shown in FIG. 7, a p-type well region 12 and an n-type well region 13 are formed on the main surface side of a p-type semiconductor substrate 11 by a normal twin-tub process for CMOS, and further, element isolation is performed by a LOCOS process. A field oxide film 14 and a channel stopper 15 for preventing a parasitic channel formed of a p + type semiconductor region.

Next, the surface of the active region is thermally oxidized to a thickness of 10
After the formation of the gate oxide film 16 of nm,
Polycrystalline silicon film 17 having a thickness of 200 nm, which is a conductive film of
Is deposited by a known chemical vapor deposition method. After doping the polycrystalline silicon film 17 with phosphorus (P), which is an n-type impurity, by a known thermal diffusion method or ion implantation method, as shown in the plan view of FIG. The crystalline silicon film 17 is processed so as to have a shape suitable for finally forming a floating gate electrode. At this time, the polycrystalline silicon film is left as it is in the peripheral circuit MOS transistor region and used as a cover.

Subsequently, a composite film of silicon oxide films 18 and 20 and a nitride film 19 to be an interlayer insulating film of a memory transistor is formed. First, the surface of the polysilicon film 17 is thermally oxidized to form a thin oxide film 18 having a thickness of 4 nm. next,
After a silicon nitride film 19 having a thickness of 20 nm is formed by a known chemical vapor deposition method, the surface is thermally oxidized to form a silicon oxide film 20 having a thickness of 4 nm.

Oxide film 18 / nitride film 19 thus formed
/ Composite interlayer insulating film having a three-layer structure of oxide film 20
A polycrystalline silicon film 21 having a thickness of 300 nm, which is a second conductive film, is formed. The interlayer insulating films 18, 19, and 20 are covered with the polycrystalline silicon film 21 immediately after being formed, and are not exposed thereafter, so that highly reliable interlayer insulating film characteristics can be realized. The polycrystalline silicon film 21 includes
As in the case of the first layer, phosphorus (P), which is an n-type impurity, is doped by a known thermal diffusion method or ion implantation method.

Next, as shown in FIG.
The second polycrystalline silicon film 21, the interlayer insulating films 18, 19, 20 and the first polycrystalline silicon film 17 formed on the S transistor region are sequentially removed by a known dry etching technique.

Although not shown in FIG. 9, the peripheral circuit M
When the interlayer insulating films 18, 19, 20 are etched in the OS transistor region, the substrate surface and the gate oxide film 16 in the peripheral circuit MOS transistor region are completely covered with the first polycrystalline silicon film 17. Also, the first
In the dry etching of the polycrystalline silicon film 17, a sufficiently large etching selectivity (about 30 to 50) with respect to the underlying gate oxide film 16 can be realized. In the process, there is no fear that the substrate surface in the MOS transistor region for the peripheral circuit is exposed or is affected by contamination or damage.

Subsequently, after cleaning the substrate surface in the peripheral circuit MOS transistor region, the peripheral circuit MOS transistor region is thermally oxidized.
An 18-nm-thick gate oxide film 27 for a transistor is formed. At this time, an oxide film 27 'having a thickness of about 60 nm is simultaneously formed on the surface of the second polycrystalline silicon film 21 in the memory transistor portion.

After that, a tungsten polycide film 28 as a third conductive film is formed. As a procedure for forming the tungsten polycide film 28, first, a polycrystalline silicon film having a thickness of 150 nm is formed, and a phosphorus, which is an n-type impurity, is formed thereon by a known thermal diffusion method or ion implantation method.
(P) is doped to a concentration of about 5 × 10 ²⁰ / cm ³ . Subsequently, the thickness of 150 n is formed by a known chemical vapor deposition method.
The tungsten silicide film 28 is formed directly on the above-mentioned polycrystalline silicon film to obtain an electrically integrated tungsten polycide film 28.

Next, as shown in FIG. 10, the tungsten polycide film 28 as the third conductive film is removed on the memory transistor region. On the other hand, the same film is left as it is on the peripheral circuit MOS transistor region. At this time, in order to prevent the tungsten polycide film 28 from being left behind due to a step at the end of the second polycrystalline silicon film 21 covering the memory / transistor region, the main removal is performed in an isotropic dry state. This is performed using an etching technique. Further, since the etching can be stopped by the oxide film 27 ', the memory transistor region is not affected at all.

Subsequently, oxide film 27 ′ is removed by wet etching, and the surface of second polycrystalline silicon film 21 is completely exposed.

Next, as shown in FIG.
In the OS transistor portion, the tungsten polycide film 28 as the third conductive film is patterned by an anisotropic dry etching technique to form the gate electrode 28 of the peripheral circuit MOS transistor. Subsequently, by performing anisotropic dry etching in the memory transistor section,
Second polycrystalline silicon 21, interlayer insulating film 1 having a three-layer structure
A stacked two-layer gate electrode structure made of 8, 19, 20 and the first polysilicon 17 is formed. At this time, the two-layer gate electrode structure of the memory / transistor portion is overlapped and cut by a single lithography process using an anisotropic dry etching technique.

Subsequently, by ion implantation using a photoresist mask and a subsequent thermal annealing step,
A source region including the n + type semiconductor region 24, a drain region including the n + type semiconductor region 22, and a drain shield region including the p + type semiconductor region 23 are formed.

Thereafter, n-channel and p-channel MOS transistors having an LDD structure are formed in a peripheral circuit MOS transistor portion by a well-known CMOS process, while a non-doped and boron / phosphorus-doped silicon oxide film is deposited, a contact hole is formed, and aluminum is formed. Through the formation of the metal wiring consisting of the nonvolatile semiconductor memory device shown in FIG. 4, the nonvolatile semiconductor memory device including the nonvolatile memory transistor and the peripheral circuit MOS transistor is realized.

In the nonvolatile semiconductor memory device manufactured by the above-described manufacturing process, the memory cells forming the word lines of the memory array
The control gate electrode of the transistor is formed of polycrystalline silicon. In order to form this control gate electrode with a low-resistance wiring such as tungsten polycide similarly to the gate electrode of the peripheral circuit MOS transistor, a part of the manufacturing process is changed as shown in FIGS. Good. FIG.
2 and 13 correspond to FIGS. 10 and 11, respectively.

The following two points are changed in FIG.

(1) The third conductive film 28 is not a tungsten polycide film but a polycrystalline silicon single layer film having a thickness of 150 nm.

(2) After removing the third conductive film 28 from the memory transistor region, the fourth conductive film is continuously formed after removing the thermal oxide film 27 ′ on the second conductive film 21. 4
0 is formed. The fourth conductive film 40 is a tungsten silicide film formed by a chemical vapor deposition method, and has a thickness of 150 nm.

Thereafter, as shown in FIG. 13, the gate electrodes are patterned by anisotropic dry etching in the memory transistor portion and the peripheral circuit transistor portion. With the above change, on the memory transistor region, the tungsten silicide film 40 is electrically integrated with the polycrystalline silicon film 21 as the second conductive film, and a control gate electrode having a tungsten polycide structure can be obtained. Note that the thickness of the polycrystalline silicon film 21, which is the second conductive film, is desirably reduced to 150 nm so that the height of the two-layer gate electrode of the memory transistor is not increased more than necessary. On the other hand, on the peripheral circuit MOS transistor region, the tungsten silicide film 40 is electrically integrated with the polycrystalline silicon film 28 as the third conductive film,
A peripheral MOS transistor gate electrode having a tungsten polycide structure is realized.

In the nonvolatile semiconductor memory device manufactured by the above-described manufacturing process, the gate oxide film of the peripheral circuit MOS transistor has one specification (18 nm). To make these two specifications (for example, 18 nm and 35 nm) so that the MOS transistor for the peripheral circuit can be selectively used for high-speed read operation and high-voltage rewrite drive,
A part of the manufacturing process may be changed as follows.

Hereinafter, description will be made with reference to FIGS.

As shown in FIG. 14, the p-type well region 12
And an n-type well region 13, a field oxide film 14, and
The channel stopper 15 is formed in the same manner as in the manufacturing process of FIG.

Next, the surface of the active region is thermally oxidized to a thickness of 10
After forming the gate oxide film 16 having a thickness of 200 nm, a polysilicon film 17 having a thickness of 200 nm, which is a first conductive film, is deposited in the same manner as in the manufacturing process of FIG. Further, processing is performed so that the polysilicon film 17 has a shape suitable for use as a floating gate electrode in the memory transistor region. At this time, the polysilicon film 17 is left as it is in the first and second peripheral circuit MOS transistor regions.

Subsequently, a composite film of the silicon oxide films 18 and 20 and the nitride film 19 to be an interlayer insulating film of the memory transistor, and a second polysilicon film 21 are continuously formed.

Next, as shown in FIG.
The second polysilicon film 21, the interlayer insulating films 18, 19, and 20 and the first polysilicon film 17 formed on the OS transistor region are formed by a known dry etching technique, and the gate oxide film 16 is formed by a wet etching technique. To remove sequentially.

Thereafter, a thermal oxide film 36 is formed to a thickness of 28 nm. At this time, the oxide film 41 on the polysilicon film in the memory transistor region has a thickness of about 56 nm. afterwards,
The thermal oxide film 36 in the second peripheral MOS transistor region is removed by wet etching by a photoetching process.

Further, as shown in FIG. 16, the surface of the active region is newly thermally oxidized to form a gate oxide film 39 having a thickness of about 18 nm. At this time, the oxide film 38 in the first peripheral circuit MOS transistor region has a thickness of about 35 nm.
The thickness of the oxide film 41 on the polysilicon film in the memory transistor region is about 90 nm.

Subsequently, a third conductive film (polysilicon film or a composite film of a metal silicide film and a polysilicon film such as a tungsten polycide film) 40 is formed on the entire surface, and then the third conductive layer is formed. As shown in FIG. 17, a gate electrode 40 is formed in each peripheral MOS region by anisotropic etching technology.

At the boundary step between the memory transistor region and the peripheral circuit MOS transistor region, the third
Is left without being completely etched. However, the problem of short-circuiting between wirings by laying out such that the wiring of the MOS transistor for the peripheral circuit does not cross this step or by removing only this portion including the memory transistor region by another etching step is solved. Does not occur.

Subsequently, as shown in FIG. 18, an oxide film 41 on the memory / transistor region, a second polysilicon 21, a three-layered interlayer insulating film 18, 19, 20, one layer by a photo-etching step. Eye polysilicon 17,
A stacked two-layer gate electrode is formed.

Thereafter, similarly to FIG. 4, by forming the source and drain regions, contact holes, and aluminum wiring, the nonvolatile memory transistor shown in FIG.
MO for peripheral circuit composed of gate oxide film of two specifications
A nonvolatile semiconductor memory device including an S transistor is realized.

According to the present embodiment, the following effects can be obtained.

(1) A stacked gate type non-volatile memory transistor in which a composite film material of a silicon nitride film having a dielectric constant larger than that of a silicon oxide film is applied to an interlayer insulating film and a MOS transistor for a peripheral circuit for driving the stacked gate type nonvolatile memory transistor In addition, integration can be performed on the same semiconductor substrate by a highly reliable manufacturing process.

(2) As a result, without sacrificing the memory cell area and the reliability of the interlayer insulating film gate oxide film,
A highly integrated nonvolatile semiconductor memory device having excellent write, read, and erase characteristics can be realized.

In this embodiment, the case where a composite interlayer insulating film having a three-layer structure of a silicon oxide film / silicon nitride film / silicon oxide film is used as the interlayer insulating film has been described, but the present invention is not limited to this. Not something. The effectiveness of the present invention does not change even when a two-layer structure of a silicon oxide film / silicon nitride film or another high dielectric constant film such as a tantalum oxide film (Ta ₂ O ₅ ) and a composite film thereof are used. .

In this embodiment, a highly integrated and electrically rewritable nonvolatile semiconductor memory device in which a memory cell can be constituted by one nonvolatile memory transistor has been described as an example. The present invention is not limited to this. FAMOS (Floating g
The present invention is effective in general in nonvolatile semiconductor memory devices using nonvolatile memory transistors having floating gate electrodes, including ATE Avalanche injection MOS).

A manufacturing method in which the number of steps for forming a conductive film is reduced as compared with the above embodiment will be described below with reference to FIGS.

FIG. 22 is a cross-sectional view of an integrated circuit element including a nonvolatile memory transistor and a peripheral circuit MOS transistor formed on the same semiconductor substrate by the manufacturing method described in this embodiment. FIGS. It is sectional drawing explaining the manufacturing process by an Example.

The structures of the nonvolatile memory transistor and the peripheral circuit MOS transistor formed on the same semiconductor substrate by the manufacturing method described in this embodiment of FIGS. 19 to 22 are almost the same as those of the embodiment already described. Description is omitted.

Next, the flow of the manufacturing process according to this embodiment will be described in detail with reference to FIGS.

As shown in FIG. 19, the p-type semiconductor substrate 11
A p-type well region 12 and an n-type well region 13 are formed on the main surface of the substrate by a normal twin-tub process for CMOS, and a field oxide film 14 for element isolation and a parasitic channel prevention comprising a p + type semiconductor region are further formed by a LOCOS process. Is formed.

Next, the surface of the active region is thermally oxidized to a thickness of 15 μm.
After forming a gate oxide film 27 nm in thickness, the thermal oxide film in the memory transistor region is removed by a photo-etching step, and the surface of the active region is thermally oxidized again to form a gate oxide film 16 having a thickness of 10 nm. At this time, MOS for peripheral circuits
The thickness of the gate oxide film 27 in the transistor region is 18 nm.
About.

Subsequently, the first conductive film having a thickness of 200
A polycrystalline silicon film 17 of nm is deposited by a known chemical vapor deposition method. After doping the polycrystalline silicon film with phosphorus (P) as an n-type impurity by a known thermal diffusion method or ion implantation method, the polycrystalline silicon film 17 is used as a floating gate electrode in the memory transistor region. Pattern it into a suitable shape. At this time,
In the peripheral circuit MOS transistor region, the polycrystalline silicon film 17 is left as it is.

Subsequently, as in the above-described embodiment, the silicon oxide films 18, 2 serving as interlayer insulating films of the memory transistors are formed.
Then, a composite film of 0 and the nitride film 19 and a second conductive film 21 are sequentially formed. At this time, the second conductive film 21 is a polycrystalline silicon film or a two-layer film of a tungsten silicide film and a polycrystalline silicon film.

Thus, the composite interlayer insulating films 18, 19, 2
0 is covered with the polycrystalline silicon film 21 immediately after the formation,
Since it is not exposed thereafter, highly reliable interlayer insulating film characteristics can be realized.

Next, as shown in FIG.
Second conductive film 2 formed on OS transistor region
1. The interlayer insulating films 18, 19, 20 are sequentially removed by a known dry etching technique. Interlayer insulating films 18, 19, 20
Is etched, the peripheral circuit MOS transistor region is completely covered with the first-layer polycrystalline silicon film 17. In this series of dry etching steps, there is no concern that the surface of the substrate in the MOS transistor region for the peripheral circuit will be affected by contamination or damage.

Next, as shown in FIG. 21, the first layer polycrystalline silicon film 17 is patterned by an anisotropic dry etching technique to form a gate electrode of a peripheral circuit MOS transistor. Then, a stacked two-layer gate electrode including the second conductive film 21, the interlayer insulating films 18, 19, 20, and the first-layer polycrystalline silicon film 17 having a three-layer structure is formed. At this time, the two-layer gate electrode is overlapped and cut in one lithography process by an anisotropic dry etching technique.

Thereafter, the same source and drain region forming steps and wiring steps as in the above-described embodiment are performed. Through the above steps, a nonvolatile semiconductor memory device including the nonvolatile memory transistor and the peripheral circuit MOS transistor shown in FIG. 22 is realized.

According to this embodiment, a nonvolatile semiconductor memory device including a nonvolatile memory transistor and a MOS transistor for a peripheral circuit can be realized with a small number of conductive films.

In this embodiment, as described above,
It can be applied to various interlayer insulating films and conductive film materials. Further, the present invention is effective in general in a nonvolatile semiconductor memory device using a nonvolatile memory transistor having a floating gate electrode.

Next, with reference to FIGS. 23 to 28, a description will be given of a manufacturing method when the gate insulating film of the peripheral MOS transistor has two specifications in order to make the peripheral circuit have a high withstand voltage and a high speed in the nonvolatile semiconductor memory device. This will be described in detail.

FIGS. 23 to 28 are a sectional view and a plan view for explaining the manufacturing process according to this embodiment.

First, in the structure of FIG. 28, the gate oxide film of the peripheral MOS transistor has two specifications (18/35 nm).
The feature is that.

As shown in FIG. 23, the p-type well region 12
And an n-type well region 13, a field oxide film 14, and
A channel stopper 15 for preventing a parasitic channel made of a p + type semiconductor region is formed in the same manner as in the above-described embodiment.

Next, the surface of the active region is thermally oxidized to a thickness of 30.
After forming the gate oxide film 51 of nm, the gate oxide film 51 in the memory transistor region is removed by a photoetching process. Thereafter, the surface of the active region in the memory transistor region is thermally oxidized to form a gate oxide film 50 having a thickness of 10 nm. At this time, the thickness of the gate oxide film 51 in the first peripheral MOS region becomes 35 nm. Subsequently, as in the above-described embodiment, the first conductive layer having a thickness of 20
A polycrystalline silicon film 49 having a thickness of 0 nm is formed. In the memory transistor region, the polycrystalline silicon film 49 is patterned so as to serve as a floating gate electrode, and first and second polycrystalline silicon films 49 are formed.
The polycrystalline silicon film 49 is left so as to protect the entire surface in the peripheral circuit MOS transistor region.

Subsequently, a composite film of the silicon oxide films 18 and 20 and the nitride film 19 to be an interlayer insulating film of the memory transistor and a 300-nm-thick polysilicon film 52 as a second conductive layer are formed.

Thereafter, as shown in FIG.
2 formed on the MOS transistor region for the peripheral circuit of FIG.
The polycrystalline silicon film 52 of the layer, the interlayer insulating films 18 and 19,
20 are sequentially removed by a known dry etching technique.

Next, as shown in FIG. 25, the first polycrystalline silicon film 49 in the second peripheral circuit MOS transistor region is removed by a known dry etching technique. Thereafter, the gate oxide film 51 is formed by wet etching.
Is removed.

Subsequently, as shown in FIG. 26, the active region surface of the second peripheral circuit MOS transistor portion is thermally oxidized again to form a gate oxide film 53 having a thickness of 18 nm.
At this time, 5 μm is formed on the polysilicon film in the memory transistor region and the first peripheral circuit MOS transistor region.
Oxide films 55 and 56 of about 0 nm are formed. Next, 3
A third conductive layer (polysilicon film or a composite film of a metal silicide film such as a tungsten polycide film and a polycrystalline silicon film) 54 having a thickness of 00 nm is deposited by a known chemical vapor deposition method. Thereafter, the third transistor in the memory transistor region and the first peripheral circuit MOS transistor region
Is removed by dry etching.

Furthermore, as shown in FIG. 27, the polycrystalline silicon film 4 in the first peripheral circuit MOS transistor region is formed.
9, the upper oxide film 56, and the third conductive film 54 in the second peripheral circuit MOS transistor region are processed into gate electrodes by dry etching technology. Subsequently, a stack-type two-layer gate electrode including the second-layer polycrystalline silicon film 52, the three-layered interlayer insulating films 18, 19, and 20 and the first-layer polycrystalline silicon film 49 is formed by a photoetching process. At this time, the multilayer film is overlap-cut in one lithography step by an anisotropic dry etching technique.

Thereafter, similarly to the above-described embodiment, the non-volatile memory transistor and the gate oxide film of two specifications are formed as shown in FIG. 28 by forming source and drain regions, forming contact holes, and forming aluminum wiring. A nonvolatile semiconductor memory device including MOS transistors for peripheral circuits is realized.

According to the present embodiment described above, the gate oxide film thickness of the MOS transistor for the peripheral circuit can be set to two specifications, and the MOS transistor for the peripheral circuit can be driven at a high speed for reading and a high voltage drive for rewriting. It can be used properly for different purposes.

[0131]

According to the present invention, a nonvolatile memory transistor in which a film material having a dielectric constant larger than that of a silicon oxide film is applied to an interlayer insulating film, and an M for peripheral circuits for driving the same.
OS transistors can be integrated over the same semiconductor substrate by highly reliable manufacturing process steps. As a result, without sacrificing the memory cell area,
A nonvolatile semiconductor memory device having excellent write, read, and erase characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a basic embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a basic embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a basic embodiment of the present invention.

FIG. 4 is a sectional view of a nonvolatile semiconductor memory device formed by a manufacturing method according to a specific embodiment of the present invention;

FIG. 5 is an internal block diagram of a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 6 is a layout plan view of a 4-bit memory cell array of a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 7 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 8 is a layout plan view of a memory cell array of a nonvolatile semiconductor memory device according to a specific example of the present invention.

FIG. 9 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 10 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 11 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific example of the present invention.

FIG. 12 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 13 is a diagram illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a specific example of the present invention.

FIG. 14 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 15 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 16 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 17 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 18 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 19 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 20 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 21 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 22 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 23 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 24 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 25 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 26 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 27 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

FIG. 28 is a view illustrating a method of manufacturing a nonvolatile semiconductor memory device according to another specific embodiment of the present invention.

[Explanation of symbols]

1. semiconductor substrate, 2. field oxide film for element isolation,
3: gate oxide film of nonvolatile memory transistor, 5
... first conductive film (floating gate electrode of memory transistor, MOS transistor area for peripheral circuit)
6 ... interlayer insulating film, 7 ... second conductive film (control gate electrode of memory transistor, cover of interlayer insulating film 6), 8
... Gate insulating film of MOS transistor for peripheral circuit, 10
... Third conductive film (gate electrode of peripheral circuit MOS transistor).

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisa-ryu ▼ Tokuo 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Masahiro Ushiyama 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory Co., Ltd. (72) Inventor Dr. Kawakami 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory Co., Ltd. (56) References JP-A-3-283570 (JP, A) JP-A Sho57 JP-A-76876 (JP, A) JP-A-63-73566 (JP, A) JP-A-2-297970 (JP, A) JP-A-61-245577 (JP, A) JP-A-64-5072 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A nonvolatile memory transistor having a floating gate electrode and a control gate electrode and a MOS transistor for a peripheral circuit having a gate electrode are formed in a first region and a second region of the same semiconductor substrate, respectively. A method of manufacturing the semiconductor device, wherein the first region and the second region are formed on a semiconductor substrate.
A first step of forming a silicon oxide film to be a gate insulating film of the nonvolatile memory transistor later; and forming a conductive film to be the floating gate electrode later on the silicon oxide film so as to cover at least the entire surface of the second region. A second step of forming a layer, and an insulating layer having a higher dielectric constant than the silicon oxide film, which is to be an interlayer insulating film of the nonvolatile memory transistor later, on the conductive layer covering the entire surface of the second region. A third step of forming a film, a fourth step of sequentially removing the insulating film, the conductive layer, and the silicon oxide film in the second region, and forming a peripheral region on the semiconductor substrate in the second region. A fifth step of forming a gate insulating film of the circuit MOS transistor; and a sixth step of forming the gate electrode on the gate insulating film of the peripheral circuit MOS transistor. Method of manufacturing that the non-volatile semiconductor memory device. 2. The method according to claim 1, wherein a part of said insulating film includes at least a silicon nitride film. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, wherein said insulating film has a structure in which a silicon nitride film is inserted between silicon oxide films. 4. A nonvolatile memory transistor having a floating gate electrode and a control gate electrode and a MOS transistor for a peripheral circuit having a gate electrode are formed in a first region and a second region of the same semiconductor substrate, respectively. Forming a first silicon oxide film to be a gate insulating film of the nonvolatile memory transistor later on the semiconductor substrate in the first region, Forming a second silicon oxide film to be a gate insulating film of the peripheral circuit MOS transistor later on a semiconductor substrate;
And forming a first conductive layer that will later become the floating gate electrode and the gate electrode on the first and second silicon oxide films so as to cover at least the entire surface of the second region.
And a lower dielectric constant than the first and second silicon oxide films, which will later become an interlayer insulating film of the nonvolatile memory transistor, on the first conductive layer covering the entire surface of the second region. A third step of forming an insulating film having a large thickness, a fourth step of forming a second conductive layer to be the control gate electrode later on the insulating film, and a step of forming the second conductive layer in the second region. A fifth step of partially removing the layer and the insulating film. 5. The method according to claim 4, wherein a part of said insulating film includes at least a silicon nitride film. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein said insulating film has a structure in which a silicon nitride film is inserted between silicon oxide films.