JPH0817948A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of an MOS transistor which has a gate insulating film of high breakdown voltage and can realize high level of integration and high reliability. CONSTITUTION:In the manufacturing method of an MOS transistor, a first layer polycrystalline silicon film 15 is formed on a silicon substrate 10 via a gate oxide film, and then selectively etched by using an island pattern as a mask, and a trench 11 for element isolation is formed by selectively etching the substrate 10. A CVD oxide film 12 is buried and formed in the trench 11, a second layer polycrystalline silicon film 20 is formed on the whole surface, and the second layer polycrystalline silicon film 20 and the first layer polycrystalline silicon film 15 are selectively etched by using a line type pattern formed on the first layer polycrystalline silicon film 15 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS structure, and more particularly to a semiconductor device having improved element isolation technology and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a trench isolation method has been widely used instead of a LOCOS isolation method as an element isolation technique for semiconductor integrated circuits. In the trench isolation method, first, a thermal oxide film, a polycrystalline silicon film, and a CVD silicon oxide film formed on a silicon substrate are resist-patterned and etched by RIE. After that, the resist is peeled off, and the silicon substrate is RIEed and etched using the CVD silicon oxide film as a mask to form trenches for element isolation.

Then, in order to reduce crystal defects generated during the formation of the trench, heat treatment in a nitrogen atmosphere and thermal oxidation in an oxidizing atmosphere are performed to form an oxide film on the sidewall of the trench. Here, impurities may be implanted into the trench sidewall and the trench bottom in order to enhance the element isolation capability. Next, the trench is filled with an insulator by the CVD method. After that, the CVD insulator is ground and planarized by resist etch back or polishing until the polycrystalline silicon is exposed, and the polycrystalline silicon and the oxide film thereunder are removed.

Since the element isolation region is formed by the processes up to this point, elements such as transistors will be formed on the element region in the following. First, the silicon substrate on the element region is oxidized, and impurities are implanted through the oxide film for controlling the threshold value of the transistor. Then, the previous oxide film is once peeled off, a gate oxide film is newly formed, and polycrystalline silicon to be a gate is deposited. After that, the gate is patterned, a diffusion layer is formed, and wiring is performed, whereby a transistor is completed.

By such a trench element isolation method, the trench width for element isolation can be narrowed to a certain extent. However, the following problems occur in the process of forming the gate oxide film and the gate electrode after forming the trench element isolation region as described above.

As shown in FIG. 31A, the element isolation region has an insulating film 12 in a trench 11 provided in a substrate 10.
Is formed by embedding the element isolation region, but by the NH ₄ F treatment after forming this element isolation region, a corner 1 is formed at the end of the element region.
You can do 4. After that, if a gate oxide film is formed to form a transistor, an electric field is concentrated at the corner 14, causing dielectric breakdown of the gate oxide film, kinking of a subthreshold current, etc., and greatly deteriorating the characteristics of the transistor. . Therefore, it is necessary to devise a process so that this corner is not formed.

Further, as shown in FIG. 31B, for example, the floating gate 3 is formed on the substrate 10 via the tunnel insulating film 13.
0 is formed, and the gate insulating film 31 is formed on the floating gate 30.
The element isolation method as described above is applied to a non-volatile semiconductor memory device in which a control gate 29 is formed through the above to form an electrically rewritable memory cell and a plurality of the memory cells are integrated. Consider the case.

In this case, after forming the element isolation region, the tunnel oxide film and the polycrystalline silicon electrode, it is necessary to form a slit of polycrystalline silicon on the element isolation region in order to form the floating gate. With integration, unless the slit width of the floating gate electrode is reduced to a certain extent or less, the capacitance between the floating gate and the control gate becomes small and the coupling ratio becomes small. For example, the element isolation width is 0.
In the case of 4 μm, it is necessary to form the slit width to be 0.2 μm or less in consideration of the coupling ratio.
It becomes extremely difficult to make the element isolation region smaller.

Further, when digging the semiconductor substrate in the element isolation region, it is very difficult to dig the entire semiconductor substrate with a uniform width, and as a result, the gate width of the memory cell varies in the entire semiconductor substrate. Therefore, the capacitance between the semiconductor substrate and the floating gate varies, and the coupling ratio also varies. At this time, if the capacitance between the floating gate and the control gate can be adjusted so as to cancel it (for example, when forming a slit in the polycrystalline silicon that will be the floating gate on the element isolation region,
If the slit width is narrower where the gate width is wider, the capacitance between the floating gate and the control gate is increased) and the variation in the coupling ratio can be reduced. However, it is impossible to adjust the capacitance between the floating gate and the control gate in this way for all the large number of memory cells in the semiconductor substrate.

Further, in an electrically rewritable memory, it is necessary to form various kinds of peripheral circuit transistors and select transistors in addition to the memory cells. If these transistors are formed in a process different from that of the memory cell, the number of steps is increased and the cost per bit is increased. Therefore, it is desirable to manufacture the memory cell in the same process.

[0011]

As described above, in the conventional trench element isolation process, the formation of a corner in the element region causes dielectric breakdown of the gate oxide film, a kink in the subthreshold characteristics, and a minimum element isolation width. Has a problem that it is substantially determined by the slit width of the gate electrode. Further, for example, when the element isolation method as described above is applied to a non-volatile memory, if the slit width of the gate electrode cannot be reduced to a certain level or less due to integration, the capacitance between the floating gate and the control gate becomes small, There are problems that the coupling ratio becomes small and that the coupling ratio varies due to the variation in the gate width that occurs when forming the element isolation region.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device having a high breakdown voltage gate insulating film and capable of achieving high integration and high reliability. It is to provide a manufacturing method.

[0013]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention (claim 1), in a semiconductor device having a MOS structure, an element isolation groove formed so as to surround an island-shaped element formation region in a semiconductor substrate, and an element embedded in the groove. An isolation insulating film, a first conductive film which is formed on a part of an element formation region of a semiconductor substrate via a gate insulating film, and has both ends self-aligned with an element isolation groove; It is characterized by comprising a conductive film and a second conductive film formed on the element isolation insulating film.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device having the above structure, a step of forming a first-layer conductive film on a semiconductor substrate via a gate insulating film, and using the island pattern as a mask. A step of selectively etching the first-layer conductive film and a substrate to form an element isolation groove, a step of embedding an insulating film in the element isolation groove, and a second-layer conductive film formed on the entire surface. The method is characterized by including a step and a step of selectively etching the second-layer conductive film and the first-layer conductive film using a linear pattern passing over the first-layer conductive film as a mask.

Further, according to the present invention (claim 3), a floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed on the floating gate via a gate insulating film to enable electrical rewriting. A non-volatile memory cell,
In a semiconductor device in which the memory cells are arranged in a matrix, an element isolation groove for isolating the memory cells is formed in a semiconductor substrate, and an element isolation insulating film is buried in the groove, and two opposing sides of a floating gate are formed. Are self-aligned with the element isolation trench, and the remaining two sides are self-aligned with the control gate.

The present invention (claim 4) is a method for manufacturing a semiconductor device in which electrically rewritable nonvolatile memory cells are arranged in a matrix on a semiconductor substrate, and a tunnel insulating film is provided on the semiconductor substrate. A step of forming a first-layer conductive film to be a floating gate, and a step of selectively etching the first-layer conductive film and the tunnel insulating film using the line pattern as a mask, and further selectively etching the substrate to form a device isolation groove. And a step of burying an insulating film in the isolation trench, a step of forming a second-layer conductive film to be a control gate on the entire surface through a gate insulating film, and a line-shaped pattern of the first conductive film. And a step of selectively etching the second-layer conductive film and the first-layer conductive film using the second line-shaped pattern as a mask.

The preferred embodiments of the present invention are as follows.

(1) The buried insulating film is buried up to a position higher than the substrate surface and lower than the upper surface of the first-layer conductive film.

(2) After the selective etching of the conductive film of the first layer and before the selective etching of the trench for element isolation, the first conductive film on the semiconductor substrate is formed.
Forming an insulating film thinner than the insulating film under the first conductive film in a region close to the conductive film, and forming a conductive material electrically connected to the first conductive film on the insulating film.

(3) The conductive material used for a part of the etching mask of the semiconductor substrate is formed in contact with the substrate. Further, the etching mask of the semiconductor substrate is formed of at least two layers of conductive material.

(4) The etching mask for the semiconductor substrate is formed of at least two layers of conductive material.

(5) In the semiconductor memory device, at least a part of the gate electrode of the peripheral transistor (transistor other than the memory cell) has the same conductive layer as the floating gate of the memory cell.

(6) In the semiconductor memory device, the coupling ratio is controlled by controlling the area of the side wall of the floating gate corresponding to the gate width.

(7) The conductive material used for the etching mask of the semiconductor substrate is used as the floating gate electrode, and the insulating film of the floating gate is present on at least a part of the side wall of the conductive material. The conductive material of the eye is laminated.

(8) At least a part of a gate electrode of a transistor other than a memory cell is formed by laminating at least a part of layers of a floating gate electrode and a control gate electrode, and is electrically connected at least at a part. thing.

[0027]

According to the present invention, since the slit width of the first-layer conductive film becomes the element isolation width as it is, ie, so-called self-alignment is performed, the distance between the respective transistors can be reduced and high integration can be achieved. Furthermore, by forming the embedded insulating film to a position higher than the surface of the substrate, it is possible to form a high breakdown voltage gate insulating film without forming a corner at the end portion of the element region.

In the present invention, since the high-energy particles hit the edge portion of the gate insulating film when the semiconductor substrate is dug, the reliability of the gate insulating film may be lowered.
Furthermore, when the insulator buried in the trench is etched back, charges are charged up in the gate electrode, and the electric field generated thereby may cause dielectric breakdown of the gate insulating film or decrease in reliability.

However, by forming the side wall on the gate electrode, the oxide film edge portion is protected when the trench is dug, so that the breakdown voltage does not deteriorate. further,
Since the insulating film thinner than the gate insulating film is formed under the side wall, the dielectric breakdown of the gate insulating film caused by the charge-up of the gate electrode, which occurs when the insulator buried in the trench is etched back. Alternatively, the reliability is reduced in the insulating film thinner than the gate insulating film, so that damage to the gate insulating film is reduced.

Regarding the nonvolatile semiconductor memory device,
In the case of applying the above-mentioned element isolation method, the etching rate greatly depends on the element isolation width because the rate of gas supply is controlled when etching back the insulator buried in the trench. That is, for example, when the trench width is narrow (that is, the gate width is wide), the etching rate becomes fast, and the capacitance between the floating gate and the control gate on the floating gate sidewall increases. Also, when the trench width is wide, the opposite is true. This reduces variations in the coupling ratio within the semiconductor substrate.

Further, the coupling ratio can be controlled by adjusting the area of the floating gate side wall portion in accordance with the gate width. Further, since the peripheral circuit transistor and the selection transistor can be formed in the same process as the memory cell, the number of steps can be reduced. Further, the present invention is effective for all processes in which the gate electrode may be charged up, such as ion implantation, RIE, and CDE.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing an element structure of a MOS transistor according to a first embodiment of the present invention,
2A is a sectional view taken along the line AA 'in FIG. 1, and FIG. 2B is a sectional view taken along the line BB' in FIG. In this embodiment, a single transistor structure is shown, but in general, this trench element isolation can also be used for cell structures such as DRAM, SRAM, and EEPROM.

In the figure, 10 is an n-type silicon substrate, 11 is an element isolation groove (trench), 12 is a buried insulating film, 13 is a gate insulating film, 15 is a gate electrode made of a first-layer conductive film, and 17 is element isolation. Region, 18 is element region, 19 is CV
D insulating film, 20 is a gate electrode made of a second conductive film, 2
Reference numeral 1 is a gate electrode contact, 22 is a source / drain electrode, 23 is a source / drain diffusion layer, and 24 is an interlayer insulating film.

Next, the manufacturing process of this embodiment will be described with reference to FIG.
This will be described with reference to FIGS. These figures are shown in FIG.
It corresponds to the A ′ cross section.

First, as shown in FIG. 3A, an n-type silicon substrate 10 is provided with, for example, a surface boron concentration of 1 × 10 ¹⁶ cm ^−3.
Then, a p-well is formed, and appropriate channel implantation is performed to adjust the threshold value in the region where the gate is formed. Subsequently, a thermal oxide film (gate insulating film) 13 having a thickness of 10 nm, for example, is formed on the surface of the silicon substrate 10, and a first-layer polycrystalline silicon film 15 serving as a gate electrode is deposited to a thickness of 400 nm, for example.

Next, as shown in FIG. 3B, after forming an oxide film of, for example, 18 nm on the polycrystalline silicon film 15, the oxide film 1 serving as a mask during trench RIE is formed thereon.
9 is deposited to a thickness of 350 nm by the CVD method, for example.

Next, as shown in FIG. 3C, after patterning the element isolation region by a photolithography process, CVD is performed using a resist (not shown) as a mask.
Oxide film 19, polycrystalline silicon film 15, gate oxide film 13
Is selectively etched by anisotropic etching, and the silicon substrate 10 is further selectively etched by anisotropic etching to form a trench 11 for element isolation. In this etching, the CVD oxide film 19 to the silicon substrate 10 may be etched using the resist as a mask and the resist may be peeled off at the end, or the CVD oxide film 19 may be etched using the resist as a mask and then the resist is peeled off. Then, the polycrystalline silicon film 15, the gate oxide film 13, and the silicon substrate 10 may be etched using the CVD oxide film 19 as a mask.

Next, in order to remove the damage generated at the time of forming the trench, a heat treatment is performed in, for example, a nitrogen atmosphere or an inert gas atmosphere, and the meaning of protecting the edge of the gate oxide film 13 is also included. The trench sidewall is thermally oxidized in an oxidizing atmosphere containing water vapor. Here, in order to prevent field inversion, impurities may be implanted into the sidewall of the trench or the bottom of the trench.
Then, as shown in FIG. 4D, S is formed by a CVD method using, for example, TEOS gas so as to fill the trench.
The iO ₂ film 12 is deposited to a thickness of 1000 nm, for example.

Next, as shown in FIG. 4E, the oxide film 12 is etched back by RIE until the polycrystalline silicon film 15 is exposed. At this time, the polycrystalline silicon film 15
Acts as a stopper for etch back. For this etch back, an etching back technique using a resist may be used, or polishing may be used.

Then, the polycrystalline silicon film 15 is coated with, for example, 1
After forming a 2 nm oxide film, for example, phosphorus doping is performed at 1 × 10 ¹⁸ cm ⁻³ . After etching the oxide film, the second-layer polycrystalline silicon film 20 is formed for wiring the gate electrode.
Is deposited to a thickness of 200 nm by, for example, a CVD method, and phosphorus doping is performed at 1 × 10 ²¹ cm ⁻³ by an ion implantation method. After that, the gate region is patterned by a photolithography process, and then the polycrystalline silicon film 20 is etched. The state of the AA 'cross section at this time is shown in FIG.
FIG. 5 (g) shows the state of the BB 'cross section.

After that, after the source / drain diffusion layer formation, the interlayer insulation deposition, and the contact hole etching process, the source / drain wiring is performed by, for example, A1 to complete the transistor shown in FIGS. .

As described above, according to this embodiment, as compared with the conventional trench element isolation method, the wing of the gate polycrystalline silicon is not formed, so that high integration can be achieved. Further, a corner is not formed at the end portion of the element region, and a high breakdown voltage gate oxide film can be formed.

(Embodiment 2) In the first embodiment, high energy particles hit the edge portion of the gate oxide film when the semiconductor substrate is dug, which may cause deterioration of the gate oxide film. Further, when the insulator deposited in the trench is etched back, the gate electrode may be charged up, which may cause deterioration of the gate oxide film.

In this embodiment, since the edge portion of the gate oxide film is protected by the side wall of polycrystalline silicon when the semiconductor substrate is dug, deterioration is unlikely to occur. Further, since the oxide film thinner than the gate oxide film is formed in the region under the side wall of the polycrystalline silicon, the deterioration of the oxide film during the etch back occurs in this region, and the deterioration of the gate oxide film is reduced. it can. The steps of this embodiment will be described below with reference to FIGS.
Shown in

First, as shown in FIG. 6A, the n-type silicon substrate 10 is provided with, for example, a surface boron concentration of 1 × 10 ¹⁶ cm ^−3.
Then, a p-well is formed, and appropriate channel implantation is performed to adjust the threshold value in the region where the gate is formed. Then, a thermal oxide film (gate insulating film) 13 having a thickness of, for example, 10 nm is formed on the surface of the silicon substrate, and a first gate electrode is formed.
The layer polycrystalline silicon film 15 is deposited to a thickness of 400 nm, for example. After that, the SiN film 43 is formed on the polycrystalline silicon film 15 to have a thickness of 50 nm, for example.

Next, as shown in FIG. 6B, after patterning the element isolation region by a photolithography process, the upper portion S is formed by using a resist (not shown) as a mask.
iN film 43, polycrystalline silicon film 15, gate oxide film 13
Is etched by anisotropic etching. The etching at this time is performed by using the resist as a mask and the upper SiN film 4
3 to the gate oxide film 13 may be etched and the resist may be removed at the end, or the upper SiN film 43 may be etched using the resist as a mask and then the resist may be removed.
Polycrystalline silicon film 1 using upper SiN film 43 as a mask
5. The gate oxide film 13 may be etched.

Next, as shown in FIG. 6C, an oxide film 44 having a thickness smaller than that of the gate oxide film 13, for example, 5 nm is formed on the exposed substrate surface by thermal oxidation. Next, as shown in FIG. 6D, a polycrystalline silicon film 45, which is heavily doped in the adjacent area, is deposited to a thickness of, for example, 30 nm. This polycrystalline silicon film 45 does not need to be adjacently doped.

Then, as shown in FIG. 7E, RIE is performed.
Thus, the polycrystalline silicon film 45 is etched to form a polycrystalline silicon side wall 46 on the polycrystalline silicon film 15.

Then, as shown in FIG. 7F, RIE is performed.
Alternatively, after etching the thin oxide film 44 on the silicon substrate 10 with NH ₄ F, the silicon substrate 10 is etched by RIE. At this time, the polycrystalline silicon film 15
Since the upper SiN film 43 serves as a mask when the silicon substrate 10 is etched, it needs to be thick enough not to be completely etched by the NH ₄ F treatment.

Then, in order to remove crystal defects generated during the formation of the trench, heat treatment is performed in, for example, a nitrogen atmosphere or an inert gas atmosphere, and then the trench sidewalls are removed in an oxidizing atmosphere containing hydrogen chloride or water vapor. Thermally oxidize. At this time, the polycrystalline silicon 46 on the side wall needs to be thick enough not to be completely oxidized. Here, in order to prevent field inversion, impurities may be injected into the sidewall of the trench or the bottom of the trench. After that, FIG.
As shown in (g), the oxide film 12 is deposited by, for example, a CVD method using TEOS gas so as to fill the trench.

Next, as shown in FIG. 8H, the oxide film 12 is etched back until the polycrystalline silicon film 15 is exposed. At this time, the polycrystalline silicon film 15 functions as a stopper for etch back. For this etch back, an etch back technique using a resist may be used, or polishing may be used.

Next, as shown in FIG. 8I, the sidewall polycrystalline silicon 46 is completely oxidized to form an oxide film 47. The oxide film 47 is formed not only on the side wall of the polycrystalline silicon film 15 but also on the upper surface thereof. At this time, if the sidewall polycrystalline silicon 46 is heavily doped with impurities, it is much more easily oxidized than the undoped polycrystalline silicon film 15.

Next, as shown in FIG. 8J, the oxide film 47 is etched by, eg, NH ₄ F treatment or RIE until the surface of the polycrystalline silicon film 15 is exposed.
After that, the transistor is completed in the same manner as the process of the first embodiment.

(Embodiment 3) An embodiment in which the element isolation method of the present invention is applied to a nonvolatile semiconductor device (NAND type EEPROM) will be described. 9 is a plan view showing two NAND cell parts, FIG. 10A is a sectional view taken along the line AA ′ in FIG. 9 (memory cell part), and FIG.
B ′ cross-sectional view (selection and peripheral transistor portion), FIG.
FIG. 10 is a sectional view taken along the line CC ′ of FIG. 9. In FIG. 9, M (M1 to M8) are memory cells, and S (S1, S2) are select transistors.

In the present embodiment, since the side wall of the floating gate is also used as the capacitance between the floating gate and the control gate, the coupling ratio can be increased and the coupling ratio is controlled in consideration of the gate width. With characteristics. Further, when the oxide in the trench is etched back, the etchback progresses faster in the region where the gate width is wide, and the etchback progresses slowly in the region where the gate width is narrow.
Therefore, the variation of the coupling ratio is reduced. Further, the selection and peripheral transistors can also be formed in the same step as the memory cell by etching the insulating film on the floating gate before depositing the polycrystalline silicon serving as the control gate, and the number of steps can be reduced.

The manufacturing process of this embodiment will be described with reference to FIGS. In these figures, (a) shows the cell part in the AA 'cross section, and (b) shows the peripheral part in the BB' cross section.

First, element isolation is performed by the same steps as in the first or second embodiment. However, in this embodiment, in order to form a line-shaped element region rather than forming a trench so as to surround the island-shaped element region, a floating gate is used as a mask with a line-shaped resist pattern in the direction orthogonal to the word lines as a mask. The first-layer polycrystalline silicon film to be formed is selectively etched, and the substrate is selectively etched to form line-shaped trenches.

Then, as shown in FIG. 12, for example, 12
After the thermal oxide film 13 having a thickness of 10 nm is formed, the first-layer polycrystalline silicon film 30 serving as a floating gate is formed in the cell portion, and the first-layer polycrystalline silicon film 15 serving as a gate electrode is formed in the peripheral portion. These polycrystalline silicon films 30 and 15 are formed by patterning the same film. Then, the polycrystalline silicon films 30 and 15 are doped with, for example, 1 × 10 ¹⁸ cm ⁻³ . Further, the polycrystalline silicon films 30, 15
After removing the upper oxide film, a silicon oxide film or an oxide film 31 of ONO or the like is formed to a thickness of 20 nm, for example.

Next, as shown in FIG. 13, a photoresist 33 is formed on the cell portion by a photolithography process, and the oxide film 31 on the peripheral gate and the select gate not covered with the resist 33 is removed by etching. At this time, in the peripheral portion, the sidewall oxide film 34 is formed on the side of the gate electrode 15.
Will remain.

Then, as shown in FIG. 14, the second-layer polycrystalline silicon film 29 serving as a control gate is formed in the cell portion, and the second-layer polycrystalline silicon film 20 serving as a gate electrode is formed in the peripheral portion.
Is accumulated by, for example, 200 nm. These polycrystalline silicon films 29 and 20 are substantially the same film except that the formation regions are different.

Then, using the line-shaped resist pattern in the word line direction as a mask, the second-layer polycrystalline silicon film 29 (2
0), oxide film 31, first-layer polycrystalline silicon film 30 (1
5) is selectively etched by RIE to separate the memory cell and the selection transistor in the word line direction. And
The memory cell is completed by forming the source / drain diffusion layers.

(Embodiment 4) Next, as a fourth embodiment of the present invention, a memory cell portion and a peripheral circuit portion of an EEPROM (Vpp system Tr, VM / Vcc system Tr section; Vpp is a high voltage,
The process of simultaneously forming the intermediate voltage VM and the power supply voltage Vcc will be described.

First, as shown in FIG. 15A, on the p-type silicon substrate 50, for example, the surface phosphorus concentration is 1 × 10 ¹⁶ cm ^−3.
To form the n-type well 51 in combination with a lithography process, and then, for example, the surface boron concentration is 3 × 1.
The p-type well 52 is selectively formed to have a ^density of 0 ⁶ cm ^-3 . At this time, the n well 51 is formed deeper than the p well 52, and is a double well in the cell portion as shown in FIG.

Then, a field oxide film 53 is formed by a normal LOCOS process. Then, after performing channel implantation of each transistor, a gate oxide film 54 of, for example, 30 nm thick Vpp-based Tr is formed. Next, Vpp system T
Only the portion to be the r portion is covered with the resist 55, and the oxide films of the other Tr portion and the cell portion are removed by etching. Then V
The M / Vcc Tr gate oxide film 56 and the select transistor gate oxide film are oxidized and formed, for example, to 16 nm.

Next, as shown in FIG. 15B, Vpp
System, VM / Vcc select transistor part is covered with resist,
The oxide film in the memory cell portion is removed by etching. afterwards,
The tunnel oxide film 57 is formed by thermal oxidation of 6 to 10 nm, for example.

Then, as shown in FIG. 16C, the first
The layer polycrystalline silicon film 58 is, for example, 400 nm, CVDS
An iO ₂ film 58 is formed to a thickness of 200 nm. Then, a trench pattern is formed by a photolithography process.

Next, as shown in FIG. 16D, after filling the trench portion with the insulating film 60, the ONO film 6 is formed on the entire surface.
1 is formed, and the second-layer polycrystalline silicon film 62 is deposited thereon to a thickness of 200 nm, for example. Subsequently, a resist pattern 63 is formed on the second-layer polycrystalline silicon film 62, and the peripheral Tr
Part and polycrystalline silicon film 62 to be the selected Tr part and ON
The O film 61 is removed by etching. In this example, the polycrystalline silicon film 62 and the ONO film 61 on the ONO film 61 are removed by etching, but they can be formed without etching removal. At this time, it is necessary to partially remove the second-layer polycrystalline silicon film 62 and the ONO film 61 so that the peripheral Tr can directly contact Al with the first-layer polycrystalline silicon film 58. In addition, the second-layer polycrystalline silicon film 62 is formed into 20
After 0 nm deposition, polishing may be performed to make the surface flat.

Then, as shown in FIG. 17E, WS
A low resistance material such as i is deposited in contact with the second-layer polycrystalline silicon film 62. Then, the first and second-layer polycrystalline silicon films 58 and 62, the WSi film 65, and the ONO film 61 are sequentially etched with one resist mask 66. And
By forming a control gate, a floating gate, a selection gate, and a peripheral Tr gate of the memory cell and performing metallization, a structure as shown in FIG. 17F is obtained.
In the figure, 68 is an interlayer insulating film, and 69 is an Al wiring layer.

By using this process, the pattern of the peripheral Tr and the cell portion Tr has been formed in separate processes until now.
This can be formed in one pattern. Further, it is not necessary to process the floating gate, and it can be formed simultaneously with the trench pattern. Due to the above two points, the steps can be largely omitted, and the memory can be formed at low cost. Note that FIG. 18 shows a schematic diagram of the memory cell portion and the peripheral portion.

(Embodiment 5) In the first embodiment, when the semiconductor substrate is dug, high energy particles hit the edge portion of the gate oxide film, which may cause deterioration of the gate oxide film. Further, when the insulator deposited in the trench is etched back, the gate electrode may be charged up, which may cause deterioration of the gate oxide film. In this embodiment, since polycrystalline silicon is connected to the substrate, deterioration due to charge-up is unlikely to occur.

19 to 25 show process sectional views of this embodiment. The left side of FIGS. 19 to 25 corresponds to the DD ′ section in FIG. 9, and the right side corresponds to the EE ′ section.

First, as shown in FIG. 19, after forming two kinds of gate oxide films 13 on a silicon substrate 10, for example, a first layer polycrystalline silicon film 30 is deposited to a thickness of 100 nm, and, for example, a polycrystalline portion of a source portion 71 is formed. The silicon film 30 and the oxide film 13 are selectively removed by etching.

Next, as shown in FIG. 20, for example, the second
Layer polycrystalline silicon film 30 'to 300 nm, CVD-Si
An O ₂ film 19 is deposited to 200 nm. At this time, the second-layer polycrystalline silicon film 30 ′ is the first-layer polycrystalline silicon film 3
0 and the substrate 10 can be formed in electrical contact with each other, and charge-up damage in a future process is released because the charge is discharged to the substrate 10 at this contact portion.

The following steps may be the same as the steps described so far, as shown in FIGS. Incidentally, 37 in the figure is an insulating film which is formed on the polycrystalline silicon film 29 serving as a control gate and used when patterning the film 29.

(Embodiment 6) This embodiment is also a method of reducing damage applied to an oxide film. 26 and 27 show process sectional views. This figure corresponds to the DD ′ cross section of FIG. 9.

In the above embodiments, the oxide film (gate oxide film), the polycrystalline silicon film, the SiO ₂ CVD film is formed on the substrate.
Although the film has three layers, in this embodiment, one conductive layer is further formed to form a total of five layers.

That is, as shown in FIG.
After depositing the first-layer polycrystalline silicon film 15 via the gate oxide film 13 thereon, a polycrystalline silicon film 38 is deposited thereon via the insulating film 39, and the CVD-SiO ₂ film 19 is deposited thereon. accumulate. Then, as shown in FIG.
Using the resist pattern (not shown) provided on the insulating film 19 as a mask, the trenches 11 to 11 are selectively etched.
To form.

Then, as shown in FIG. 27C, the insulating film 12 is buried and formed in the trench 11 by depositing and etching back the insulating film 12. In this embodiment, although the upper conductive film is charged up when it is etched back, the gate oxide film 13 such as the tunnel oxide film is not deteriorated because it is not charged up to the lower layer.

Then, as shown in FIG. 27D, the polycrystalline silicon film 38 and the insulating film 39 are removed. After that,
It is formed through the same steps as described above.

In this embodiment, the same effects as in the previous embodiment can be obtained, and charge-up damage can be avoided without increasing the number of photolithographic masks.

Although the above-described embodiment is mainly concerned with the NAND cell type EEPROM, it is not limited to this, and can be widely applied to semiconductor devices.

(Embodiment 7) FIG. 28A shows a seventh embodiment of the present invention.
28B is a plan view showing the embodiment of FIG.
It is a -A 'sectional view.

In this embodiment, the source 81 and the drain 82 are formed by forming a buried n ⁺ diffusion layer on the side surface and part of the surface of the trench isolation, and the floating gate 30, The control gate 29 is formed. These arrays are formed through the select gates SG (or ST) as shown in FIG. 29A or 29B. The operation is similar to the conventional one.

FIG. 30 shows a modification of this embodiment,
(A) is a plan view and (b) is a sectional view taken along the line AA ′ of (a). Basically, it is similar to FIG. 28, except that only the side surface of the trench is a buried n ⁺ layer.

With such a structure, the region of the buried n ⁺ layer can be reduced, and since the side surface of the floating gate is used for the interpolycrystalline silicon capacitor, writing can be performed at a low voltage. .

[0087]

As described in detail above, according to the present invention, since the slit width of the gate electrode becomes the element isolation width as it is, so-called self-alignment is performed, the distance between each transistor can be reduced, and the high It becomes possible to integrate. In addition, no corner is formed at the end of the element region, and a high breakdown voltage oxide film can be formed. Further, by forming the side wall on the gate electrode, the oxide film edge portion is protected when the trench is dug, so that the breakdown voltage does not deteriorate. Further, since an oxide film thinner than the gate insulating film is formed under the side wall, the dielectric breakdown of the oxide film caused by the charge-up of the gate electrode, which occurs when the insulator buried in the trench is etched. Or the decrease in reliability is
Since the oxide film is thinner than the gate oxide film, damage to the gate oxide film is reduced.

Regarding the nonvolatile semiconductor memory device,
In the case of applying the above-mentioned element isolation method, the etching rate greatly depends on the element isolation width because the rate of gas supply is controlled when etching back the insulator buried in the trench. For example, when the trench width is narrow (that is, the gate width is wide), the etching rate is increased, and the capacitance between the floating gate and the control gate on the floating gate sidewall increases. Also, when the trench width is wide, the opposite is true. This reduces variations in the coupling ratio within the semiconductor substrate.

Further, the coupling ratio can be controlled by adjusting the area of the floating gate side wall portion in accordance with the gate width. Further, since the peripheral circuit transistor and the selection transistor can be formed in the same process as the memory cell, there is an advantage that the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing an element structure of a MOS transistor according to a first embodiment.

FIG. 2 is a sectional view taken along the line AA ′, BB ′ of FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 9 is a plan view showing the element structure of the EEPROM according to the third embodiment.

10 is a sectional view taken along the line AA ′, BB ′ of FIG.

FIG. 11 is a sectional view taken along the line CC ′ of FIG. 9.

FIG. 12 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 14 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 15 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 16 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 17 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 18 is a sectional view showing a configuration of a memory cell portion and a peripheral portion in a fourth embodiment.

FIG. 19 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 20 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 21 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 22 is a sectional view showing the manufacturing process of the fifth embodiment.

FIG. 23 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 24 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 25 is a cross-sectional view showing the manufacturing process of the fifth embodiment.

FIG. 26 is a cross-sectional view showing the manufacturing process of the sixth embodiment.

FIG. 27 is a cross-sectional view showing the manufacturing process of the sixth embodiment.

FIG. 28 is a plan view and a cross-sectional view showing a seventh embodiment.

FIG. 29 is an equivalent circuit diagram of the seventh embodiment.

FIG. 30 is a plan view and a cross-sectional view showing a modified example of the seventh embodiment.

FIG. 31 is a view showing a problem of conventional trench element isolation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... N-type silicon substrate 11 ... Element | device isolation groove | channel (trench) 12 ... Embedded insulating film 13 ... Gate insulating film 15 ... Gate electrode consisting of a 1st layer conductive film 17 ... Element isolation area 18 ... Element area 19 ... CVD insulating film 20 ... Gate Electrode Made of Second Layer Conductive Film 21 ... Gate Electrode Contact 22 ... Source / Drain Electrode 23 ... Source / Drain Diffusion Layer 24 ... Interlayer Insulating Film 29 ... Control Gate 30 Made of Second Layer Conductive Film ... First Layer Floating gate 31 made of conductive film ... Gate insulating film

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location H01L 21/76 29/78 H01L 29/78 301 R (72) Inventor Toru Maruyama Komukai, Kawasaki City, Kanagawa Prefecture TOSHIBA-Cho No. 1 In stock company Toshiba R & D Center (72) Inventor Hiroshi Watanabe Komukai-komukai-ku, Kanagawa Pref. Komukai TOSHIBA-cho No. 1 Inside company Toshiba Research & Development Center (72) Inventor Hemink Gertoyan Kawasaki Kanagawa Komukai Toshiba-cho, Sachi-ku, Yokohama-shi Incorporated company Toshiba Research and Development Center

Claims (6)

[Claims] 1. An element isolation groove formed on a semiconductor substrate so as to surround an island-shaped element formation region, an element isolation insulating film embedded in the groove, and an element isolation region on the substrate. A first-layer conductive film which is formed on a gate insulating film via a gate insulating film and whose both ends are self-aligned with the element-isolating groove, and is formed on the first-layer conductive film and the element-isolating insulating film. A semiconductor device comprising: a second conductive film layer. 2. A first substrate on a semiconductor substrate via a gate insulating film.
A step of forming a layer conductive film, a step of selectively etching the first layer conductive film by using the island pattern as a mask, and a step of selectively etching the substrate to form an element isolation groove, and insulating in the element isolation groove. A step of embedding the film, a step of forming a second-layer conductive film on the entire surface, and a step of selectively etching the second-layer conductive film and the first-layer conductive film using a linear pattern passing over the first-layer conductive film as a mask A method of manufacturing a semiconductor device, comprising: 3. A floating gate made of a first layer conductive film is formed on a semiconductor substrate via a tunnel insulating film, and a control gate made of a second layer conductive film is formed on the floating gate via a gate insulating film. In a semiconductor device in which electrically rewritable non-volatile memory cells are formed by arranging the memory cells in a matrix, an element isolation groove for separating the memory cells is formed in the substrate, and the element isolation groove is formed in the groove. An insulating film for filling is formed, two opposing sides of the floating gate are self-aligned with the isolation trench, and the remaining two sides are self-aligned with the control gate. Semiconductor device. 4. A method of manufacturing a semiconductor device comprising electrically rewritable non-volatile memory cells arranged in a matrix on a semiconductor substrate, comprising: a first layer conductive layer serving as a floating gate on a semiconductor substrate via a tunnel insulating film. A step of forming a film, a step of selectively etching the first-layer conductive film and the tunnel insulating film using the line-shaped pattern as a mask, and a step of selectively etching the substrate to form an element isolation groove; A step of burying an insulating film in the first step, a step of forming a second-layer conductive film to be a control gate on the entire surface through a gate insulating film, and a second line-shaped pattern intersecting the line-shaped pattern of the first conductive film And a step of selectively etching the second-layer conductive film and the first-layer conductive film with the mask as a mask. 5. The semiconductor device according to claim 1, wherein the upper surface of the embedded insulating film is higher than the surface of the substrate and lower than the upper surface of the first-layer conductive film. 6. After the selective etching of the first-layer conductive film and before the selective etching of the element isolation trench, a region of the substrate close to the first-layer conductive film is formed more than an insulating film below the first-layer conductive film. The method for manufacturing a semiconductor device according to claim 2, wherein a thin insulating film is formed, and a conductive material that is electrically connected to the first-layer conductive film is formed on the insulating film.