JP2008235936A - Non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a method of manufacturing the same, both of which are capable of reducing the number of manufacturing processes and has high-speed operability and high reliability. <P>SOLUTION: The non-volatile semiconductor memory device includes a memory cell, having a self-aligned two-layer gate structure which includes a gate insulating film formed on a semiconductor substrate, a first conductor 3 serving as a floating gate layer, a second conductor 7 serving as a control gate layer, and an insulation film 6 for electrically insulating the first conductor and the second conductor. The memory cell unit is constituted by connecting a plurality of the memory cells in series. A gate transistor is connected to the memory cell unit in series. A resistance element is constituted, by using the two-layer gate structure, the first conductor is used as a resistor, and the second conductor and the insulation film are removed, with respect to a region of a part of the first conductor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a non-volatile semiconductor memory device having a two-layer gate structure comprising a gate insulating film, a floating gate layer as a charge storage layer, an insulating film, and a control gate layer, and a method for manufacturing the same, and in particular, a memory cell portion and its peripheral circuit The present invention relates to the structure of the gate insulating film including the portion and the gate electrode.

  The nonvolatile semiconductor memory device includes a memory cell (memory cell transistor) and a selection transistor, and includes a high breakdown voltage (Vpp) transistor, a Vcc transistor that operates with a normal power source, and the like as peripheral circuits (peripheral circuits). Circuit transistor). The gate insulating film of each transistor has a different thickness depending on the voltage to be handled.

  36 (a), (b) to 37 (c), (d) are cross-sectional views showing a manufacturing process of a conventional nonvolatile semiconductor memory device. As shown in FIG. 36A, an N well region 302 and a P well region 303 are formed in a silicon substrate 301, and a sufficiently thick element isolation film 304 is formed by a LOCOS method. The element region separated by the element isolation film 304 includes, for example, a memory cell, a selection transistor (selection Tr), a transistor in a memory peripheral circuit, a high voltage transistor (Vpp Tr), a normal power supply transistor (Vcc system). Tr). First, the gate oxide film 305 in the selective Tr portion is formed. Thereafter, a resist is applied and patterned, the region other than the memory cell portion is covered with the resist 315, the gate oxide film 305 is removed, and a gate oxide film 306 of the memory cell is formed. The notches in the figure indicate that the memory cell and the selected Tr, Vpp-based Tr and Vcc-based Tr are represented by different cross sections.

  Next, as shown in FIG. 36B, a first polysilicon layer 307 is deposited, and after patterning, an insulating film 308 is formed on the surface of the polysilicon layer. The polysilicon layer 307 serves as a floating gate of the memory cell and serves as a gate electrode of the selection transistor. On the transistor part side (Vpp Tr, Vcc Tr) of the peripheral circuit, the insulating film 308, the first layer polysilicon 307, and the gate insulating film 305 thereunder are removed. Thereafter, the resist is patterned to form a gate oxide film 309 in the Vpp Tr portion. Further, as shown in the figure, a new resist 316 is patterned to remove the gate oxide film 309 in the region of the Vcc Tr portion.

  Next, as shown in FIG. 37C, a gate oxide film 310 of the Vcc Tr portion is formed. Thereafter, a second polysilicon layer (gate electrode) 311 is formed. Thereafter, a memory cell, a select transistor, a high breakdown voltage transistor, and a Vcc transistor are formed through patterning of the memory cell and each transistor, an ion implantation process, an interlayer insulating film 312 deposition, a wiring 313 formation process, and the like. (FIG. 37 (d)).

  According to the above configuration, the gate oxide films of the above-described transistors are formed in four types, which are different from 305, 306, 309, and 310, respectively. For this reason, an increase in the number of processes such as resist formation and oxidation processes causes an increase in cost.

  In addition, as described above, the memory cell portion has a two-layer gate structure including a floating gate layer (first polysilicon layer 307) and a control gate layer (second polysilicon layer 311). In the semiconductor memory device, as described with reference to the drawing, the gate electrode of the transistor in the peripheral circuit is usually formed of the control gate layer (second layer polysilicon 311) of the memory cell portion. However, in the manufacture of the peripheral circuit transistors in this case, it is difficult to form both surface channel type N channel and P channel MOS transistors. This will be described below.

  In general, the control gate layer of the memory cell transistor has a polycide structure by depositing a second layer of polysilicon and then laminating, for example, WSi (tungsten silicide) on the polysilicon to further increase the conductivity. Next, a resist is applied and patterning as a gate electrode is performed.

  Here, in the conventional method using the control gate layer as the gate of the transistor of the peripheral circuit, when considering the N channel MOS transistor and the P channel MOS transistor as surface channel type elements advantageous for miniaturization, Before the step of laminating WSi, N-type and P-type impurities must be separately injected into the second polysilicon layer. Further, in order to complete the transistor, it is necessary to stack WSi, and after processing the gate electrode, to distinguish and inject N-type and P-type impurities into the source and drain regions. Therefore, the resist patterning and impurity implantation steps must be increased.

  On the other hand, in view of such a problem, when the gate electrode of the transistor in the peripheral circuit is formed of the first polysilicon layer 307 which becomes the floating gate layer of the memory cell, the same conductivity type as the source region and the drain region is obtained after the gate electrode processing. It is possible to obtain a surface channel type element by injecting impurities into the gate electrode. However, since the first polysilicon layer 307 serving as a floating gate layer usually has a higher resistance than the second polysilicon layer 311 serving as a control gate layer, in this case, in the transistor of the peripheral circuit High-speed operation will be hindered.

Prior art document information related to the invention of this application includes the following.
Japanese Unexamined Patent Publication No. 07-130893

  As described above, in the prior art, the gate insulating films of the transistors in the memory cell portion and the peripheral circuit portion have different thicknesses, which increases the number of manufacturing steps and increases the cost. In order to increase the operation speed, the gate of the transistor in the peripheral circuit of the memory generally has the same polycide structure as the control gate layer of the conventional memory cell unit. However, the transistor in the peripheral circuit has such a polycide structure. If a surface channel type device is to be realized as the gate of this, the steps of resist patterning and impurity implantation increase, and the manufacturing cost increases.

  In view of the above circumstances, it is an object of the present invention to provide a nonvolatile semiconductor memory device having a reduced number of manufacturing steps and having high-speed operation and high reliability and a method for manufacturing the same. .

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a gate insulating film, a first conductor serving as a floating gate layer, a second conductor serving as a control gate layer, and a second conductor formed over a semiconductor substrate. A memory cell having a self-aligned two-layer gate structure comprising an insulating film that electrically insulates the first conductor and the second conductor, and a plurality of the memory cells are connected in series A memory cell unit; a select gate transistor connected in series to the memory cell unit; and a resistance element using the two-layer gate structure, wherein the first conductor is a resistor. And the second conductor and the insulating film are removed with respect to a part of the region on the first conductor.

According to this invention, to simplify the manufacturing process, lowering the production cost, and the transistor of the peripheral circuit can be salicide structure or polymetal gate, as peripheral circuits of the memory, is embedded in the high-speed CMOS circuits A nonvolatile semiconductor memory device and a method for manufacturing the same can be provided.

  FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. An N well 102 and a P well 103 are selectively formed on a P type silicon substrate 101. In a region constituting the memory cell array, a P well 103 is formed in the surface of the N well 102. A thick element isolation film 104 is selectively formed on the silicon substrate 101 by the LOCOS method. The element region separated by the element isolation film 104 is divided into, for example, memory cells, a selection transistor (selection Tr), a high breakdown voltage transistor (Vpp Tr), and a normal power supply transistor (Vcc Tr). Note that the notches in the figure indicate that the memory cell, the selected Tr, the Vpp Tr, and the Vcc Tr are shown in different cross sections, as in FIG.

The memory cell and the selection Tr have the same gate insulating film 105 as the Vcc Tr. A first polysilicon layer 106 serving as a floating gate layer and a second polysilicon layer 107 serving as a control gate layer are stacked on the gate insulating film 105. An insulating film 109 is formed between the first polysilicon layer 106 and the second polysilicon layer 107. The insulating film 109 is, for example, a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film (ONO film). In the selection Tr, there is a portion where the first polysilicon layer 106 is directly connected to the metal wiring member 112a. In the memory cell, the first polysilicon layer 106 (floating gate layer) serves as a charge storage layer, and programming and erasing are performed by transferring charges in the charge storage layer under the control of the second polysilicon layer (control gate layer) 107. A single memory cell or a plurality of these memory cells are connected to form a memory cell unit. FIG. 1 is a cross section of an array of memory cells having a common control gate (second polysilicon layer 107). For example, when the present invention is applied to a NAND-type EEPROM, a predetermined number of memories arranged in a direction perpendicular to the cross section. A cell constitutes a memory cell unit. Each memory cell unit is connected to at least one selection transistor (shown as selection Tr), and a plurality of the memory cell units are arranged to constitute a memory cell array (not shown).

  The high breakdown voltage transistor (Vpp Tr) and the normal power supply transistor (Vcc Tr) are shown here as transistors that drive and control the voltages that control the memory cells and the selection Tr.

  The gate insulating film 108 of Vpp Tr is formed thicker than the gate insulating film 105 of Vcc Tr. That is, the other gate insulating films of the memory cell, the selection Tr, and the peripheral Vcc-based Tr are the gate insulating film 105 formed by a common process, and are substantially the same film.

  The first polysilicon layer 106 is used for all gate electrodes of the Vpp Tr and Vcc Tr. On the first polysilicon layer 106, for example, a highly doped second polysilicon layer (control gate layer) 107 is formed. A member formed on the first polysilicon layer 106 of the gate electrode of the Vpp Tr and Vcc Tr is a material different from the second polysilicon layer (control gate layer) 107, for example, salicide or metal. Also good.

An opening is selectively formed in the interlayer insulating film 110 formed on the entire surface of the substrate, and the gate of the selected Tr or the source and drain diffusion layers (N ⁺ diffusion layer, P ⁺ diffusion layer) of the Vpp Tr and Vcc Tr And the metal wiring member 112 are electrically connected.

  According to the above configuration, it can be expected that the types of gate insulating films are made as common as possible and the step of oxidizing the peripheral transistors is omitted. As a result, a nonvolatile semiconductor memory device with reduced manufacturing costs is realized. Hereinafter, the manufacturing method will be described.

  2A to 2C are cross-sectional views showing the manufacturing method having the configuration shown in FIG. 1 in the order of steps. First, as shown in FIG. 2A, an N well 102 and a P well 103 are selectively formed on a silicon substrate 101. Next, an element isolation film 104 having a thickness of about 300 nm is selectively formed on the silicon substrate 101 by the LOCOS method. Next, a gate insulating film 108 of Vpp Tr (high voltage transistor) is formed to 40 nm, for example. Thereafter, the region where the Vpp Tr is to be formed is covered with a resist 115, and the gate insulating film 108 in other regions is removed. Next, a region other than the Vpp Tr, that is, the gate insulating film 105 in each part of the memory cell, the selection Tr, and the Vcc Tr is formed to 8 nm, for example.

After removing the resist 115, a first polysilicon layer 106 is deposited on the gate insulating films 105 and 108 as shown in FIG. After patterning the memory cell portion, an insulating film 109 of a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film (ONO film) is formed on the first polysilicon layer 106.

  Next, as shown in FIG. 2C, after the insulating film 109 in the transistor portion of the peripheral circuit is removed, a second polysilicon layer 107 is deposited. Thereafter, the configuration of FIG. 1 is achieved through patterning, ion implantation, interlayer insulating film deposition, wiring formation, and the like.

  In the above embodiment, as described above, the type of the gate insulating film can be actively shared, and the gate oxidation process of the peripheral circuit transistor can be simplified. In this example, the gate oxide film 108 of the high breakdown voltage transistor and the other gate oxide film 105 are two types. However, the present invention is not limited to this. For example, the gate insulating film of the memory cell and the Vcc transistor may be the same or different. The gate insulating film of the selection transistor and the Vpp transistor may be the same film.

3 and 4 show a modification of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
3 differs from FIG. 1 in that the gate insulating film of the selected Tr is substantially the same as the gate insulating film 108 of the Vpp Tr. For example, the gate insulating film 108 of the selected Tr and the Vpp-based Tr is formed to 40 nm, and the gate insulating film 105 in each region of the memory cell and the Vcc-based Tr is formed to 8 nm.

  The configuration of FIG. 4 is different from the configuration of FIG. 3 in that the gate insulating film of each part of the Vcc Tr is different from the gate insulating film 105 of the memory cell (gate insulating film 118). For example, the gate insulating film 108 of the selected Tr and the Vpp-based Tr is formed to be substantially the same 40 nm, the gate insulating film 105 of the memory cell is formed to 8 nm, and the gate insulating film 118 of each part of the Vcc-based Tr is formed to 12 nm.

  In the configuration of FIG. 4, the gate insulating film of the selection Tr and the Vpp-based Tr is substantially the same film. However, as another configuration, the gate insulating film of each part of the selection Tr and the Vcc-based Tr is substantially the same film. The gate insulating film of the cell may be different from the gate insulating film of the Vpp Tr.

  Also in the above, as in the case of FIG. 1, since the types of the gate insulating films are positively shared, the gate oxidation step of the peripheral circuit transistor can be omitted. Note that, as described above, particularly when the gate insulating film of the selection transistor and the peripheral circuit transistor are the same film, the selection transistor has fewer restrictions on the transistor characteristics than the memory cell transistor. The degree of freedom with respect to the thickness of the insulating film is not so much impaired, and this is advantageous in achieving high-speed operation by optimizing the gate insulating film of the peripheral circuit transistor.

  Further, in the present invention, the process is complicated in order to increase the speed of the peripheral circuit transistor by using the first conductor layer (floating gate layer) of the memory cell as the gate electrode of the peripheral circuit. There is no advantage. That is, it is possible to easily make the transistors of the peripheral circuit salicide or polymetal gate. This will be described below based on this.

  5 to 16 are sectional views showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention in the order of the manufacturing steps. Here, a non-volatile semiconductor memory device having a two-layer gate structure, in which the control gate has a laminated structure of, for example, polysilicon / WSi, the gate electrode of a peripheral transistor is formed with a salicide structure using a floating gate layer of a memory cell. Thus, a structure and a method for speeding up peripheral transistors will be described. In each figure, (a) is a cross-sectional view of a memory cell portion, (b) is a cross-sectional view of an N-channel transistor in a peripheral circuit, and (c) is a cross-sectional view of a P-channel transistor in the peripheral circuit.

  First, as shown in FIG. 5, an N-type substrate region and a P-type substrate region in which an N well and a P well are formed by impurity implantation or the like are prepared for a semiconductor substrate. The element isolation film 1 is formed by a selective oxidation method or the like. Next, a gate oxide film 2 (insulating film) is formed on the activated region by performing gate oxidation or the like. Next, a first polysilicon layer 3 to be a floating gate layer is deposited. Thereafter, if necessary, the polysilicon layer 3 is doped with an N-type impurity by a phosphorus diffusion method or the like. Alternatively, a polysilicon layer 3 containing impurities in advance may be deposited. Although not shown, a process for forming a cell / slit in the polysilicon layer 3 of the memory cell portion (a) corresponding to the planar pattern of the memory cell unit of the nonvolatile semiconductor mechanism device to be manufactured later is performed. Done.

Thereafter, as shown in FIG. 6, an insulating film (ONO film) 6 made of, for example, SiO ₂ / Si ₃ N ₄ / SiO ₂ is deposited. Next, a second polysilicon layer 7 serving as a control gate layer is deposited and doped with N-type impurities. In this step, a polysilicon layer 7 containing impurities in advance may be deposited. Next, in order to increase conductivity as the control gate layer, for example, WSi is deposited on the second polysilicon layer 7 (not shown). Further, a SiN film 8 is deposited as a mask material on the control gate layer (polysilicon layer 7).

  Thereafter, as shown in FIG. 7, a resist 9 is applied and patterned. Next, after the SiN film 8 is etched by anisotropic etching (memory cell portion (a)), the resist is removed. Next, as shown in FIG. 8, the control gate layer (polysilicon layer 7) is etched by anisotropic etching using the SiN film 8 as a mask, and then the ONO film 6 is etched. At this time, the memory cell portion (a) has a structure in which the gate is processed up to the ONO film 6, and the peripheral portions (b) and (c) have a structure in which the floating gate layer is exposed.

  Thereafter, as shown in FIG. 9, a resist 10 is applied and patterned. Next, the floating gate layer (first polysilicon layer 3) is etched by anisotropic etching using the SiN film 8 for the memory cell portion (a) and the resist 10 for the peripheral portions (b) and (c). To do. Thereafter, the resist is removed.

Next, as shown in FIG. 10, a resist is applied, and the resist 11 is patterned so that the memory cell portion (a) and the N-channel type transistor (b) are exposed, and an LDD (Lightly Doped Drain) structure is formed. The resist is removed by doping an N-type impurity which becomes N ⁻ .

After that, as shown in FIG. 11, a resist is applied, the resist 12 is patterned so that the P-channel type transistor of (c) is exposed, and a P-type impurity that becomes P ^{− of} the LDD structure is doped, and the resist is formed. Remove.

  Thereafter, as shown in FIG. 12, after depositing a SiN film, anisotropic etching is used to form the SiN film (SiN film 13) on the gate side walls of the memory cell and peripheral circuit transistors. Next, a resist is applied, the resist 14 is patterned so that the P-channel transistor side of (c) is exposed, P-type impurities are doped, and the resist is removed.

  Thereafter, as shown in FIG. 13, a resist is applied, the resist 15 is patterned so that the memory cell and the N channel type transistor are exposed, an N type impurity is doped, and the resist is removed. Thereafter, high-temperature annealing is performed to activate the impurities.

After that, as shown in FIG. 14, the oxide film (insulating film) 2 on the source and drain regions of the transistor is removed, so that silicon is exposed. Thereafter, for example, a Ti / TiN film 16 is deposited by sputtering and reacted with silicon by high-temperature annealing. Thereafter, the unreacted Ti / TiN film is removed and high-temperature annealing is performed again to form a silicide film 17 to complete the salicide structure (FIG. 15).
Through the above steps, as shown in FIGS. 15A, 15B, and 15C, the source, drain, and gate of the transistor in the memory cell portion or the peripheral portion are completed. The silicide film 17 which has become salicide is lower than the sheet resistance of the underlying polysilicon layer 3 and of course has a low resistivity. Thereby, the structure of a high-speed CMOS circuit can be expected.

  Thereafter, although not shown, an interlayer insulating film is deposited and formed, and through various processes such as contact hole opening, wiring formation, and protective film deposition, the nonvolatile semiconductor memory device is completed.

  If the element structure needs to be planarized due to miniaturization, a dummy pattern DMY having the same double-layer gate structure as the memory cell is formed on the element isolation region in the vicinity of the peripheral transistor as shown in FIG. .

  According to the above embodiment, since the gate oxide film is shared with the memory cell and the peripheral transistor, the number of manufacturing steps such as resist formation and oxidation steps can be reduced. In this example, although not shown, if there are a select transistor of the memory cell and a high breakdown voltage transistor of the peripheral circuit, these gate insulating films are the same film and are thicker than the gate oxide film 2 (insulating film). Alternatively, as in the first embodiment, only the gate insulating film of the high breakdown voltage transistor is different, and the selection transistor of the memory cell may be configured to use the gate oxide film 2. In short, a combination that can reduce the number of manufacturing steps such as an oxidation step may be adopted.

  Further, since the first polysilicon layer (floating gate layer) is used for the gate electrode of the peripheral circuit transistor and the salicide structure is adopted, the surface channel type MOS transistor of the surface channel type MOS transistor can be used regardless of the deposition of WSi on the control gate layer. Can be formed. That is, in FIGS. 10B and 10C to FIG. 13B and FIG. 13C, both N-channel and P-channel MOS transistors are reliably implanted with impurities of the same conductivity type as the source and drain regions. The surface channel type is obtained, and then the salicide structure (FIG. 15) is obtained. Therefore, it is possible to realize a high-performance nonvolatile semiconductor memory device in which the peripheral circuit transistors are increased in speed by a manufacturing method in which the flow of resist patterning and impurity implantation steps is not complicated. Note that the metal sputtered on silicon for forming the salicide structure is not limited to Ti / TiN, and another metal may be used.

  FIG. 17 is a cross-sectional view showing a third embodiment of the present invention, and shows a structure using a floating gate layer (first polysilicon layer 3) as a high resistance element. That is, the gate electrode of the transistor of the memory peripheral circuit in the nonvolatile semiconductor memory device having the two-layer gate structure is configured using the floating gate layer of the memory cell, and the floating gate layer is used as a high resistance element in the peripheral element portion. Also used.

  Specifically, up to the floating gate layer is formed as in the second embodiment (see FIG. 5). Thereafter, if necessary, an impurity is doped in the peripheral region. That is, although not shown in the figure, after applying a resist and patterning the resist so that a region to be a resistance element in the peripheral portion is exposed, a desired impurity is doped and the resist is removed.

  Thereafter, similarly to the second embodiment, the SiN film 8 on the control gate layer is deposited (see FIG. 6). Thereafter, although not shown, a resist is patterned on the memory cell portion and the resistance element, and the SiN film 8 is processed by anisotropic etching. At this time, with respect to the resistance element, the resist is patterned so that the resist remains on the resistance element excluding the region to be contacted.

  Next, similarly to the second embodiment, the control gate layer and ONO film are processed by anisotropic etching using the SiN film 8 as a mask, and the resist is removed. Thereafter, although not shown, a resist is applied and patterned, and the gate electrode of the peripheral transistor and the contact region of the resistance element are used as a mask, and the remaining region of the memory cell portion and the resistance element is used as a mask using the SiN film as a mask. The floating gate layer is processed by anisotropic etching. Thereafter, the resist is removed.

Further, the source region and the drain region of the transistor are formed in the same manner as in the second embodiment. Thereafter, salicide is formed.
Through the above steps, the source, drain, and gate of the transistor as shown in FIG. 15 and the resistance element as shown in FIG. 17 are completed. Thereafter, an interlayer insulating film 19 is deposited and formed through various processes such as contact hole opening, wiring formation, protective film deposition, and the nonvolatile semiconductor memory device is completed.

  FIG. 17 also shows the interlayer insulating film 19 and the metal wiring 20 formed in this step. The remaining second polysilicon layer 7 provides a certain height that matches the height of the surrounding element structure, and thus contributes to planarization of the interlayer insulating film 19.

  If the element structure needs to be planarized due to miniaturization, a dummy pattern DMY having the same two-layer gate structure as the memory cell is formed on the element isolation region in the vicinity of the peripheral transistor as shown in FIG. .

Note that the metal sputtered on silicon for forming the salicide structure is not limited to Ti / TiN, and another metal may be used.
Further, the processing of the gate electrode and the resistance element of the transistor in the peripheral circuit may be performed after the processing of the memory cell portion is completed without performing the processing of the memory cell portion as in the above method.

  Next, as a fourth embodiment, a method of processing the gate electrode and the resistance element of the peripheral transistor after processing the memory cell portion will be described with reference to FIGS. 18 and 19 and a part of the second embodiment.

  First, in the same manner as in the second embodiment, in the memory cell portion (a), gate processing is performed up to the ONO film 6 or the second polysilicon layer 7 as shown in FIG. At this time, although not shown, the resistance element is processed up to the ONO film 6 or the second polysilicon layer 7 as in the third embodiment.

  After the above gate processing, as shown in FIG. 18, a resist 31 is formed in the transistors (b) and (c) of the peripheral circuit. Next, the floating gate layer (first polysilicon layer 3) in the memory cell portion is etched by anisotropic etching. Thereafter, the resist is removed.

  Thereafter, as shown in FIG. 19, a resist 32 is applied and patterned, and the floating gate layers in the peripheral portions (b) and (c) are etched by anisotropic etching. At this time, although not shown in the figure, as for the resistance element, as in the third embodiment, the contact region of the resistance element is used as a resist, and the remaining area of the resistance element is used as a mask with the SiN film as a mask. Is processed by anisotropic etching. Thereafter, the resist is removed. Further, similarly to the second embodiment, a source region and a drain region of the transistor are formed, and then a salicide structure is formed. FIGS. 18 and 19 show an example in which up to the second polysilicon layer 7 is removed in the peripheral portions (b) and (c) during the gate processing in the memory cell portion (a). In this case, when the oxide film (insulating film) 2 on the source region and the drain region is removed before the salicide is formed, the ONO film 6 remaining on the gate is also removed.

  Through the above steps, the source, drain and gate of the transistor as shown in FIG. 15 and the resistance element as shown in FIG. 17 are completed. Thereafter, an interlayer insulating film is deposited and formed through various steps such as contact hole opening, wiring formation, protective film deposition, and the nonvolatile semiconductor memory device is completed. FIG. 17 also shows an interlayer insulating film and wiring formed in the subsequent process.

  If the element structure needs to be planarized due to miniaturization, a dummy pattern DMY having the same two-layer gate structure as the memory cell is formed on the element isolation region in the vicinity of the peripheral transistor as shown in FIG. .

  Note that the metal sputtered on silicon for forming the salicide structure is not limited to Ti / TiN, and another metal may be used.

  Next, referring to FIGS. 20, 21 and a part of the fourth embodiment as the fifth embodiment, the floating gate layer of the memory cell is used for the gate electrode of the transistor of the peripheral circuit. A configuration in which peripheral transistors are speeded up by using, for example, a polymetal gate of polysilicon / W (tungsten) will be described.

In the fifth embodiment, a method of processing the gate electrode and the resistance element of the peripheral transistor after processing the memory cell portion will be described.
First, in the same manner as in the fourth embodiment, processing is performed as shown in FIG. Next, after doping an N-type impurity for forming a source region and a drain region of the memory cell portion (a), the resist 31 is removed.

Here, when the LDD structure is required in the doping of the N-type impurity, the N-type impurity is set to a doping amount that becomes N ⁻ of the LDD structure. Next, although not shown, after depositing the SiN film, the resist the coated and patterned such that the memory cell unit (a) is exposed by anisotropic etching, the SiN etching to form the SiN gate sidewall of the memory cell portion is left, the previous N ^- higher The resist 31 is removed after doping with N-type impurities at a concentration.

  Thereafter, although not shown, after depositing SiN, applying a resist, and patterning, the SiN and ONO film 6 in the peripheral portion are removed by etching, the resist is removed, and the memory cell portion is protected by the SiN film 24 ( (Illustrated in FIG. 20).

  After that, as shown in FIG. 20, for example, a W film 18 is stacked, a resist is applied, and patterning is performed (resist 32). Next, the W film 18 in the peripheral portion is etched by anisotropic etching, and then the floating gate layer (first polysilicon) 3 is etched. Thereafter, the resist 32 is removed.

  Thereafter, similarly to the second embodiment, the source region and the drain region of the peripheral transistor are formed. Through the above steps, the source, drain, and gate of the transistor are completed as shown in FIG.

  If the element structure needs to be planarized due to miniaturization, a dummy pattern DMY having the same two-layer gate structure as the memory cell is formed on the element isolation region in the vicinity of the peripheral transistor as shown in FIG. .

Thereafter, an interlayer insulating film is deposited and formed through various steps such as contact hole opening, wiring formation, protective film deposition, and the nonvolatile semiconductor memory device is completed. The metal for forming the polymetal gate is not limited to W as long as the sheet resistance and resistivity are lower than those of the first polysilicon layer 3, and another metal may be used.
As described above, in the fourth and fifth embodiments, the processing of the gate electrode of the transistor in the peripheral circuit is not performed simultaneously with the gate processing of the memory cell portion. The number of manufacturing processes increases slightly. However, by using the first conductive layer (floating gate layer) of the memory cell as the gate electrode of the peripheral circuit, the type of gate insulating film is positively selected between the memory cell transistor or the select transistor and the peripheral circuit transistor. Therefore, it is possible to reduce the number of manufacturing steps by omitting the number of gate oxidation steps for peripheral circuit transistors to some extent.

  In the first to fifth embodiments so far, the element isolation method has been a selective oxidation method such as a LOCOS method, but is not limited thereto. There is another method such as STI (Shallow Trench Isolation) technique, which will be described below.

  FIG. 23 is a sectional view showing a nonvolatile semiconductor memory device according to the sixth embodiment of the present invention. The difference from FIG. 1 is that an element isolation film using STI (Shallow Trench Isolation) technology is used. Also, WSi 201 is stacked on the second polysilicon layer 107 in the control gate layer of the memory cell portion, while the gate electrodes of the transistors (Vpp Tr, Vcc Tr) of the peripheral circuit are on the first polysilicon layer 106. The structure is different from that of FIG. 1 in that it has a polymetal gate structure in which W (tungsten) 202 is formed.

  Also in the sixth embodiment, similarly to the first embodiment, the gate insulating film 105 commonly used by the memory cell transistor, the selection Tr, and the Vcc Tr and the gate insulation of the high breakdown voltage transistor (Vpp Tr) are used. Two types of gate insulating films are formed with the film 108.

  According to the above configuration, as in the first embodiment, it can be expected that the type of the gate insulating film is positively shared and the step of oxidizing the peripheral transistors is omitted. As a result, a nonvolatile semiconductor memory device with reduced manufacturing costs is realized. Hereinafter, the manufacturing method will be described.

24A to 24C are cross-sectional views showing the manufacturing method of the configuration of FIG. 23 in the order of steps.
First, as shown in FIG. 24A, an N well 102 and a P well 103 are selectively formed on a silicon substrate 101. Next, a gate insulating film 108 of Vpp Tr (high voltage transistor) is formed on the silicon substrate 101, for example, 40 nm. Thereafter, the region where the Vpp Tr is to be formed is covered with a resist 115, and the gate insulating film 108 in other regions is removed.

  Next, as shown in FIG. 24B, a region other than the Vpp Tr, that is, the gate insulating film 105 in each portion of the memory cell, the selection Tr, and the Vcc Tr is formed to 8 nm, for example. After removing the resist 215, a first polysilicon layer 106 is deposited on the gate insulating films 105 and 108. Next, a resist 216 is patterned on the first polysilicon layer 106 in accordance with element isolation. Using this resist 216 as a mask, a trench 217 reaching the substrate by the STI method is formed.

Next, as shown in FIG. 24C, the trench 217 is embedded with an insulating film 218 such as TEOS (Tetraethoxysilane). Next, an insulating film 109 of a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film (ONO film) is formed on the insulating film 218 and the first polysilicon layer 106. After selectively removing the insulating film 109 in the selected Tr and the Vpp Tr and Vcc Tr portions of the peripheral circuit, a stacked structure of the second polysilicon layer 107 and the WSi 201 is deposited. Thereafter, although not shown, the resist is patterned to remove the second polysilicon layer 107 and WSi 201 in the transistor portion of the peripheral circuit.

  Next, although not shown, gate processing of the memory cell and selection Tr and ion implantation into the source region and the drain region are performed. Next, W (tungsten) 202 is laminated on the first polysilicon 106 of the Vpp Tr and Vcc Tr of the peripheral circuit while protecting the memory cell and the selected Tr side. Thereafter, a resist is applied and patterned, and W202 is performed by anisotropic etching, and then the first polysilicon layer 106 is etched. After that, the configuration of FIG. 23 is achieved through the formation of the source region and drain region of each transistor of the Vpp Tr and Vcc Tr of the peripheral circuit, the entire wiring process, and the like.

  Also in the above-described embodiment, the type of gate insulating film can be actively shared, and the gate oxidation process of the peripheral circuit transistor can be simplified. Also in this example, other combinations are conceivable, for example, the gate insulating film of the memory cell and the Vcc transistor are made the same film, and the gate insulating film of the selection transistor and the Vpp transistor is made the same film.

  Further, by using the first conductor layer (floating gate layer) of the memory cell for the gate electrode of the peripheral circuit, there is an advantage that the process is not complicated in order to increase the speed of the transistor of the peripheral circuit. Hereinafter, the case where the peripheral circuit transistor has a salicide structure will be described as an example.

  25 to 28 are cross-sectional views showing the nonvolatile semiconductor memory device according to the seventh embodiment of the present invention in the order of the manufacturing steps. Here, as in the sixth embodiment, an element isolation film using STI (Shallow Trench Isolation) technology is used. In the nonvolatile semiconductor memory device having a two-layer gate structure, the control gate has a laminated structure of, for example, polycrystalline silicon / WSi, and the gate electrode of the peripheral transistor is formed with the salicide structure using the floating gate layer of the memory cell. Thus, a structure and a method for speeding up peripheral transistors will be described. In each figure, (a) is a cross-sectional view of a memory cell portion, (b) is a cross-sectional view of an N-channel transistor in the peripheral circuit, and (c) is a cross-sectional view of a P-channel transistor in the peripheral circuit.

  First, as shown in FIG. 25, an N-type substrate region and a P-type substrate region in which an N well and a P well are formed by impurity implantation or the like are prepared for a semiconductor substrate. A gate oxide film 2 (insulating film) is formed on the substrate by performing gate oxidation or the like. Next, a first polysilicon layer 3d to be a floating gate layer is deposited. Thereafter, if necessary, the polysilicon is doped with an N-type impurity by a phosphorus diffusion method or the like. Alternatively, polysilicon containing impurities in advance may be deposited. Next, a SiN film 21 is deposited as a mask material. Next, although not shown, a resist is applied, patterning is performed, the SiN film 21 on the element isolation region is removed by anisotropic etching, and the resist is removed. Using the remaining SiN film 21 as a mask, the polysilicon layer 3d, the gate oxide film 2, and the semiconductor substrate are sequentially etched by anisotropic etching to form a trench 200 in the semiconductor substrate.

  Next, as shown in FIG. 26, for example, an insulating film 22 such as TEOS is deposited by the CVD method, and planarized by CMP (Chemical Mechanical Polishing) or the like, and the insulating film 22 on the SiN film 21 is removed. . Thus, the insulating film 22 is buried in the trench 200.

  Thereafter, as shown in FIG. 27, the SiN film 21 is removed by wet etching, and a first polysilicon layer 3e to be a floating gate layer is deposited again. Thereafter, if necessary, the polysilicon is doped with an N-type impurity by a phosphorus diffusion method or the like. Next, although not shown, a resist is applied, patterning is performed so as to form cell slits in the memory cell (a), the first polysilicon is removed by anisotropic etching, and the resist is removed.

  27 is the same as the structure shown in FIG. 5 except that the element isolation region has a trench shape and the polysilicon layer on the active region has a laminated structure of 3d and 3e. It is.

  Thereafter, transistors are formed by the same method as the manufacturing process shown in the second embodiment. That is, as shown in FIG. 28, the gate electrode of the transistor in the peripheral circuit has a salicide structure using the floating gate (first polysilicon 3d, 3e) of the memory cell.

  In this example as well, although not shown, if there are a memory transistor selection transistor and a peripheral circuit high breakdown voltage transistor, the gate insulating film is the same film and is more than the gate oxide film 2 (insulating film). A thick film may be used, and only the gate insulating film of the high breakdown voltage transistor is different as in the sixth embodiment, and the gate oxide film 2 may be used as the selection transistor of the memory cell. That is, a combination that can reduce the number of manufacturing steps such as an oxidation step may be employed.

  Further, in the case where the transistor is formed, if the element structure needs to be flattened due to miniaturization, as shown in FIG. 29, the element isolation region in the vicinity of the transistor in the peripheral circuit is formed in the same manner as the memory cell. A dummy pattern DMY having a layer gate structure is formed. Thereafter, although not shown, the nonvolatile semiconductor memory device is completed through various processes such as interlayer insulating film formation, contact term opening, wiring formation, and protective film deposition.

  FIG. 30 is a cross-sectional view of a state in which a dummy pattern DMY as shown in FIG. 29 is formed on an element isolation region adjacent to a transistor in a peripheral circuit of the memory, an interlayer insulating film 23 is stacked, and then planarized by CMP or the like. It is. FIG. 31 is a cross-sectional view showing the difficulty of flattening when the dummy pattern DMY is not formed. That is, the flatness of the element structure is improved by forming the dummy pattern DMY on the element isolation region adjacent to the transistor in the peripheral circuit of the memory.

  Although the case where the present invention is applied to a NAND type EEPROM has been described above, the nonvolatile semiconductor memory device according to the present invention is used not only for the NAND type but also for the NOR type, the DINOR type, the AND type, and the like. Can do. Hereinafter, an EEPROM to which the present invention can be applied will be described.

  FIG. 32 is a circuit diagram of a memory cell array of a NAND type EEPROM. As shown in the figure, in a NAND type EEPROM, a bit line side select gate (SG1), a memory cell group (memory cell unit) connected in series with each other, and a source line between a bit line BL and a source line VS. A side select gate (SG2) is connected in series. The selection gates of the selection transistors represented by SG1 and SG2 and the control gates of the memory cells represented by CG are connected to a selection transistor and a peripheral circuit transistor (not shown) for driving and controlling a voltage for controlling the memory cell, respectively.

  FIG. 33 is a circuit diagram of a NOR type EEPROM memory cell array. As shown in the figure, in a NOR type EEPROM, a bit line side select gate (SG) and one memory cell are connected in series between a bit line BL and a source line VS extending in a direction perpendicular to the bit line BL. Connected to. A selection gate of each selection transistor represented by SG and a control gate of each memory cell represented by CG are connected to a selection transistor and a peripheral circuit transistor (not shown) for driving and controlling a voltage for controlling the memory cell.

  FIG. 34 is a circuit diagram of a memory cell array of a DINOR (Divided NOR) type EEPROM. As shown in the figure, in the DINOR-type EEPROM, memory cells are connected in parallel between one sub bit line (sub BL) and a plurality of source lines VS. The sub bit line (sub BL) is connected to the bit line BL via the bit line selection gate (SG). A selection gate of each selection transistor represented by SG and a control gate of each memory cell represented by CG are connected to a selection transistor and a peripheral circuit transistor (not shown) for driving and controlling a voltage for controlling the memory cell.

  FIG. 35 is a circuit diagram of a memory cell array of an AND type EEPROM. As shown in the figure, in the AND type EEPROM, a bit line side select gate (SG1), a memory cell group (memory cell unit) connected in parallel to each other, and a source line between a bit line BL and a source line VS. A side select gate (SG2) is connected in series. The selection gates of the selection transistors represented by SG1 and SG2 and the control gates of the memory cells represented by CG are connected to a selection transistor and a peripheral circuit transistor (not shown) for driving and controlling a voltage for controlling the memory cell, respectively.

  As described above in each embodiment, the feature of the nonvolatile semiconductor memory device of the present invention is that, firstly, the configuration in which the gate oxide film is shared with the memory cell and the peripheral transistor is positively adopted. Yes. This reduces the number of manufacturing processes such as resist formation and oxidation processes. Second, the first polysilicon layer (floating gate layer) is used for the gate electrode of the transistor in the peripheral circuit. Accordingly, the salicide structure can be employed without complicating the process regardless of the lamination of the conductor (for example, WSi) on the control gate layer. That is, compared to the case where the control gate layer is used for the gate electrode of the peripheral circuit transistor, the gate oxidation step of the peripheral circuit transistor can be omitted, and the impurity implantation into the source region, drain region, and gate electrode can be performed simultaneously. The steps of resist patterning and impurity implantation for the gate electrode, which are necessary for making the peripheral circuit transistor a surface channel type, can be omitted. In addition, a polymetal gate structure in which other conductors are stacked can be employed regardless of the deposition of WSi on the control gate layer. These configurations speed up the operation of the peripheral circuit transistors. Thirdly, the first polysilicon layer can be used as a high resistance element while increasing the speed of the peripheral circuit transistor.

1 is a cross-sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. (A)-(c) is sectional drawing which shows the manufacturing method of the structure of FIG. 1 in order of a process. Sectional drawing which shows the 1st modification of the non-volatile semiconductor memory device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the 2nd modification of the non-volatile semiconductor memory device which concerns on 1st Embodiment of this invention. The 1st sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 2nd sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 3rd sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. FIG. 14 is a fourth cross-sectional view showing the middle of the manufacturing process of main parts of the nonvolatile semiconductor memory device according to the second embodiment of the invention. The 5th sectional view showing the middle of the manufacturing process of each part of the principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 6th sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 7th sectional view showing the middle of the manufacture process of each part of the principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. FIG. 15 is an eighth cross-sectional view showing the middle of the manufacturing process of main parts of the nonvolatile semiconductor memory device according to the second embodiment of the invention. The 9th sectional view showing the middle of the manufacture process of each part of the important section in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 10th sectional view showing the middle of the manufacture process of each part of the principal part in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. The 11th sectional view showing the middle of the manufacturing process of each part of the important section in the nonvolatile semiconductor memory device concerning a 2nd embodiment of this invention. FIG. 13 is a twelfth cross-sectional view showing a part of the manufacturing process in the nonvolatile semiconductor memory device according to the second embodiment of the invention. Sectional drawing which shows the structure of the principal part which concerns on 3rd Embodiment of this invention. The 1st sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 4th embodiment of this invention. The 2nd sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 4th embodiment of this invention. The 1st sectional view showing the middle of the manufacturing process of each principal part in the nonvolatile semiconductor memory device concerning a 5th embodiment of this invention. The 2nd sectional view showing the middle of the manufacture process of each part of the principal part in the nonvolatile semiconductor memory device concerning a 5th embodiment of this invention. FIG. 15 is a third cross-sectional view showing a part of the manufacturing process in the nonvolatile semiconductor memory device according to the fifth embodiment. Sectional drawing which shows the non-volatile semiconductor memory device concerning 6th Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the structure of FIG. 23 in order of a process. The 1st sectional view showing the middle of the manufacturing process of the principal part of the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. The 2nd sectional view showing the middle of the manufacturing process of the principal part of the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. The 3rd sectional view showing the middle of the manufacturing process of the principal part of the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. The 4th sectional view showing the middle of the manufacture process of each part of the important section in the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. The 5th sectional view showing the middle of a part of manufacturing process in the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. The 6th sectional view showing the middle of the manufacture process of each part of the principal part in the nonvolatile semiconductor memory device concerning a 7th embodiment of this invention. Sectional drawing which shows the structure in the middle of the manufacturing process of each principal part in the non-volatile semiconductor memory device concerning 7th Embodiment of this invention compared with FIG. 1 is a circuit diagram showing a configuration of a NAND type EEPROM to which each embodiment of the present invention can be applied. 1 is a circuit diagram showing a configuration of a NOR type EEPROM to which each embodiment of the present invention can be applied. 1 is a circuit diagram showing a configuration of a DINOR type EEPROM to which each embodiment of the present invention can be applied. 1 is a circuit diagram showing a configuration of an AND type EEPROM to which each embodiment of the present invention can be applied. (A), (b) is each sectional drawing which shows the manufacturing process of the conventional non-volatile semiconductor memory device. (C), (d) is each sectional drawing following FIG. 36 which shows the manufacturing process of the conventional non-volatile semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... N well, 103 ... P well, 104, 1 ... Element isolation film (oxide film), 105, 108, 2 ... Gate oxide film, 106, 3 ... First polysilicon layer (floating gate, Peripheral circuit transistor gate), 107 ... second polysilicon layer (control gate), 109,6 ... ONO film, 110,19,23 ... interlayer insulating film (oxide film), 112,20 ... wiring, 16 ... Ti / TiN film, 17 ... silicide film (TiSi), 200, 217 ... trench, 201 ... WSi, 202, 18 ... W (tungsten), 218, 22 ... trench element isolation film (TEOS), 7 ... polysilicon / WSi ( Control gate), 8, 13, 24... SiN film, 9, 10, 11, 12, 14, 15, 215, 218, 31, 32.

Claims (8)

A gate insulating film, a first conductor serving as a floating gate layer, a second conductor serving as a control gate layer, the first conductor, and the second conductor formed on the semiconductor substrate. A memory cell having a self-aligned double-layer gate structure comprising:
A memory cell unit in which a plurality of the memory cells are connected in series;
A select gate transistor connected in series to the memory cell unit;
A resistance element using the two-layer gate structure;
Comprising
In the resistance element, the first conductor is used as a resistor, and the second conductor and the insulating film are removed from a part of the region on the first conductor. A nonvolatile semiconductor memory device.   A first gate insulating film formed on the semiconductor substrate, and a third conductor different from the second conductor on the first conductor formed via the first gate insulating film. The nonvolatile semiconductor memory device according to claim 1, further comprising a first transistor having a gate electrode having a stacked structure.   3. The nonvolatile semiconductor device according to claim 2, wherein in the resistance element, a contact region in which the third conductor is formed is formed on a partial region on the first conductor. Storage device.   4. The nonvolatile semiconductor memory device according to claim 2, further comprising a silicide layer formed on a surface of the source / drain region of the first transistor. A second gate insulating film formed on the semiconductor substrate; and a gate electrode having a structure in which the third conductor is stacked on the first conductor formed via the second gate insulating film. A second transistor,
5. The nonvolatile semiconductor memory device according to claim 2, wherein a film thickness of the second gate insulating film is thicker than a film thickness of the first gate insulating film. 6.   The nonvolatile semiconductor memory device according to claim 1, wherein a metal wiring is formed in a region where the second conductor and the insulating film are removed.   The nonvolatile semiconductor memory device according to claim 1, wherein the resistance element is formed on an element isolation insulating film. The select gate transistor has a gate electrode formed through a third gate insulating film,
3. The nonvolatile semiconductor memory device according to claim 2, wherein the thickness of the gate insulating film is equal to the thickness of the second gate insulating film and the third gate insulating film.

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