JPH0319273A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0319273A
JPH0319273A JP15431389A JP15431389A JPH0319273A JP H0319273 A JPH0319273 A JP H0319273A JP 15431389 A JP15431389 A JP 15431389A JP 15431389 A JP15431389 A JP 15431389A JP H0319273 A JPH0319273 A JP H0319273A
Authority
JP
Japan
Prior art keywords
silicide
resistor
resistors
polycrystalline silicon
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15431389A
Other languages
Japanese (ja)
Inventor
Ryuichi Okamura
龍一 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15431389A priority Critical patent/JPH0319273A/en
Publication of JPH0319273A publication Critical patent/JPH0319273A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the degree of freedom of design by electrically connecting a resistor and a wiring layer via a silicide part, and arranging the silicide part in the region except the contact part between the wiring layer and the resistor. CONSTITUTION:Polysilicon resistors 1, 2 are formed between aluminum wirings 1, 2, and silicide 7 is formed in the nearly central parts of the resistors 1, 2. The resistors 1, 2 have mutually different values, and electrically connected with the wirings 3, 4 via silicide 6 formed in contact holes. The silicide 7 is formed in the polycrystalline silicon region except holes 5; as to the resistor 2, the silicide 6 is formed only in the hole 5 parts. In this manner, the resistors 1, 2 have the silicide 7 also in the part except the contact part with the wirings 3, 4, and the length and the width of the silicide part 7 are changed in the case of design change. Hence an aperture part forming mask only may be changed, so that design becomes free.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に多結晶シリコン抵抗の
構造に関する. 〔従来の技術〕 従来、この種の多結晶シリコン抵抗(以下ボリシリ抵抗
と略記する)は、所定の大きさ、および抵抗値になるよ
うに多結晶シリコン層を形成し、その両端に金属配線、
たとえばアルミニウム配線(以下、アルミ配線と略記す
る)を接続して完或されていた. 従来技術の詳細を第5図および第6図を参照して説明す
る。ボリシリ抵抗11は、アルミ配線3および4間に設
けられ、このアルミ配線3,4との接触部にはシリサイ
ド6が形成されている.(シリサイド6は便宜上、斜線
を施してあるが、断面を示すものではない。) 次に従来のポリシリ抵抗の製造方法を示す。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a polycrystalline silicon resistor. [Prior Art] Conventionally, this type of polycrystalline silicon resistor (hereinafter abbreviated as polycrystalline resistor) consists of forming a polycrystalline silicon layer so as to have a predetermined size and resistance value, and connecting metal wiring to both ends of the polycrystalline silicon layer.
For example, it was completed by connecting aluminum wiring (hereinafter abbreviated as aluminum wiring). Details of the prior art will be explained with reference to FIGS. 5 and 6. The resistive resistor 11 is provided between the aluminum wirings 3 and 4, and silicide 6 is formed at the contact portion with the aluminum wirings 3 and 4. (The silicide 6 is shaded for convenience, but its cross section is not shown.) Next, a conventional method for manufacturing a polysilicon resistor will be described.

絶縁膜8上に多結晶シリコンを0.2〜0.3μmの厚
さで被着させ、その多結晶シリコン中に、所定の抵抗値
を得るために不純物をイオン注入する.次に、フォトリ
ソグラフィー技術によりレジストをマスクとして多結晶
シリコンをエッチングし、ポリシリ抵抗11を形或する
。その上に0.3〜0.5μmの厚さの絶縁膜9を形成
し、フォトリングラフィー技術にてポリシリ抵抗1lの
所定のコンタクト部上に開孔を設ける。その上に高融点
金属、たとえば白金等のシリサイドを形成しやすい金属
を被着させ、400〜500℃程度の熱処理を加えると
、ポリシリ抵抗11のフンタクト部にシリサイド6が形
成される.その後、王水によるウェットエッチングによ
りシリサイドしなかった白金をエッチングした後、1.
0〜1.5μmの厚さの絶縁膜10を形成し、フォトリ
ソグラフィー技術により、アルミ配線と接続するための
コンタクト孔5を形或する。その上にバリアメタルとし
て、タングステンあるいはチタン等の高融点金属を厚サ
1. 0〜1.5μmのアルミニウムを被着させ、フォ
トリングラフィー技術によりアルミニウムを所定の配線
形状にパターニングしてアルミ配線3および4を形成す
る. 以上述べた様に従来の半導体装置におけるポリシリ抵抗
は、コンタクト部のみにシリサイドを有する構造となっ
ていた. 〔発明が解決しようとする課題〕 上述した従来のボリシリ抵抗は、アルミ配線とのコンタ
クト部だけにシリサイドを形成しているが、複数の異な
る抵抗値を持つ抵抗が必要な場合、抵抗毎に大きさを変
えるか、不純物のイオン注入量を変える必要があり設計
工数又は、イオン注入工程の増加によりプロセス工期が
長くなる欠点がある。
Polycrystalline silicon is deposited on the insulating film 8 to a thickness of 0.2 to 0.3 μm, and impurity ions are implanted into the polycrystalline silicon to obtain a predetermined resistance value. Next, polysilicon resistor 11 is formed by etching the polycrystalline silicon using photolithography using the resist as a mask. An insulating film 9 having a thickness of 0.3 to 0.5 μm is formed thereon, and openings are formed on predetermined contact portions of the polysilicon resistor 1l using photolithography. When a high-melting point metal such as platinum which easily forms silicide is deposited thereon and heat treatment is applied at about 400 to 500°C, silicide 6 is formed in the exposed portion of polysilicon resistor 11. After that, after etching the platinum that was not silicided by wet etching with aqua regia, 1.
An insulating film 10 having a thickness of 0 to 1.5 μm is formed, and a contact hole 5 for connection to an aluminum wiring is formed by photolithography. On top of that, a high melting point metal such as tungsten or titanium is applied as a barrier metal to a thickness of 1. Aluminum with a thickness of 0 to 1.5 μm is deposited, and the aluminum is patterned into a predetermined wiring shape using photolithography technology to form aluminum wirings 3 and 4. As mentioned above, polysilicon resistors in conventional semiconductor devices have a structure in which silicide is present only in the contact area. [Problems to be Solved by the Invention] The conventional polysilicon resistor described above forms silicide only in the contact area with the aluminum wiring, but if resistors with multiple different resistance values are required, each resistor has a large It is necessary to change the impurity ion implantation amount or to change the impurity ion implantation amount, which has the disadvantage that the process time becomes longer due to an increase in design man-hours or ion implantation steps.

また、設計変更等で抵抗値を変えたい場合、抵抗の大き
さを変更すると、第6図に示すように、ポリシリ抵抗1
1の形状,シリサイド6の位置、コンタクト孔5の位置
、アルミ配線3,4のパターンを変更することとなり、
結果として、抵抗形或用マスク,シリサイド形戊用マス
ク,コンタクト形或用マスク,アルミ配線形成用マスク
の4種類のマスクを各工程でしなければならない。その
ため、変更にかかる時間,経費等が大きくなる欠点があ
る。
Also, if you want to change the resistance value due to design changes, etc., if you change the resistance size, the polysilicon resistance 1
The shape of 1, the position of silicide 6, the position of contact hole 5, and the pattern of aluminum wiring 3 and 4 were changed.
As a result, four types of masks must be used in each process: a resistance type mask, a silicide type mask, a contact type mask, and a mask for aluminum wiring formation. Therefore, there is a drawback that the time and cost required for changes are large.

本発明の目的は、抵抗値の変更に対して、製造工程等に
おいて、大幅に工数の増加を招くことなく、設計の自由
度を向上させた半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device in which the degree of freedom in design is improved in response to changes in resistance values without significantly increasing the number of man-hours in the manufacturing process.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、多結晶シリコンで層で形或され
た抵抗と、該抵抗の両端部に夫々形或された第1及び第
2のシリサイド部と、該第1及び第2のシリサイド部を
介して前記抵抗と電気的に接続された配線層と、該配線
層と前記抵抗との接触部以外の前記多結晶シリコン層の
所定の領域に設けられた第3のシリサイド部とを有して
いる。
A semiconductor device of the present invention includes a resistor formed of a layer of polycrystalline silicon, first and second silicide parts formed at both ends of the resistor, and the first and second silicide parts. a wiring layer electrically connected to the resistor via a third silicide portion provided in a predetermined region of the polycrystalline silicon layer other than a contact portion between the wiring layer and the resistor. ing.

このような構虞によりシリサイド部形或用マスクを変更
するだけで、任意のシリサイド部を多結晶シリコン層に
形或でき、工程数の増加を招くことむく低抵抗を形戒す
ることが可能となる。
With this structure, any desired silicide region can be formed into a polycrystalline silicon layer by simply changing the shape of the silicide region or the mask used, making it possible to achieve low resistance without increasing the number of steps. Become.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する.第1図に
本発明の第1の実施例の平面図を示す。
Next, the present invention will be explained with reference to the drawings. FIG. 1 shows a plan view of a first embodiment of the present invention.

アルミ配線3および40間には、ボリシリ抵抗1および
2が形成される。ポリシリ抵抗AIは、ほぼ中央部にシ
リサイド7が形成されており,ボリシリ抵抗A1と抵抗
B2とは互いに異なる抵抗値を有している。これらのポ
リシリ抵抗1および2は、従来技術同様、アルミ配線3
および4と夫々、コンタクト孔5に設けられたシリサイ
ド6を介して電気的に接続されている。(シリサイド6
,7は便宜上、斜線が施してあるが、断面を示すもので
はない。) 以下にポリシリ抵抗A1およびポリシリ抵抗B2につい
て第2図(a)および(b)を参照して詳述する。
Voltage resistors 1 and 2 are formed between aluminum wirings 3 and 40. The polysilicon resistor AI has a silicide 7 formed approximately in the center, and the polysilicon resistor A1 and the resistor B2 have different resistance values. These polysilicon resistors 1 and 2 are connected to aluminum wiring 3 as in the prior art.
and 4 are electrically connected to each other via silicide 6 provided in contact hole 5. (Silicide 6
, 7 are shaded for convenience, but do not represent cross sections. ) Polysilicon resistor A1 and polysilicon resistor B2 will be described in detail below with reference to FIGS. 2(a) and (b).

ポリシリ抵抗Alには、第2図(a)に示すようにアル
ミ配線3および4との接触部、すなわち、コンタクト孔
にシリサイド6が設けられている。
As shown in FIG. 2(a), the polysilicon resistor Al is provided with silicide 6 at the contact portions with the aluminum wirings 3 and 4, that is, at the contact holes.

またこのコンタクト孔5以外の多結晶シリコン領域にシ
リサイド7が形或されている。また、ボリシリ抵抗B2
には、コンタクト孔5部にのみシリサイド6が形成され
ている。
Further, silicide 7 is formed in the polycrystalline silicon region other than the contact hole 5. In addition, the resistor B2
In this case, silicide 6 is formed only in the contact hole 5 portion.

次に本発明の実施例の一製造方法を示す。絶縁膜8上に
多結晶シリコンを0.2〜0.3μmの厚さで被着させ
その多結晶シリコン中に不純物をイオン注入する。フォ
トリソグラフィー技術によりレジストをマスクにして多
結晶シリコンをエッチングし、ポリシリ抵抗A1および
抵抗B2を形或する。その上に0.3〜0.5μmの厚
さの絶縁膜9を形成し、フォトリングラフィー技術によ
りシリサイド化する部分に開孔を設ける。この実施例で
は、ボリシリ抵抗A1は、コンタクト孔部と、たとえば
抵抗中央部に開孔を設け、ポリシリ抵抗B2ではコンタ
クト孔部だけに開孔を行う。その上に白金等の金属を被
着させ400〜500℃の熱処理を加えると絶縁膜9の
開孔部の多結晶シリコンにシリサイド6および7が形成
される。シリサイドしなかった白金をエッチングした後
、1.0〜1.5μmの厚さの絶縁膜10を形成し、フ
ォトリソグラフィー技術にて抵抗と配線を接続するため
のコンタクト孔5の開孔を行う。その上にバリアメタル
と1.0〜1.5μmの厚さのアルミニウムを被着し、
フォトリソグラフィー技術にて、アルミニウムをパター
ニングして、アルミ配線3,4を形或する。この様に、
ボリシリ抵抗A1は、配線接続用のコンタクト孔5部と
抵抗の中央部にシリサイド構造を持ち、ポひシリ抵抗B
2は、配線接続用のコンタクト孔5部だけにシリサイド
構造を持つ。
Next, a manufacturing method of an embodiment of the present invention will be described. Polycrystalline silicon is deposited on the insulating film 8 to a thickness of 0.2 to 0.3 μm, and impurity ions are implanted into the polycrystalline silicon. Polycrystalline silicon is etched by photolithography using a resist as a mask to form polysilicon resistors A1 and B2. An insulating film 9 having a thickness of 0.3 to 0.5 μm is formed thereon, and holes are formed in the portions to be silicided by photolithography. In this embodiment, the polysilicon resistor A1 has an opening in the contact hole and, for example, in the center of the resistor, and the polysilicon resistor B2 has an opening only in the contact hole. When a metal such as platinum is deposited thereon and heat treated at 400 to 500° C., silicides 6 and 7 are formed in the polycrystalline silicon in the openings of the insulating film 9. After etching the unsilicided platinum, an insulating film 10 with a thickness of 1.0 to 1.5 μm is formed, and a contact hole 5 for connecting the resistor and wiring is formed by photolithography. On top of that, barrier metal and aluminum with a thickness of 1.0 to 1.5 μm are deposited.
Aluminum wirings 3 and 4 are formed by patterning aluminum using photolithography technology. Like this,
The resistor A1 has a silicide structure in the 5 contact holes for wiring connection and the center of the resistor, and the resistor B
No. 2 has a silicide structure only in 5 portions of the contact hole for wiring connection.

次に本実施例のポリシリ抵抗の機能を説明する。Next, the function of the polysilicon resistor of this embodiment will be explained.

ポリシリ抵抗A1及び抵抗B2が有するコンタクト孔5
部のシリサイド構造は抵抗と配線の接続抵抗を減少させ
る。また、ポリシリ抵抗A1は、中央部にもシリサイド
構造を有しているが、これはシリサイド両端部をショー
トさせる様に機能する。
Contact hole 5 of polysilicon resistor A1 and resistor B2
The silicide structure of the part reduces the resistance and interconnection resistance. The polysilicon resistor A1 also has a silicide structure in the center, which functions to short-circuit both ends of the silicide.

そのため、ボリシリ抵抗A1の抵抗値は、中央にシリサ
イド構造を有しないポリシリ抵抗B2に比べて低くなる
。この様に、抵抗中央部にシリサイド構造を形或するこ
とにより抵抗値を変化させることができる。
Therefore, the resistance value of the polysilicon resistor A1 is lower than that of the polysilicon resistor B2 which does not have a silicide structure in the center. In this way, by forming a silicide structure in the center of the resistor, the resistance value can be changed.

本発明において、抵抗値の設計変更が生じた場合につい
て、第3図および第4図を参照して説明する。第4図に
おいて、ポリシリ抵抗11の抵抗値をRuとする。次に
、設計変更により抵抗値Rl1より小さい抵抗値が必要
となった場合には、ポリシリ抵抗l1のコンタクト孔5
部以外にもシリサイド部12を第3図のようにたとえば
、2ケ所形成すれば良い。このような設計変更における
マスク変更はシリサイド形或領域用のマスクを変更する
だけで良く、1工程の変更だけで実現できる。
In the present invention, a case where a design change in resistance value occurs will be explained with reference to FIGS. 3 and 4. In FIG. 4, the resistance value of the polysilicon resistor 11 is Ru. Next, if a resistance value smaller than the resistance value Rl1 is required due to a design change, the contact hole 5 of the polysilicon resistor l1
In addition to the silicide portions, silicide portions 12 may be formed at two locations, for example, as shown in FIG. Mask changes in such design changes can be accomplished by simply changing the mask for a certain region of silicide type, and can be achieved by changing only one process.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、ポリシリ抵抗の配線とのコ
ンタクト部以外の部分にもシリサイド構造を有しており
、このシリサイド部の長さ,幅等を変えるだけで、抵抗
値を変えることができ、設計が容易になる。さらに設計
変更等で、多結晶シリコン層の抵抗値を変えたい場合は
、コンタクト部以外に形或されるシリサイド部の長さ,
幅等を変更するため、開孔部形或マスクのみを変更すれ
ばよく、工数を大幅に低減できる利点がある。
As explained above, the present invention has a silicide structure in parts other than the contact part with the wiring of the polysilicon resistor, and the resistance value can be changed simply by changing the length, width, etc. of this silicide part. This makes the design easier. Furthermore, if you want to change the resistance value of the polycrystalline silicon layer due to design changes, etc., the length of the silicide part formed other than the contact part,
In order to change the width etc., it is only necessary to change the shape of the opening or the mask, which has the advantage of greatly reducing the number of man-hours.

第6図は、従来例における設計変更時の抵抗を示す平面
図である。
FIG. 6 is a plan view showing the resistance at the time of design change in the conventional example.

l・・・・・・ポリシリ抵抗A,2・・・・・・ポリシ
リ抵抗B、3,4・・・・・・アルミ配線、5・・・・
・・コンタクト孔、6,7.12・・・・・・シリサイ
ド、8,9.10・・・・・・絶縁膜、l1・・・・・
・ポリシリ抵抗。
l... Polysilicon resistance A, 2... Polysilicon resistance B, 3, 4... Aluminum wiring, 5...
...Contact hole, 6,7.12...Silicide, 8,9.10...Insulating film, l1...
・Polysiliary resistance.

Claims (1)

【特許請求の範囲】[Claims] 多結晶シリコンで形成された抵抗と、該抵抗の両端部に
それぞれ設けられた第1および第2のシリサイド部と、
該第1および第2のシリサイド部を介して前記抵抗とそ
れぞれ電気的に接続された配線層と、該配線層と前記抵
抗との接触部以外の前記多結晶シリコン層の所定の領域
に設けられた第3のシリサイド部とを有することを特徴
とする半導体装置。
a resistor formed of polycrystalline silicon; first and second silicide portions provided at both ends of the resistor;
A wiring layer electrically connected to the resistor through the first and second silicide portions, and a predetermined region of the polycrystalline silicon layer other than a contact portion between the wiring layer and the resistor. A semiconductor device characterized in that it has a third silicide portion.
JP15431389A 1989-06-15 1989-06-15 Semiconductor device Pending JPH0319273A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15431389A JPH0319273A (en) 1989-06-15 1989-06-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15431389A JPH0319273A (en) 1989-06-15 1989-06-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0319273A true JPH0319273A (en) 1991-01-28

Family

ID=15581389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15431389A Pending JPH0319273A (en) 1989-06-15 1989-06-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0319273A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5137466A (en) * 1990-10-29 1992-08-11 Yazaki Corporation Electric connector
US5591042A (en) * 1994-10-27 1997-01-07 Sumitomo Electric Industries, Ltd. Connector assembly
JP2001196559A (en) * 2000-01-13 2001-07-19 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP2001257271A (en) * 2001-02-13 2001-09-21 Seiko Epson Corp Semiconductor device and its manufacturing method
WO2004105135A1 (en) * 2003-05-19 2004-12-02 Advanced Micro Devices, Inc. Method of forming resistive structures
US7180153B2 (en) 2001-03-30 2007-02-20 Renesas Technology Corp. Capture of residual refractory metal within semiconductor device
JP2008235936A (en) * 2008-05-26 2008-10-02 Toshiba Corp Non-volatile semiconductor memory device
US7888728B2 (en) 1997-07-10 2011-02-15 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and its manufacturing method
JP2012182488A (en) * 2012-05-25 2012-09-20 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
JP2014192314A (en) * 2013-03-27 2014-10-06 Citizen Holdings Co Ltd Semiconductor device manufacturing method
KR20180084613A (en) * 2017-01-17 2018-07-25 에이블릭 가부시키가이샤 Semiconductor device and method of manufacturing semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216356A (en) * 1985-03-20 1986-09-26 Nec Corp Semiconductor resistor
JPS6289341A (en) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp Manufacture of master slice system large scale semiconductor integrated circuit device
JPS6467942A (en) * 1987-09-08 1989-03-14 Nec Corp Formation of resistance circuit of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216356A (en) * 1985-03-20 1986-09-26 Nec Corp Semiconductor resistor
JPS6289341A (en) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp Manufacture of master slice system large scale semiconductor integrated circuit device
JPS6467942A (en) * 1987-09-08 1989-03-14 Nec Corp Formation of resistance circuit of semiconductor device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5137466A (en) * 1990-10-29 1992-08-11 Yazaki Corporation Electric connector
US5591042A (en) * 1994-10-27 1997-01-07 Sumitomo Electric Industries, Ltd. Connector assembly
US8969942B2 (en) 1997-07-10 2015-03-03 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and its manufacturing method
US8698225B2 (en) 1997-07-10 2014-04-15 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and its manufacturing method
US7888728B2 (en) 1997-07-10 2011-02-15 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and its manufacturing method
JP2001196559A (en) * 2000-01-13 2001-07-19 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP2001257271A (en) * 2001-02-13 2001-09-21 Seiko Epson Corp Semiconductor device and its manufacturing method
US7408239B2 (en) 2001-03-30 2008-08-05 Renesas Technology Corp. Capture of residual refractory metal within semiconductor device
US7180153B2 (en) 2001-03-30 2007-02-20 Renesas Technology Corp. Capture of residual refractory metal within semiconductor device
GB2417830B (en) * 2003-05-19 2007-04-25 Advanced Micro Devices Inc Method of forming resistive structures
GB2417830A (en) * 2003-05-19 2006-03-08 Advanced Micro Devices Inc Method of forming resistive structures
WO2004105135A1 (en) * 2003-05-19 2004-12-02 Advanced Micro Devices, Inc. Method of forming resistive structures
JP2008235936A (en) * 2008-05-26 2008-10-02 Toshiba Corp Non-volatile semiconductor memory device
JP2012182488A (en) * 2012-05-25 2012-09-20 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
JP2014192314A (en) * 2013-03-27 2014-10-06 Citizen Holdings Co Ltd Semiconductor device manufacturing method
KR20180084613A (en) * 2017-01-17 2018-07-25 에이블릭 가부시키가이샤 Semiconductor device and method of manufacturing semiconductor device
CN108336067A (en) * 2017-01-17 2018-07-27 艾普凌科有限公司 The manufacturing method of semiconductor device and semiconductor device

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