JP2654175B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device.

(Prior Art) In general, in miniaturization of an integrated circuit, a technique of directly connecting polycrystalline silicon (Si) used as a gate electrode as a wiring to a direct diffusion layer is important.
A method usually used in the above-described technique will be described with reference to FIG.

First, as shown in FIG. 3A, an oxide film 42 for separating an element region on a Si substrate 41 by using a selective oxidation method, for example.
To form Next, a gate insulating film 43 made of SiO _{2 is} formed, for example, to a thickness of about 10 nm by, for example, HCl oxidation. Then, for example, using a chemical vapor deposition method (CVD method),
Is deposited to a thickness of about 140 nm. Thereafter, a resist film 45 is applied to a predetermined thickness, and a mask for forming a hole for connecting the polycrystalline Si film 44 and a diffusion layer region described later is formed by photolithography (FIG. 3A )reference).

Thereafter, as shown in FIG. 3B, using the resist film 45 as a mask, holes for connecting the polycrystalline Si film 44 and the diffusion layer region are formed by, for example, anisotropic dry etching.
After removing the resist film, the gate insulating film 43 present at the bottom of the hole to be connected is removed using, for example, NH ₄ F or the like. Next, for example, using a chemical vapor deposition method, a polycrystalline Si film
47 is formed to about 50 nm, and then, for example, phosphorus is ion-implanted at about 50 × 10 ¹⁵ cm ⁻² with an energy of 50 KeV to form a diffusion layer region 48.
Is formed (see FIG. 3 (b)).

Thereafter, a polycrystalline Si film 49 is further formed using a chemical vapor deposition method.
Deposit about 100 nm. And, for example, 900 in POCl ₃ atmosphere
Polycrystalline Si film 4 deposited by heat treatment at ℃ for about 30 minutes
4, 47, 49 are reduced in resistance and the diffusion layer region 48 is also electrically activated.

Thereafter, a resist film 50 is applied to a predetermined thickness, and a mask for forming a wiring portion to be connected to the gate electrode and the diffusion layer region 48 is formed by photolithography (see FIG. 3B). .

Next, as shown in FIG. 3 (c), the polycrystalline Si films 44, 47 and 49 are etched using, for example, anisotropic dry etching using the resist film 50 processed into a predetermined shape as a mask. , A gate electrode 51a, and a diffusion layer region 53b to be described later.
Then, a wiring portion 51b to be connected to is formed.

Thereafter, using the gate electrode 51a as a mask, for example,
About 5 × 10 ¹⁵ cm ⁻² ions are implanted at an energy of eV to form diffusion layer regions 53a and 53b (see FIG. 3 (c)).

Next, as shown in FIG. 3D, about 500 nm of SiO ₂ is deposited by, for example, a chemical vapor deposition method, and an interlayer insulating film 54 is formed. Then, a connection hole 55a with the diffusion layer region 53a and a connection hole 55b with the wiring portion 51b are formed by using photolithography and anisotropic etching. Thereafter, for example, Al is deposited to a thickness of about 500 nm by sputtering, and a metal wiring 56 is formed by using a combination of photolithography and anisotropic etching, thereby completing a semiconductor device.

(Problem to be Solved by the Invention) When the conventional method is used, the diffusion layer region 53 directly connected to the wiring portion 51b must be a semiconductor of the same conductivity type. For types,
Direct connection was possible only to the n-type diffusion layer region.

Further, as shown in FIG. 3 (c), the polycrystalline Si films 44, 47, 49
Since the part 52 of the Si substrate 41 is also etched during the etching, the part 52 is liable to cause electrical leakage, which causes a problem that the characteristics of the semiconductor device are deteriorated.

In addition, the conventional method requires not only performing a photolithography process twice to form a hole directly connecting the wiring portion 51b and the diffusion layer region 53b, but also performing a polycrystalline Si film three times. Must be deposited separately. Also, high-concentration ion implantation must be performed twice, which is a complicated process as a whole.

The present invention has been made in consideration of the above problems, and can connect a diffusion layer region and a wiring portion regardless of the conductivity type. An object of the present invention is to provide a method for manufacturing a semiconductor device which does not deteriorate.

[Configuration of the invention]

(Means for Solving the Problems) In a method for manufacturing a semiconductor device according to the present invention, a step of forming an element region and an element isolation region on a semiconductor substrate and a step of forming a gate insulating film on the element region and the element isolation region Depositing a conductive film on the gate insulating film and patterning to form a gate electrode on the device region and a wiring portion on a predetermined portion on the device isolation region; and a device using the gate electrode and the wiring portion as a mask. Forming a diffusion layer region on the region, forming an interlayer insulating film on the pattern formation surface of the semiconductor substrate, and directly removing the interlayer insulating film to directly connect the wiring portion and the diffusion layer region Forming a connection hole to be connected to the wiring portion, and a step of selectively forming a metal film at the bottom of the connection hole.

(Operation) According to the method of manufacturing a semiconductor device according to the present invention thus configured, it is not necessary to remove the gate insulating film in the region where the diffusion layer region and the wiring portion are directly connected. Unlike the conventional method, the crystalline Si film can be formed at once, thereby simplifying the manufacturing process as compared with the conventional method.

Since the gate insulating film is not removed, etching of the semiconductor substrate, which has conventionally occurred at the time of forming the wiring portion, does not occur, so that electric leakage does not occur and deterioration of characteristics of the semiconductor device can be prevented.

In addition, there is a gate insulating film between the wiring portion and the diffusion layer region which are connected by the formation of the metal film. Since the gate insulating film serves as a barrier for diffusion, the wiring portion and the diffusion layer region have the same conductivity type. It does not need to be.

(Embodiment) FIG. 1 shows a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

As shown in FIG. 1 (a), for example, first conductivity type Si
Forming an element isolation region 2 made of SiO ₂ with the substrate 1, for example a selective oxidation method. Thereafter, a gate insulating film 3 of about 10 nm is formed, for example, in an oxidizing atmosphere of 800 ° C. and 10% HCl. Then, a polycrystalline Si film 4 to be a gate electrode and a wiring portion is deposited to a thickness of about 400 nm by using, for example, a chemical vapor deposition method.
A heat treatment is performed for 30 minutes in a POCl ₃ atmosphere at 30 ° C. This heat treatment is performed to reduce the resistance of the polycrystalline Si film. Next, a resist film 5 is applied to a predetermined thickness (for example, 1.5 μm),
Patterning is performed using a photolithography method.

Thereafter, using the resist film 5 patterned as shown in FIG. 1B as a mask, the polycrystalline Si film 4 is patterned using, for example, anisotropic etching to form a gate electrode 4a and a wiring portion 4b. I do. And the gate electrode
Using the 4a and the wiring portion 4b as a mask, for example, As is ion-implanted at about 5 × 10 ¹⁵ cm ⁻² at an energy of 40 KeV to form a diffusion layer region.
7a and 7b are formed.

Thereafter, as an interlayer insulating film, for example, a SiO ₂ film 8 of about 500 nm is deposited by a chemical vapor deposition method. A connection hole 9 for directly connecting the wiring portion 4b and the diffusion layer region 7b to the interlayer insulating film 8 by a combination of photolithography and anisotropic etching, and a diffusion layer region 7a. Connection hole 10
And the connection hole 11 with the wiring portion 4b are formed at the same time.

Further, for each of the connection holes 9, 10 and 11, for example, WF ₆
100 to 2 using chemical vapor deposition of tungsten
A 00 nm tungsten film 12 is formed. Tungsten film 12
Fig. 1 (c) because it grows selectively only on Si
The coated shape is as shown in FIG.

After that, as shown in FIG. 1 (d), for example, Al is deposited to a thickness of about 500 nm as a metal wiring by a sputtering method.
Patterning is performed using a combination of photolithography and anisotropic etching to form a metal wiring 13, thereby completing a semiconductor device.

As described above, according to the present embodiment, the photolithography method can be omitted once as compared with the conventional method, and the gate insulating film 3 in the region where the wiring portion 4b and the diffusion layer region 7b are directly connected is formed. The fact that there is no need to remove the polycrystalline Si film 4 and the fact that the polycrystalline Si film 4 can be formed at one time unlike the conventional method makes the manufacturing process simpler than the conventional method. Since the gate insulating film 3 is not removed,
Since the etching of the Si substrate 1 which has conventionally occurred at the time of forming the wiring portion does not occur, electric leakage does not occur, and deterioration of semiconductor device characteristics can be prevented.

Further, according to the present embodiment, the connection between the diffusion layer region 7b and the wiring portion 4b is achieved by covering the whole exposed portion of Si with tungsten, so that the contact resistance can be significantly reduced.

In addition, wiring parts connected by tungsten coating
Since the gate insulating film 3 is provided between the gate insulating film 4b and the diffusion layer region 7b and serves as a diffusion barrier, the wiring portion 4b and the diffusion layer region 7b do not need to use the same conductivity type Si. It is also possible to connect.

In this embodiment, the gate electrode 4a and the wiring portion 4b are used.
Phosphorus diffusion was used to reduce the resistance of the polycrystalline Si film used as
The same effect can be obtained by using a method of ion-implanting and electrically activating by heat treatment.

The diffusion layer region 7a in this embodiment, the 7b, although formed by ion implantation of As, this example BF ₂ to 5
A P-type one obtained by ion implantation at about 5 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0 KeV may be used.

Further, in this embodiment, a tungsten film is selectively formed, but this is a method in which, for example, Ti is deposited, a heat treatment at about 700 ° C. is performed, and only the exposed region of Si is selectively turned into Ti-silicide. The same effect can be obtained by using.

In the above embodiment, polycrystalline silicon is used as a material for the gate electrode and the wiring portion.However, after polycrystalline silicon is deposited, Ti silicide, W silicide, or Mo silicide is further deposited to form a laminated structure. The gate electrode and the wiring portion may be formed by patterning the laminated structure. In addition, W, Mo, TiN, etc. can be used as a gate electrode material.

FIG. 2 shows a second embodiment of the method of manufacturing a semiconductor device according to the present invention. For example, as shown in FIG.
An element isolation region 22 made of SiO ₂ is formed on the conductive type Si substrate 21 by using, for example, a selective oxidation method. Thereafter, a gate insulating film 23 having a thickness of, for example, about 10 nm is formed. Then, a polycrystalline Si film 24 and a WSi film 25 for lowering resistance, which are to be a gate electrode and a wiring portion, are sequentially laminated, and patterned by a combination of photolithography and anisotropic etching to form a gate electrode 26a, 26b and wiring portions 26c and 26d are formed. Then, impurities are ion-implanted using the gate electrodes 26a, 26b and the wiring portions 26c, 26d as a mask, and the diffusion layer regions 27a, 27b, 27
c, 27d are formed (see FIG. 2 (a)).

Thereafter, for example, an SiO ₂ film 28 is deposited as an interlayer insulating film.
Then, the interlayer insulating film 28 is patterned by a combination of photolithography and anisotropic etching to form a connection hole with the diffusion layer region 27a and a wiring hole 26c with the diffusion layer regions 27b and 27c. A connection hole and a connection hole between the wiring portion 26d and the diffusion layer region 27d are simultaneously opened.

Further, for each of the connection hole, for example using chemical vapor deposition of tungsten using WF _6, a tungsten film 29a,
29b, 29c and 29d are formed (see FIG. 2 (b)).

Thereafter, as shown in FIG. 2 (c), for example, Al is deposited to a thickness of about 500 nm as a metal wiring by a sputtering method.
Patterning is performed using a combination of photolithography and anisotropic etching to form metal wirings 33a and 33b, thereby completing a semiconductor device.

As described above, the second embodiment can obtain the same effects as those of the first embodiment.

〔The invention's effect〕

According to the present invention, the diffusion layer region and the wiring portion can be connected regardless of the conductivity type, and the manufacturing process can be simplified. Further, deterioration of the characteristics of the semiconductor device manufactured by this manufacturing process can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. FIG. 14 is a cross-sectional view showing a manufacturing step of a semiconductor device by a conventional method. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation region, 3 ... Gate insulating film, 4 ... Polycrystalline Si film, 4a ... Gate electrode, 4b ...
Wiring portion, 5: resist film, 7a, 7b: diffusion layer region, 8
... interlayer insulating films, 9, 10, 11 ... connecting holes, 12 ... tungsten films, 13 ... Al wiring, 21 ... Si substrate, 22 ... element isolation regions, 23 ... gate insulating films, 24 ... … Polycrystalline Si film, 25 ……
Wsi film, 26a, 26b ... gate electrode, 26c, 26d ... wiring part, 2
7a, 27b, 27c, 27d: diffusion layer region, 28: interlayer insulating film, 29
a, 29b, 29c, 29d: tungsten film, 33a, 33b: metal wiring.

Claims (5)

(57) [Claims] A step of forming an element region and an element isolation region on a semiconductor substrate; a step of forming a gate insulating film on the element region and the element isolation region; and depositing a conductive film on the gate insulating film; Patterning a gate electrode on the element region while leaving the gate insulating film,
Forming a wiring portion at a predetermined portion on the device region and the device isolation region; forming a diffusion layer region on the device region using the gate electrode and the wiring portion as a mask; and forming a pattern on the semiconductor substrate. Forming an interlayer insulating film on a formation surface; and selectively removing the interlayer insulating film while leaving the gate insulating film below the wiring portion on the element region, thereby forming the wiring portion and the diffusion layer region. A step of forming a connection hole for directly connecting the connection hole and a connection hole with the wiring portion; and a step of selectively forming a metal film at the bottom of the connection hole. Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a connection hole for directly connecting the wiring portion and the diffusion layer region and a connection hole for the wiring portion are simultaneously opened. 3. The method according to claim 1, wherein the step of selectively forming the metal film uses a chemical vapor deposition method of tungsten. 4. The step of selectively forming a metal film,
2. The method according to claim 1, wherein a method of selectively forming Ti silicide by performing heat treatment after forming a Ti film is used. 5. The method according to claim 1, wherein at least one of polycrystalline silicon, high melting point metal, and high melting point metal silicide is used as a gate electrode material.