JP2555755B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and particularly to a polycide wiring region formed by stacking a silicide layer on a polysilicon layer and a semiconductor substrate, and simultaneously connecting a wiring conductive layer. The present invention relates to a semiconductor device having an improved contact part and a method for manufacturing the same.

[Conventional technology]

FIG. 3 (E) is a sectional view of a main part of a conventional semiconductor device. In the figure, 1 is, for example, a silicon substrate, 2 is a gate oxide film, and a polysilicon layer 3 is formed on the gate oxide film 2.
Polycide wiring region 10 having a laminated structure of a metal and a silicide layer 4
Are formed. 6 is an insulating interlayer film made of an oxide film,
A wiring conductive layer 9 is formed on the insulating interlayer film 6, and a part of the wiring conductive layer 9 is in contact with the silicide 4 in the polycide wiring region 10.

3 (A) to 3 (D) are cross-sectional views of a main part in each step for explaining the manufacturing process of the semiconductor device shown in FIG. 3 (E).

As shown in FIG. 3A, for example, a silicon substrate 1
An oxide film 21 for forming an insulative gate oxide film having a thickness of about 200Å is formed on the entire main surface of the
A polysilicon layer 31 having a thickness of Å and a silicide layer 41 of, for example, tungsten silicide having a thickness of about 2000 Å are sequentially formed. Further, a resist having a thickness of about 1 μm is applied on the entire surface of the silicide layer 41 and then patterned to form a resist film 5 having a predetermined shape.

Next, as shown in FIG. 3B, after the silicide layer 41, the polysilicon layer 31 and the oxide film 21 are sequentially etched by reactive ion etching (hereinafter referred to as RIE) using the resist 5 as a mask, The resist 5 is removed, and a polycide wiring region 10 having a laminated structure of the polysilicon layer 3 and the silicide layer 4 is formed on the gate oxide film 2.

Next, as shown in FIG. 3 (C), an insulating property of an oxide film having a thickness of about 3000 Å is formed by using a chemical vapor deposition method (hereinafter referred to as CVD) to cover the substrate 1 and the polycide wiring region 10. Of the interlayer film 6 of about 1 μm is deposited on the entire surface of the interlayer film 6.
After applying a resist having a thickness of, the resist film 7 having a predetermined shape is formed by performing patterning for forming a contact portion.

Next, as shown in FIG. 3D, the interlayer film 6 is etched using the resist film 7 as a mask by using, for example, RIE to contact holes 8 reaching the silicide layer 4.
To form.

Next, the residue of the interlayer film 6 on the silicide layer 4 and the natural oxide film on the silicide layer 4 are completely removed by using, for example, hydrofluoric acid, and then the resist film 7 is removed. A wiring conductive layer 9 made of polysilicon having a thickness of about 2000 Å is deposited on the entire surface of the silicide layer 4 to obtain a semiconductor device having a contact portion shown in FIG. 3 (E).

In the conventional semiconductor device having the above-mentioned structure, the wiring conductive layer 9 connected to the polycide wiring region 10 at the contact portion is connected to the main surface of the silicide layer 4 in the polycide wiring region 10, so that the contact portion is not formed. There has been a problem that the silicide layer 4 is separated from the underlying polysilicon layer 3 by the hydrofluoric acid treatment at the time of formation and the heat treatment at about 800 ° C. or more performed after the contact portion is formed, resulting in contact failure.

In order to solve the problem of contact failure in the contact portion as described above, there is provided a semiconductor device in which the wiring conductive layer 9 directly contacts the underlying polysilicon layer 3 of the polycide wiring region 10 in the contact portion. was suggested.

FIG. 1F is a cross-sectional view of a main part showing an example of such a semiconductor device. In the figure, 1 is, for example, a silicon substrate, 2 is a gate oxide film, and a polycide region region 10 having a laminated structure of a polysilicon layer 3 and a silicide layer 4 is formed on the gate oxide film 2. 6 is an insulating interlayer film made of an oxide film, 9 is a wiring conductive layer, and the wiring conductive layer 9
Is formed on the insulating interlayer film 6, and a part thereof penetrates the silicide layer 4 in the polycide wiring region 10 and is in direct contact with the underlying polysilicon layer 3.

1 (A) to 1 (E) are cross-sectional views of the essential part in each step for explaining the manufacturing process of the semiconductor device shown in FIG. 1 (F).

As shown in FIG. 1A, for example, a silicon substrate 1
An oxide film 21 for forming an insulative gate oxide film having a thickness of about 200Å is formed on the entire main surface of the
A polysilicon layer 31 having a thickness of Å and a silicide layer 41 of, for example, tungsten silicide having a thickness of about 2000 Å are sequentially formed. Next, a resist having a thickness of about 1 μm is applied on the entire surface of the silicide layer 41 and then patterned to form a resist film 5 having a predetermined shape.

Next, as shown in FIG. 1B, the silicide layer 41 and the polysilicon layer 3 are formed by RIE using the resist 5 as a mask.
1 and the oxide film 21 are sequentially etched, and then the resist 5
Is removed, and a laminated structure of the polysilicon layer 3 and the silicide layer 4 is formed on the gate oxide film 2. This laminated structure constitutes the polycide wiring region 10 described above.

Next, as shown in FIG. 1C, the substrate 1 and the polycide wiring region are formed by using, for example, CVD (chemical vapor deposition).
An insulating interlayer film 6 made of an oxide film having a thickness of about 3000 Å is deposited to cover 10 and a resist having a thickness of about 1 μm is applied on the entire surface of the interlayer film 6, and then patterning for forming a contact portion is performed. By doing so, a resist film 7 having a predetermined shape is formed.

Next, as shown in FIG. 1D, the interlayer film 6 is etched using the resist film 7 as a mask by using, for example, RIE, and the contact layer 81 reaching the silicide layer 4 is formed.
To form.

Next, as shown in FIG. 1E, the silicide layer 4 is further formed by using, for example, RIE with the resist film 7 as a mask.
Is etched to form a contact hole 82 reaching the underlying polysilicon layer 3.

Finally, the native oxide film on the silicide layer 4 is completely removed by using, for example, hydrofluoric acid, the resist film 7 is removed, and the entire surface of the interlayer film 6 and the polysilicon layer 3 is removed.
A conductive layer 9 for wiring made of, for example, polysilicon having a thickness of 2000 Å is deposited to obtain a semiconductor device having a contact portion shown in FIG. 1 (F). As is clear from FIG. 1 (F), in the semiconductor device of the present invention, the wiring conductive layer 9 is in direct contact with the underlying polysilicon layer 3 of the polycide wiring region 10 at the contact portion.

[Problems to be Solved by the Invention]

According to the semiconductor device having the structure shown in FIG. 1 (F), since the wiring conductive layer 9 is in direct contact with the underlying polysilicon layer 3 of the polycide wiring region 10 in the contact portion, the above-mentioned contact portion is formed. Of the polysilicon layer 3 in the contact portion by the treatment with hydrofluoric acid or heat treatment of
Although a contact failure due to peeling between the conductive layer 9 and the silicide layer 4 does not occur, when it is necessary to connect the wiring conductive layer 9 to the semiconductor substrate as well, the contact hole 82 in FIG. In addition, another contact hole that penetrates the insulating interlayer film 6 and reaches the semiconductor substrate 1 is formed, and a conductive layer electrically connected to the wiring conductive layer 9 is also formed in the other contact hole. There was a need.

However, it is necessary to form another contact hole reaching the semiconductor substrate in addition to the contact hole in the polycide wiring region to form a conductive layer for wiring that connects the inside of each contact hole and between both contact holes. Not only does the layout area increase to hinder the miniaturization of the circuit, but the conductive layer for wiring connecting the polycide wiring region 10 and the semiconductor substrate becomes long, and the resistance of the conductive layer for wiring increases. was there.

[Means for solving the problem]

According to the present invention, in the contact portion, one contact hole is formed, a part of which reaches the polysilicon layer in the polycide wiring region and a remaining part of which reaches the semiconductor substrate at a position adjacent to the position where the polycide wiring region is arranged. Then, a conductive layer for wiring is formed in the contact hole.

[Work]

In the semiconductor device of the present invention, since the conductive layer for wiring is in direct contact with both the semiconductor substrate of the underlying polysilicon layer in the polycide wiring region, the contact portion is treated by hydrofluoric acid or heat treatment when forming the contact portion. There is no electrical contact failure in the wiring conductive layer in (3), and the contact portion and the semiconductor substrate are connected with a small area and low resistance.

[Explanation of Example]

FIG. 2 shows a sectional structure of a main part of an embodiment of the semiconductor device of the present invention. The basic structure of the semiconductor device of the present invention shown in FIG. 2 is the same as the structure of the semiconductor device shown in FIG. 1 (F), where 1 is, for example, a silicon substrate, 2 is a gate oxide film, 3
Is a polysilicon layer, and 4 is a silicide layer, and the polysilicon layer 3 and the silicide layer 4 form a polycide wiring region 10. Reference numeral 6 is an insulating interlayer film made of an oxide film. A part of the insulating film 6 penetrates the insulating interlayer film 6 and the silicide layer 4 to reach the underlying polysilicon layer 3 of the polycide wiring region 10, and the remaining part reaches the semiconductor substrate 1 adjacent to the installation position of the polycide wiring region 1 The individual contact holes 82 are formed, and the wiring conductive layer 9 that directly contacts both the polysilicon layer 3 and the semiconductor substrate 1 is continuously formed on the insulating interlayer film 6 and in the contact holes 82. Has been formed.

The method of manufacturing the semiconductor device shown in FIG. 2 is performed by covering the semiconductor substrate 1 and the polycide wiring region 10 shown in FIG.
The thickness of 00Å forms the insulating interlayer film 6, and after a resist having a thickness of about 1 μm is applied on the entire surface of the insulating interlayer film 6, a part thereof is located on the polycide wiring region 10 and the rest is A resist film patterned into a predetermined shape having a contact portion forming opening located on the semiconductor substrate 1 adjacent to the installation position of the polycide wiring region 10 is formed.

Next, using the resist film as a mask, RIE
Is used to etch the insulating interlayer 6 and the silicide layer 4 so as to partially cover the polycide wiring region as described above.
One contact hole 82 is formed which reaches the underlying polysilicon layer 3 of 10 and the rest reaches the semiconductor substrate 1 adjacent to the installation position of the polycide wiring region 10. Next, the conductive layer 9 for wiring is formed in the insulating interlayer 6 and the contact hole 82 to obtain the semiconductor device of the present invention shown in FIG.

〔The invention's effect〕

As described above, in the semiconductor device of the present invention, the conductive layer 9 for wiring is in direct contact with both the underlying polysilicon layer 3 of the polycide wiring region 10 and the semiconductor substrate 1 in the contact portion. A highly reliable semiconductor which does not cause a failure in electrical contact at the contact portion due to the treatment with hydrofluoric acid or a heat treatment, and allows the contact portion and the semiconductor substrate to be connected with low resistance and has no failure. The device can be obtained. Further, the area required for the contact portion is also reduced, which can contribute to downsizing of the device.

[Brief description of drawings]

1 (A) to 1 (F) are cross-sectional views of main parts in respective manufacturing steps for explaining a method of manufacturing a semiconductor device having a structure shown in FIG. 1 (F) which is the basis of the semiconductor device of the present invention. Two
FIG. 3 is a cross-sectional view of an essential part showing the structure of an embodiment of a semiconductor device according to the present invention, and FIGS. 3A to 3E show a conventional method for manufacturing a semiconductor device having the structure shown in FIG. FIG. 6 is a cross-sectional view of a main part in each manufacturing step for explaining. 1 ... Substrate, 2 ... Insulating oxide film, 3 ... Polysilicon layer, 4 ... Silicide layer, 6 ... Insulating film (interlayer film), 9
...... Wiring conductive layer, 10 …… Polycide wiring area, 82 ……
Contact hole.

Claims (2)

(57) [Claims] 1. A polycide wiring region having a laminated structure of a polysilicon layer and a silicide layer formed at a predetermined position on a semiconductor substrate with an insulating oxide film interposed between the polycide wiring region and the surface of the semiconductor substrate. An insulating film formed so as to cover the insulating film and the silicide layer,
One contact hole formed so that a part thereof reaches the polysilicon layer and the remaining part reaches the semiconductor substrate adjacent to the formation position of the polycide wiring region;
A semiconductor device comprising at least a wiring conductive layer formed in the contact hole so as to be in direct contact with both the polysilicon layer and the semiconductor substrate in the contact hole. 2. A step of forming a polycide wiring region having a laminated structure of a polysilicon layer and a silicide layer at a predetermined position on a semiconductor substrate through an insulating oxide film, and the polycide wiring region and the exposed semiconductor substrate. A step of forming an insulating film to cover the surface, and a part of the insulating film and the silicide layer penetrating to the polysilicon layer and the remaining part of the semiconductor substrate adjacent to the formation position of the polycide wiring region. Semiconductor comprising a step of forming one reaching contact hole and a step of forming a conductive layer for wiring, which is in direct contact with both the polysilicon layer and the semiconductor substrate in the contact hole, in at least the contact hole Device manufacturing method.