JPH0936222A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of photomasks used at the time of forming multilayered wiring by the etching conductive films other than a conductive film and, at the same time, leaving parts of the other conductive films in the area corresponding to an opening formed through an interlayer insulating film and the conductive film. SOLUTION: Resist patterns 4a and 4b are formed by applying a resist film to the surface of an interlayer insulating film 3 and patterning the resist film by using a photolithographic technique. Then the insulating film 3 is etched by using the patterns 4a and 4b as masks and an alloy layer 2 is etched. After the alloy layer 2 is etched, the patterns 4a and 4b are removed. Thus wirings 2a and 2b are formed in the same patterns as the patterns 4a and 4b and the parts 3a and 3b of the insulating film 3 are left on the wirings 2a and 2b. In addition, an opening 5 is formed through the wiring 2a and the left part 3a of the insulating film 3 and a buried W layer is formed in the opening 5 and electrically connected to the wiring 2a. Therefore, only one photomask is required at the time of forming the first-layer wiring, because the wiring can be formed through one time of photolithographic process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having multi-layer wiring and a manufacturing method thereof.

In the manufacturing cost of a large scale integrated circuit (LSI), the cost of the photolithography process occupies a large proportion. In order to reduce the manufacturing cost, it is preferable to reduce the number of photomasks and the number of photolithography steps. Also, as the number of photomasks increases, it is necessary to design with an allowance for alignment between masks.
This is against the miniaturization of I. From the viewpoint of reducing the LSI manufacturing cost and miniaturization, a semiconductor device having a structure with a small number of photomasks is desired.

[0003]

2. Description of the Related Art A conventional multilayer wiring forming method will be described with reference to FIG. As shown in FIG. 5A, an aluminum (Al) layer is formed over the substrate 100 having an insulating surface,
This Al layer is patterned to form an Al wiring 101. At this time, a photolithography process using the photomask M ₁ having the pattern of the Al wiring 101 is performed.

In FIG. 5B, an interlayer insulating film 102 is formed to cover the surfaces of the Al wiring 101 and the substrate 100.
Next, a contact hole is formed in the interlayer insulating film 102 and A
Part of the surface of the l-wiring 101 is exposed. At this time, a photolithography process using a photomask M ₂ having a contact hole pattern is performed. Next, the contact hole is filled with a tungsten (W) plug 103.

As shown in FIG. 5C, the interlayer insulating film 10 is formed.
An Al layer is formed on the Al layer 2, and the Al layer is patterned to form an Al wiring 104. At this time, the Al wiring 10
A photolithography process using a photomask M ₃ having a pattern of No. 4 is performed.

In FIG. 5D, an interlayer insulating film 105 covering the surfaces of the Al wiring 104 and the interlayer insulating film 102 is formed. Next, a contact hole is formed in the interlayer insulating film 105 to expose a part of the surface of the Al wiring 104. At this time, a photolithography process using a photomask M ₄ having a contact hole pattern is performed. Next, the inside of the contact hole is filled with the W plug 106.

In this way, the wiring including the Al wiring 101 is formed.
It is possible to form a wiring layer including the wiring layer and the Al wiring 104.
Wear. In order to form these two wiring layers,
Ku M ₁~ M_FourUsing 4 kinds of photo masks,
Photolithography process.

[0008]

As described with reference to FIG. 5, the conventional method requires two photomasks for each wiring layer. In today's LSI integration, multi-layer wiring of 5 layers may be used. If five layers of wiring layers are formed by the conventional method, ten photomasks are required. That is, 10 photolithography steps are required, and the large number of steps reduces the manufacturing cost.
It is a factor that hinders miniaturization.

An object of the present invention is to provide a semiconductor device capable of reducing the number of photomasks at the time of forming a multi-layer wiring and a manufacturing method thereof.

[0010]

According to one aspect of the present invention, a step of forming a conductive film on a substrate having an upper surface, a step of forming an interlayer insulating film on the conductive film, An etching mask layer including a pattern, wherein the at least one pattern is a region having a width narrower than a minimum interval between the plurality of patterns, and the etching has a non-mask region in which a surface of the interlayer insulating film is exposed. Forming a mask layer on the interlayer insulating film; etching the interlayer insulating film and the conductive film using the etching mask layer as a mask; and opening the interlayer insulating film and the conductive film. The region corresponding to the portion to form another conductive film conformally, and etching the other conductive film and opening the interlayer insulating film and the conductive film. The method of manufacturing a semiconductor device including the step of leaving the other conductive film is provided in a region corresponding to.

According to another aspect of the present invention, a substrate having an insulating surface, a wiring formed on the insulating surface, and a planar shape formed on the wiring and having substantially the same plane shape as the wiring. A conductive pad that is formed from the insulating surface to the upper surface of the insulating film in a region for electrically connecting the insulating film to the wiring and another wiring in the upper layer, and is electrically connected to the wiring. A semiconductor device having a plug member is provided.

[0012]

[Function] The conductive film and the interlayer insulating film formed thereon are
Etching is performed using the same etching mask to form wiring and contact regions. The contact region formed at this time reaches at least the conductive film. Typically,
The contact region penetrates the conductive film, and the underlying surface of the conductive film is exposed in the contact region. On the side wall of the contact region, the surface of the interlayer insulating film is exposed above and the surface of the conductive film is exposed below.

The contact region is filled with another conductive film.
At the same time, another conductive film is deposited on the surface other than the contact region. By depositing the contact region with a width smaller than the minimum width between the wirings, only the contact region can be embedded. By etching the other conductive film, it is possible to remove the other conductive film formed on the surface other than the contact region, leaving only the portion embedded in the contact region. The side wall of the other conductive film left in the contact region is in contact with and electrically connected to the conductive film at the lower side part thereof.

In this manner, the wiring pattern and the contact region for connection with the upper wiring can be formed by one photolithography process using one photomask.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring forming method according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1A, an aluminum copper alloy layer 2 having a thickness of 1 μm is formed on the surface of a substrate 1 having an insulating surface, and an interlayer insulating film 3 having a thickness of 1 μm made of a silicon oxide film is formed on the aluminum copper alloy layer 2. To form. The aluminum-copper alloy layer 2 is formed by sputtering, for example, and the interlayer insulating film 3 is formed by using silane as a source gas, for example.
It is formed by chemical vapor deposition (CVD) at 50 ° C.

Next, a resist film is applied on the surface of the interlayer insulating film 3, and the resist film is patterned by using a photolithography technique to form resist patterns 4a and 4b.

FIG. 1B shows the resist patterns 4a and 4a.
The planar shape of b is shown. The resist patterns 4a and 4b extend substantially parallel to each other in the lateral direction of the drawing. Openings 5 are formed in the vicinity of both ends of the resist pattern 4a. The opening 5 has, for example, a square shape whose one side is W1. Both ends of the resist pattern 4b extend to regions not shown. The width W2 between the resist patterns 4a and 4b is larger than the length W1 of one side of the opening 5.
Note that FIG. 1A is a cross-sectional view taken along dashed-dotted line A1-A1 in FIG.

As shown in FIG. 1C, the interlayer insulating film 3 is etched using the resist patterns 4a and 4b as masks. The etching of the interlayer insulating film 3 is performed by reactive ion etching (RIE) using CF ₄ , CHF ₃ as an etching gas, for example. Then, the alloy layer 2
Is etched. The alloy layer 2 is etched by, for example, reactive ion etching (RIE) using Cl ₂ and BCl ₃ as etching gas. Note that if the alloy layer outside the resist pattern 4a can be removed, the alloy layer in the opening 5 does not necessarily have to be completely removed, and a part of the alloy layer 2 may remain at the bottom. Alloy layer 2
After etching, the resist patterns 4a and 4b are removed.

Thus, the wirings 2a and 2b having the same pattern as the resist pattern shown in FIG. 1B are formed. Interlayer insulating films 3a and 3b remain on the wirings 2a and 2b, respectively. An opening 5 is formed in the wiring 2a and the interlayer insulating film 3a.

As shown in FIG. 1D, the W layer 6 is isotropically formed so as to cover the entire surface exposed on the substrate 1.
The W layer 6 is, for example, a reduced pressure C using WF ₆ as a source gas.
It is formed by VD. At this time, the opening 5 is filled with W, and the W layer 6 is formed along the sidewalls of the wirings 2a and 2b and the interlayer insulating films 3a and 3b and the surface of the substrate 1 in the region between the wirings 2a and 2b. To do so. To form such a W layer by isotropically growing so that the thickness of the W layer 6 is thicker than half the length W1 of one side of the opening 5 and thinner than half the width W2. You can

As shown in FIG. 2A, the W layer 6 is etched back by isotropic etching. The W layer 6 is etched by dry etching using SF ₆ as an etching gas, for example. The W layers other than the W layer in the opening 5 are removed, and the W buried layer 6a remains only in the opening 5. The W buried layer 6a contacts the side wall of the wiring 2a at a lower portion thereof and
a. Note that isotropic etching does not necessarily have to be used as long as it is only for separating wiring. For example, even if the W layer on the flat surface is removed by anisotropic etching, electrically isolated wiring can be obtained.

As shown in FIG. 2B, the interlayer insulating film 7 is embedded in the concave portion on the surface of the substrate for planarization. For example, C
Ozone TEOS (tetraethoxyorthosilane) film is formed by VD, and chemical mechanical polishing (C
The surface is flattened by MP). In the opening of the opening 5,
The upper surface of the W buried layer 6a is exposed.

As shown in FIG. 2C, FIG.
The second layer wiring is formed similarly to the formation of the first layer wiring described in (D) and FIGS. 2A and 2B. W buried layer 6
The wiring 12 of the second layer is formed in the area including the area where a is formed.
a is formed. The second layer wiring 12b is also applied to other areas.
Are formed.

Interlayer insulating films 13a and 13b are formed on the wirings 12a and 12b, respectively. The wiring 12a is electrically connected to the interlayer insulating film 13a and the W burying layer 16a buried in the opening provided in the wiring 12a. The region where the wiring is not formed is filled with the interlayer insulating film 17, and the surface is flattened. Figure 1 (A)
It is also possible to form the wiring of the third layer or more by repeating the steps similar to the steps described in (1) to (D) and FIGS. 2 (A) and 2 (B).

In the above embodiment, the photolithography process for forming the wiring of the first layer is only one time shown in FIG. 1A, and the photomask is the one shown in FIG.
Only one. Also in the formation of the wiring of the second layer or more, similarly, the photolithography process for each layer is performed only once, and the number of photomasks is one.

Although the opening 5 shown in FIG. 1B has a square shape in the above embodiment, it does not have to be a square shape. For example, the rectangle may have a short side shorter than the width W2 between the resist patterns 4a and 4b.

FIG. 3 shows a mask pattern used in a method for forming a multi-layer wiring according to another embodiment. Only the mask pattern is different from the embodiment described with reference to FIGS. 1 and 2, and the steps of forming the multilayer wiring are the same.

The wiring patterns 20a and 20b extend in the lateral direction of the figure substantially parallel to each other. Wiring pattern 20
In the vicinity of both ends of a, the pattern is divided by a slit having a width W3 formed in a direction orthogonal to the length direction. Width W4 between wiring patterns 20a and 20b
Is larger than the width W3 of the slit. One-dot chain line A in FIG.
The cross section at 3-A3 corresponds to the cross-sectional views shown in FIGS.

In the step of forming the W layer 6 shown in FIG. 1D, if the thickness of the W layer 6 is set to be half the width W3 of the slit or more, the slit portion can be filled with the W layer 6.
Therefore, similarly to the case where the opening 5 is provided in the wiring 2a, it is possible to connect to the upper wiring by the W burying layer buried in the slit portion.

In the mask pattern shown in FIG. 1B, it is necessary to make the width of the wiring pattern 4a wider than the width W1 of the opening 5 and to secure a region for alignment margin. On the other hand, in the case of the mask pattern shown in FIG. 3, it is not necessary to secure a region in which the wiring is formed in the vertical direction of the slit. Therefore, the wiring width can be reduced, and it is possible to form higher density wiring.
Further, since the opening is open at the top and bottom of the figure, the microloading effect is small.

In the above description, only the multilayer wiring layer is shown and described, and the semiconductor element structure is omitted. FIG.
An example of a semiconductor device manufactured according to an example of the present invention will be shown.

A field oxide film 23 is formed on the surface of the n-type silicon substrate 21 to define an active region. A p-type well 22 is formed in the active region, and an n-channel MOSFET composed of an n ⁺ type region 25 as a source / drain region and a gate electrode 24 having an insulated gate structure is formed in the p-type well 22. ing.

An interlayer insulating film 26 is formed on the active region and the field oxide film 23. The interlayer insulating film is
It is formed by depositing a TEOS-based oxide film of 1.0 μm and then flattening the surface by etching back.

A contact hole is formed in a portion of the interlayer insulating film 26 corresponding to the n ⁺ type region 25. Interlayer insulating film 26
A stack 27a of a contact metal layer made of a Ti layer having a thickness of 20 nm and an adhesive layer made of a TiN layer having a thickness of 80 nm is deposited on the surface by sputtering.

A blanket W layer is deposited by a single wafer type low pressure CVD apparatus. The thickness of the blanket W layer is approximately equal to or more than about 1/2 the diameter of the contact hole. SF
Etch back with a fluorine-based gas such as ₆ and an inert gas to remove the blanket W layer, the adhesive layer, and the contact metal layer except in the contact holes. In this way, the contact layer is filled with the W layer 27.

A laminated layer 28a of a contact metal layer made of a Ti layer having a thickness of 20 nm and an adhesive layer made of a TiN layer having a thickness of 80 nm by sputtering, and an Al-Si-Cu layer having a thickness of 600 nm serving as a first wiring layer. 28 is formed.
Further, an interlayer insulating film 29 is formed on the Al-Si-Cu layer 28.
Is deposited.

The interlayer insulating film 29, the first-layer wiring layer 28, and the laminated layer 28a are patterned into a desired shape to form the first-layer wirings 28, 28a and the interlayer insulating film 29 left thereon. At the same time, a contact hole is formed in a region to be in contact with the second wiring layer. In this way, the n ⁺ type region 25 and the first layer wiring 28 can be electrically connected.

A contact metal layer 31a made of a Ti layer having a thickness of 20 nm and an adhesive layer 31a made of a TiN layer having a thickness of 80 nm are formed on the entire surface exposed on the substrate by sputtering.
Is deposited.

A blanket W layer is deposited by a single wafer type low pressure CVD apparatus. The thickness of the blanket W layer is approximately equal to or more than about 1/2 the diameter of the contact hole. SF
Etch back with a fluorine-based gas such as ₆ and an inert gas to remove the blanket W layer, the adhesive layer, and the contact metal layer except in the contact holes. In this way, the contact layer is filled with the W layer 31.

An interlayer insulating film 30 is buried in a region on the interlayer insulating film 26 where the first layer wiring 28 is not formed, and the surface is flattened. The interlayer insulating film 30 is formed by flattening the surface by etching back after depositing a TEOS-based oxide film.

A stack 32a of a contact metal layer made of a Ti layer having a thickness of 20 nm and an adhesive layer made of a TiN layer having a thickness of 80 nm by sputtering, and an Al--Si--Cu layer having a thickness of 600 nm serving as a second wiring layer. 32 is formed.
In this way, the first-layer wiring 28 and the second-layer wiring layer 3
2 can be electrically connected. Since the patterning of the first wiring layer and the formation of the contact holes are performed at the same time, the first wiring can be formed by one photolithography process using one photomask.

Wiring layers above the second wiring layer 32 can be similarly formed. In the above embodiment, the case where the TEOS oxide film is used as the interlayer insulating film and the aluminum-copper alloy or Al-Si-Cu alloy is used as the wiring has been described, but other materials may be used. Although the case where Ti is used as the contact metal and the TiN layer is used as the adhesive layer has been described, other materials may be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0044]

As described above, according to the present invention,
Since the wiring layer can be patterned and the contact hole can be formed at the same time, one wiring layer can be formed by one photolithography process using one photomask. Since the number of steps for performing photolithography is reduced, manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a wiring layer and a plan view of wiring for explaining a multilayer wiring forming process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a wiring layer for explaining a multilayer wiring forming process according to an example of the present invention.

FIG. 3 is a plan view of a wiring pattern formed by a multi-layer wiring forming method according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device manufactured by a method for forming a multilayer wiring according to an example of the present invention.

FIG. 5 is a sectional view of a wiring layer for explaining a multilayer wiring forming process according to a conventional example.

[Explanation of symbols]

 1 Substrate having insulating surface 2 Aluminum copper alloy layer 2a, 2b, 12a, 12b Wiring 3, 7, 17 Interlayer insulating film 4a, 4b Wiring pattern 5 Contact hole 6 W layer 6a, 16a W embedded layer

Claims (5)

[Claims] 1. A step of forming a conductive film on a substrate having an upper surface, a step of forming an interlayer insulating film on the conductive film, and an etching mask layer including a plurality of patterns, One pattern is a region having a width narrower than the minimum interval between the plurality of patterns, and the etching mask layer having a non-mask region where the surface of the interlayer insulating film is exposed is formed on the interlayer insulating film. And a step of etching the interlayer insulating film and the conductive film by using the etching mask layer as a mask, and another conductive film filling a region corresponding to the opening of the interlayer insulating film and the conductive film. And forming the other conductive film in a region corresponding to the opening of the interlayer insulating film and the conductive film while etching the other conductive film. The method of manufacturing a semiconductor device including a to process. 2. The step of forming the other conductive film is performed on the entire surface exposed on the substrate to form wirings that are at least half the width of the contact region and are adjacent to each other formed of the conductive film. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of isotropically depositing the other conductive film having a film thickness smaller than a half of the minimum width. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the non-mask region is an opening formed inside the pattern. 4. The unmasked area is the at least one.
3. The method for manufacturing a semiconductor device according to claim 1, wherein two patterns are cut to form a band-shaped region having a width narrower than the minimum interval. 5. A substrate having an insulative surface, wiring formed on the insulative surface, an insulating film formed on the wiring and having substantially the same planar shape as the wiring, and the wiring. And a conductive embedding member electrically connected to the wiring, which is formed from the insulating surface to the upper surface of the insulating film in a region for electrical connection with another wiring in the upper layer. .