JP2005354046A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with which the occurrence of a bridge film recess or film release is suppressed and inter-wiring capacitance can be reduced. <P>SOLUTION: A method of manufacturing a semiconductor device includes: forming a wiring pattern having a first area and a second area of which wiring density is lower than that of the first area, on a semiconductor substrate 1; forming a temporary film to cover the wiring pattern; etching back the temporary film so as to expose at least a surface of the wiring pattern; selectively removing the temporary film in the second area; covering the wiring pattern with a bridge film 16 after the selective removal of the temporary film; removing the temporary film in the first area; and forming an air gap 17 under the bridge film 16 between wiring of the wiring patterns in the first area. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a crosstalk capacitance between wirings formed on a semiconductor substrate via an insulating film is reduced.

  In recent years, semiconductor devices such as discrete devices and large-scale integrated circuits (LSIs) have been further miniaturized and the degree of integration has been steadily improving. As the degree of integration increases as described above, the wiring pitch of the plurality of wirings formed on the insulating film on the semiconductor substrate must be further reduced. In addition, multi-layer wirings in which wirings are stacked in layers over an insulating film on a semiconductor substrate are often used.

  In such semiconductor device manufacturing technology, this is an insulating film with a low relative dielectric constant (ε) as a measure for reducing inter-wiring capacitance, particularly for memory / logic devices. Development of low dielectric constant films is progressing. As one of the methods, a technique using an air gap (Air Gap), which is known as an ultimate low dielectric constant using air having a relative dielectric constant close to 1, is being developed.

  A semiconductor device using an air gap is disclosed (for example, see Patent Document 1). The disclosed semiconductor device includes a first insulating film, a space region formed by removing the second insulating film, and an interlayer insulating film formed by the third insulating film, and A multilayer wiring is constituted by the lower layer wiring and the upper layer wiring. In order to form the space region, first, a first insulating film is formed on a semiconductor substrate so as to cover a lower layer wiring in which a plurality of wirings are arranged adjacent to each other. A second insulating film such as a photoresist made of a softening material is stacked over the first insulating film. A third insulating film is stacked over the second insulating film. Then, an upper layer wiring is formed on the third insulating film. Next, the second insulating film is removed and the trace is used as a space region. In this way, an interlayer insulating film having a space region with air as an insulator is formed between the upper and lower wirings. Since the space region exists in a part of the interlayer insulating film, the relative dielectric constant of air is small, and as a result, the inter-wiring crosstalk capacitance is reduced. In some cases, upper and lower wirings are supported by a plurality of pillars, and air is used for an interlayer insulating film between upper and lower wirings (for example, see Patent Document 2).

  In general, an air gap is formed by forming a layer called a temporary film between wirings, and further laminating an insulating film such as a bridge film or a passivation film on the temporary film between the wirings and the wiring, and then some reaction. A technique is employed in which a temporary film is extracted using the extracted film as an air gap. In this case, if the part to be extracted is a relatively large area, the bridge strength does not have and the bridge collapses, and there is a possibility that film peeling or the like may occur. No measures are required.

To explain this phenomenon, first, a temporary film such as a photoresist is formed so as to cover a wiring pattern including pads on the entire surface of the semiconductor substrate. Next, the temporary film is etched back to expose the surface of the wiring pattern. Next, an insulating film (usually called a bridge film) is formed on the semiconductor substrate so as to cover the temporary film and the wiring pattern. Thereafter, the temporary film is removed by etching or the like to form an air gap between the wirings of the wiring pattern. The air gap formed in the high wiring density region where a plurality of wirings are arranged close to each other has a narrow interval, so the bridge film as an insulating film on the air gap is unlikely to sink, but the wiring density is high. Since the air gap between the pads in the peripheral part of the region has a large area, the bridge film often sinks.
JP-A-8-306775 JP-A-3-126247

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the occurrence of bridge film depression and film peeling and reducing the capacitance between wirings.

  According to the first aspect of the present invention, (b) a wiring pattern having a first region and a second region having a wiring density lower than that of the first region is formed on a semiconductor substrate; Forming a temporary film so as to cover; (c) etching back the temporary film so that at least a surface of the wiring pattern is exposed; (d) selectively removing the temporary film in the second region; After selectively removing the temporary film, the wiring pattern is covered with a bridge film, (f) the temporary film in the first region is removed, and the wiring pattern in the first region is under the bridge film between the wires. A method of manufacturing a semiconductor device is provided that includes forming an air gap.

  According to the second aspect of the present invention, (a) a temporary film is formed on the semiconductor substrate, and (b) the temporary film is selectively removed, and the pattern density is higher than that of the first region and the first region. Forming a temporary film pattern having a low second region, (c) forming a metal film on the semiconductor substrate so as to cover the temporary film pattern, and (d) exposing the surface of the temporary film pattern of the metal film. Etch back to form a wiring pattern, (e) after forming the wiring pattern, after selectively removing the temporary film in the second region, (f) after selectively removing the temporary film, A semiconductor device comprising: covering a wiring pattern with a bridge film; and (g) removing a temporary film in the first region to form an air gap under the bridge film between the wirings in the wiring pattern in the first region. A manufacturing method is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can suppress generation | occurrence | production of bridge | bridging film depression and film | membrane peeling and can reduce the capacity | capacitance between wiring can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(First embodiment)
In the first embodiment of the present invention, an example applied to a discrete device will be described. As shown in FIG. 1, the semiconductor device according to the first embodiment is a bipolar transistor provided with respective wiring patterns of an emitter, a collector and a base on the surface of a semiconductor substrate 1 made of silicon single crystal. The surface of the semiconductor substrate 1 on which the transistor is formed is covered with an insulating protective film (not shown). A wiring pattern made of aluminum (Al) or the like is formed on the insulating protective film.

  The wiring pattern includes an emitter lead electrode (pad) 11a electrically connected to the emitter region of the transistor, an emitter lead wire 11 electrically connected thereto, and a collector lead electrode electrically connected to the collector region of the transistor. (Pad) 12a and collector lead wiring 12 electrically connected thereto, base lead electrode (pad) 13a electrically connected to the base region of the transistor, and base lead wiring 13 electrically connected thereto Contains.

  In the wiring pattern, the wiring spacing S between adjacent wirings is close to, for example, 5 μm or less and the influence of the crosstalk capacitance is large (first region), and the wiring spacing is wide and the crosstalk capacitance It is divided into a region (second region) that is relatively unaffected and has a low wiring density. A region dividing boundary 10 that divides the two regions is formed in a region surrounded by the emitter pad 11a, the collector pad 12a, and the base pad 13a. The inside of the region dividing boundary 10 is a region having a high wiring density, and the outside of the region dividing boundary 10 is a region having a low wiring density or a region having no wiring.

  In the first embodiment, as shown in FIG. 2, a bridge film 16 is provided so as to cover the wiring pattern. An air gap 17 is provided between the bridge film 16 and the semiconductor substrate 1 to insulate the wirings in a region having a high wiring density. The wiring interval S is preferably about 5 μm or less. When the wiring interval S exceeds 5 μm, the bridge film 16 on the air gap 17 may be depressed, and film peeling may occur. As a result, the manufacturing yield decreases. Here, 5 μm is set as a reference interval for the depression with respect to the wiring interval S.

  In the first embodiment, the air gap 17 is formed in a planar wiring pattern composed of one layer, not a multilayer. The thickness of the Al wiring constituting the wiring pattern is 1 μm. Although not shown, the surface of the Al wiring is protected by a protective film such as a silicon oxide film having a thickness of about 0.05 μm. Further, the spacing S between the wirings in the region having a high wiring density in the first embodiment is, for example, 1 μm.

  Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 3, on the surface of the semiconductor substrate 1 on which a protective insulating film (not shown) is formed, a wiring pattern including wiring connected to the emitter, collector, and base of the bipolar transistor and a lead electrode is formed. Form. The wiring pattern has emitter, collector, and base lead wires 11, 12, and 13. For example, Al or the like is used as the wiring material. The Al film serving as the lead wiring is deposited on the entire surface of the semiconductor substrate 1 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Thereafter, it is obtained by patterning into a shape as shown in FIG. 1 by photolithography (photographic etching method).

  A protective film (not shown) such as a silicon oxide film is formed on the surface of the Al film. Next, as shown in FIG. 4, a temporary film 14 having a thickness of about 1.5 μm is formed on the semiconductor substrate 1 so as to cover the wiring pattern. For the temporary film 14, for example, a photoresist or a similar material is used. In the first embodiment, a positive type photoresist is used.

  Thereafter, as shown in FIG. 5, the temporary film 14 is etched back by, for example, anisotropic etching such as reactive ion etching (RIE) to have a thickness of about 0.8 μm. Next, as shown in FIG. 6, a photomask light-shielding portion 15 is arranged in a region with high wiring density by photolithography, exposed, and developed to remove the temporary film 14 in the region with low wiring density.

  Next, as shown in FIG. 7, a bridge film 16 such as spin-on-glass (SOG) having a thickness of about 0.5 μm is formed on the semiconductor substrate 1 so as to cover the wiring pattern and the temporary film 14 between the wirings. The SOG film used as the bridge film 16 covering the air gap is a film made of silicon oxide and formed by a spin coating method, and has excellent flatness.

  Thereafter, as shown in FIG. 8, the temporary film 14 formed on the semiconductor substrate 1 is treated with a resist remover made of an alcohol-based organic solvent such as thinner. At this time, since the SOG film used as the bridge film 16 is a porous material, the resist remover dissolves the internal temporary film 14 through the bridge film 16. The temporary film 14 sandwiched between the semiconductor substrate 1 and the bridge film 16 and disposed between the wirings is dissolved and removed, leaving a space later. This space is the air gap 17 and is used as an insulator for insulating the wiring. In this manner, a wiring pattern in which the wirings are insulated by the air gap 17 is formed on the semiconductor substrate 1.

As semiconductor devices are further miniaturized and the pitch of wiring becomes finer, inter-wiring capacitance generated between wirings constituting the wiring pattern formed on the insulating film and between wirings generated between upper and lower wirings in multilayer wiring Capacity will increase. An increase in inter-wiring capacitance adversely affects the operation of the semiconductor device. In the conventional semiconductor device, the insulating film between the wirings is composed mainly of a silicon oxide (SiO ₂ ) film. The SiO ₂ film has a high relative dielectric constant of 3.9, and the inter-wiring capacitance increases. On the other hand, in the first embodiment, the air gap 17 is used in place of an insulating film made of a material such as SiO ₂ . Since the relative dielectric constant of the air gap 17 is as low as about 1, the inter-wiring capacitance can be reduced.

  When the air gap 17 is used, it is difficult to use the bridge film 16 that is an insulating film on the air gap 17 if there is a region with a low wiring density and a wide wiring interval. In the first embodiment, photolithography is introduced and the temporary film 14 in a region having a low wiring density is removed and formed in advance before the air gap 17 is formed. Therefore, the occurrence of depression of the bridge film 16, film peeling and the like is suppressed. In addition, when photolithography is used, since a photoresist or the like is used as the temporary film 14, it is not necessary to newly form a resist material, and the process can be simplified.

  In the above description, after forming the wiring pattern, the temporary film 14 is formed to form the air gap 17. However, the wiring pattern may be formed after patterning the temporary film 14 formed on the semiconductor substrate 1.

  For example, as shown in FIG. 9, the temporary film 14 such as a photoresist applied on the semiconductor substrate 1 is selectively removed by photolithography or the like to form a pattern of the temporary film 14 having the opening 117. As shown in FIG. 10, a metal film 111 such as Al is deposited so as to be embedded in the opening 117 by sputtering, CVD, or the like. The temporary film 14 is covered with a metal film 111. The metal film 111 is etched back by anisotropic etching such as RIE so that at least the surface of the temporary film 14 is exposed. As a result, as shown in FIG. 11, an emitter lead-out line 11, a collector lead-out line 12, and a base lead-out line 13 are formed. Thereafter, the air gap 17 is formed according to the steps shown in FIGS.

(Second Embodiment)
A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to process cross-sectional views of FIGS. 12 to 19 and a process flowchart of FIG. In the semiconductor device according to the second embodiment, a bipolar transistor is formed on a semiconductor substrate, and a wiring pattern is formed on the surface. The second embodiment is different from the first embodiment in that the bridge film to be used is composed of two layers and that a hole is formed in the first bridge film.

  In step S100, as shown in FIG. 12, on the surface of the semiconductor substrate 1 on which a protective insulating film (not shown) is formed, wirings and lead electrodes connected to the bipolar transistors according to the same method as in the first embodiment. Is formed. The wiring pattern includes an emitter, a collector, and a base lead wiring 11, 12, and 13. For example, aluminum is used as the wiring material. The aluminum film to be the wiring is obtained by depositing the entire surface of the semiconductor substrate 1 by CVD, PVD or the like, and then patterning the same shape as in FIG. 1 by photolithography. A protective film (not shown) made of a silicon oxide film having a thickness of about 0.05 μm is formed on the surface of the aluminum film.

  In step S101, as shown in FIG. 13, a temporary film 14 having a thickness of about 1.5 μm, for example, a positive photoresist is formed on the semiconductor substrate 1 so as to cover the wiring pattern.

  In step S102, as shown in FIG. 14, the temporary film 14 is etched back to a thickness of about 0.8 μm by, for example, anisotropic etching RIE.

  In step S103, as shown in FIG. 15, the light-shielding portion 15 of the photomask is arranged in a region with high wiring density by photolithography, exposed, and developed to remove the temporary film 14 in the region with low wiring density.

  In step S104, as shown in FIG. 16, a first insulating film 16a having a thickness of about 0.1 to 0.3 μm is formed on the semiconductor substrate 1 so as to cover the temporary pattern 14 between the wiring pattern and the wiring. . The first insulating film 16a is formed by a plasma CVD method, a TEOS method, or the like.

  In step S105, as shown in FIG. 17, through holes 27 are formed at random positions in the first insulating film 16a by avoiding a region in contact with the wiring pattern, as shown in FIG.

  In step S106, as shown in FIG. 18, the temporary film 14 is processed by pouring a resist remover made of an alcohol-based organic solvent such as thinner into the temporary film 14 from the hole 27. In this way, the temporary film 14 sandwiched between the semiconductor substrate 1 and the first insulating film 16a and disposed between the wirings is dissolved and removed, leaving a space later. This space is the air gap 17 and is used as an insulator for insulating the wiring.

  In step S107, as shown in FIG. 19, a second insulating film 16b having a thickness of about 0.5 μm is formed on the first insulating film 16a. The second insulating film 16b is made of, for example, silicon oxide formed by a plasma CVD method, a TEOS method, or the like. In this manner, a wiring pattern is formed on the semiconductor substrate 1 which is covered with the bridge film 16 having the first and second insulating films 16a and 16b and is insulated between the wirings by the air gap 17.

  In the second embodiment, since photolithography is introduced and the temporary film 14 in a region having a low wiring density is removed before the air gap 17 is formed, the bridge film 16 is depressed, film peeling, etc. Occurrence is suppressed. Further, since a photoresist or the like is used as the temporary film 14 when the photolithography method is used, it is not necessary to newly form a resist material, and the process can be simplified. Furthermore, in the second embodiment, it is possible to efficiently remove the photoresist of the temporary film 14 from the hole 27.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. In the third embodiment, as shown in FIG. 21, a bipolar transistor is formed and a wiring pattern is formed on the surface. In the third embodiment, the wiring structure has two layers, and an air gap is formed between the wirings in the high wiring density areas of the lower wiring pattern and the upper wiring pattern.

An n ⁺ type buried layer 30b and an n type epitaxial layer 30a are grown on a semiconductor substrate 1 made of p type silicon or the like. The bipolar transistor is provided in the epitaxial layer 30a and is formed in a region surrounded by a buried layer 30b and an n ⁺ high concentration layer 30c reaching the buried layer 30b from the surface of the epitaxial layer 30a. An element isolation region 6 such as a shallow trench element isolation (STI) in which a silicon oxide film is embedded is selectively formed in the surface region of the epitaxial layer 30a. A p-type base region 5 is formed on the epitaxial layer 30 a and the element isolation region 6 surrounded by the buried layer 30 b and the high concentration layer 30 c. The p-type base region 5 includes an internal base 5a made of single crystal silicon on the epitaxial layer 30a and an external base 5b made of polycrystalline silicon on the element isolation region 6.

The surface of the epitaxial layer 30a on which the base region 5 is formed is covered and protected by a protective insulating film 39 such as a SiO ₂ film. An n-type emitter lead-out region 3 made of polysilicon or the like is formed on the base region 5 so as to correspond to the upper portion of the epitaxial layer 30a serving as a collector region between the element isolation regions 6. An n-type emitter diffusion region 2 is formed in the surface region of the p-type base region 5 by diffusing n-type impurities from the emitter lead-out region 3. On the other hand, an n-type collector extraction region 4 made of polysilicon or the like formed simultaneously with the emitter extraction region 3 is electrically connected to the high concentration layer 30c.

Thus, an interlayer insulating film 40 such as a SiO ₂ film is formed above the semiconductor substrate 1 on which the bipolar transistor is formed. A first wiring pattern is formed on the interlayer insulating film 40. The first wiring pattern includes, for example, a first emitter electrode 31 made of an aluminum film, a first collector electrode 32, and a first base electrode 33. The first emitter electrode 31 has a connection plug made of tungsten or the like. The first emitter electrode 31 is electrically connected to the emitter lead-out region 3 through a connection plug. The connection plug of the first emitter electrode 31 is in contact with the emitter extraction region 3 through a barrier metal 31a such as titanium nitride (TiN). The first collector electrode 32 has a connection plug made of tungsten or the like. The first collector electrode 32 is electrically connected to the collector lead-out region 4 through a connection plug. The connection plug of the first collector electrode 32 is in contact with the collector extraction region 4 through a barrier metal 32a such as TiN. The first base electrode 33 has a connection plug made of tungsten or the like. The first base electrode 33 is electrically connected to the external base region 5b through a connection plug. The connection plug of the base electrode 33 is in contact with the external base region 5b through a barrier metal 33a such as TiN.

  An air gap 34 and a bridge film 35 are formed to insulate the first wiring pattern between wires. A temporary film (not shown) is formed on the interlayer insulating film 40 on which the first wiring pattern is formed so as to cover the first wiring pattern. The formed temporary film is etched back so that at least the surface of the first wiring pattern is exposed. A region having a low wiring density or a wiring pattern other than a region having a high wiring density where the first base electrode 33, the first emitter electrode 31, the first collector electrode 32, etc. of the first wiring pattern are arranged is formed. The temporary film in the unexposed region is selectively removed by photolithography.

Thereafter, a first insulating film 35a such as SiO ₂ is formed so as to cover the first wiring pattern and the temporary film, and then the temporary film formed in the region having a high wiring density on the interlayer insulating film 40 is removed. An air gap 34 is formed between the wirings in the lever region. The first insulating film 35a is formed by a plasma CVD method, a TEOS method, or the like. In the first insulating film 35a, a plurality of holes (not shown) are formed as in the second embodiment, and the holes are used as an inlet for pouring a resist remover that dissolves the temporary film. A second insulating film 35b is formed on the first insulating film 35a by plasma CVD, TEOS, or the like. In this way, a first wiring pattern is formed on the semiconductor substrate 1 so as to be covered with the bridge film 35 having the first and second insulating films 35a and 35b and insulated between the wirings by the air gap 34.

  A second wiring pattern is formed on the bridge film 35. The second wiring pattern has, for example, a second emitter electrode 311 and a second collector electrode 321 made of an aluminum film. The second emitter electrode 311 is in contact with the first emitter electrode 31 through a barrier metal 311a such as TiN. The second collector electrode 321 is in contact with the first collector electrode 32 through a barrier metal 321a such as TiN.

An air gap 36 and a bridge film 37 are formed in order to insulate the second wiring pattern between wires. A temporary film (not shown) is formed on the bridge film 35 so as to cover the second wiring pattern. The temporary film is etched back so that at least the surface of the second wiring pattern is exposed. A region having a low wiring density other than a region having a high wiring density where the second emitter electrode 311 and the second collector electrode 321 of the second wiring pattern are disposed, or a region where the second wiring pattern is not formed. The temporary film is selectively removed by photolithography. Thereafter, a first insulating film 37a such as SiO ₂ is formed so as to cover the second wiring pattern and the temporary film. The temporary film formed in the high wiring density region on the bridge film 35 is removed, and an air gap 36 is formed between the wirings in this region. The first insulating film 37a is formed by a plasma CVD method, a TEOS method, or the like. A plurality of holes (not shown) are formed in the first insulating film 37a such as SiO _{2 as} in the second embodiment, and the holes are used as an inlet for pouring a resist remover that dissolves the temporary film. A second insulating film 37b is formed on the first insulating film 37a by plasma CVD, TEOS, or the like. In this manner, a second wiring pattern is formed on the semiconductor substrate 1 so as to be covered with the bridge film 37 having the first and second insulating films 37a and 37b and insulated between the wirings by the air gap 36.

Further, a passivation film 38 such as SiO ₂ or silicon nitride (Si ₃ N ₄ ) is formed on the bridge film 37. In this way, the wiring pattern of the semiconductor device is formed.

  In the third embodiment, since the temporary film in the region where the wiring density is low or the region where the wiring pattern is not formed is selectively removed by photolithography in advance, the occurrence of bridge film depression, film peeling, etc. It is suppressed. In addition, when photolithography is used, since a photoresist or the like is used as a temporary film, the process can be simplified without newly forming a resist material. Furthermore, in this embodiment, since an air gap can be appropriately introduced into the multilayer wiring structure, the density of the semiconductor device can be increased.

(Other embodiments)
Although the embodiments of the present invention have been described as described above, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, embodiments and operational techniques will be apparent to those skilled in the art.

  In the first and second embodiments of the present invention, as shown in FIG. 1, the region dividing boundary 10 includes the emitter lead-out wiring 11, the collector lead-out wiring 12. And located on the pattern of the base lead-out wiring 13. The position of the region dividing boundary is not limited to the pattern, and may be projected to a region having a low wiring density. For example, as shown in FIG. 22, fine collector lead-out wirings 12 are arranged at the boundaries of regions with high wiring density. A part of the region dividing boundary 10a is located so as to protrude from the collector lead-out wiring 12 to a region having a low wiring density with a width Wp. As shown in FIG. 23, corresponding to the region dividing boundary 10a, the bridge film 16 protrudes from the outermost pattern of the collector lead-out wiring 12 onto the air gap 17a having a width Wp formed on the region side where the wiring density is low. . In this case, in the photolithography of the temporary film 14 for forming the air gaps 17 and 17a, it is not necessary to precisely position the light shielding portion 15 of the photomask shown in FIGS. Can be simplified. The width Wp of the bridge film 16 protruding from the region dividing boundary 10a to the region having a low wiring density is preferably at least the reference interval of the wiring interval S within 5 μm, preferably about ½ of the reference interval, for example, within about 2.5 μm. . If the width Wp exceeds 2.5 μm, the bridge film 16 on the air gap 17a may be depressed to cause film peeling or the like. As a result, the manufacturing yield decreases.

In the first to third embodiments, examples applied to discrete devices are shown. However, the present invention may be applied to an LSI such as a memory / logic device. In an integrated circuit chip such as an LSI, a plurality of regions having a high wiring density may exist in one chip. In this way, a plurality of regions formed in one chip can be easily made a region using an air gap.

In semiconductor devices such as LSIs, miniaturization and high integration progress, and fine pitch wiring is formed in a plurality of wiring layers. In a wiring pattern formed on an interlayer insulating film or the like, the inter-wiring crosstalk capacitance is increased by the wiring capacity generated between the wirings on the plane of the wiring layer and between the wirings facing each other across the interlayer insulating film. become. The occurrence of crosstalk adversely affects the operation of the LSI. In the conventional LSI, the interlayer insulating film or the like mainly contains SiO ₂ or the like having a relative dielectric constant of about 4 and thus the inter-wiring crosstalk capacitance is increased. By using the air gap instead of the interlayer insulating film, it is possible to reduce the inter-wiring capacitance and suppress the occurrence of crosstalk.

  As described above, the present invention naturally includes various embodiments that are not described herein. Accordingly, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a plan view showing an example of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows an example of the cross section along the AA of the semiconductor device shown in FIG. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 6) which shows an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 1) which shows the other example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 2) which shows the other example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 3) which shows the other example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 6) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 7) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing (the 8) which shows an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a flowchart explaining an example of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows an example of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a top view which shows an example of the semiconductor device which concerns on other embodiment of this invention. FIG. 23 is a diagram showing an example of a cross section taken along line BB of the semiconductor device shown in FIG. 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 11 ... Emitter lead-out wiring 11a ... Emitter lead-out electrode 12 ... Collector lead-out wiring 12a ... Collector lead-out electrode 13 ... Base lead-out wiring 13a ... Base lead-out electrode 14 ... Temporary film 15 ... Light-shielding part 16 ... Bridge film 16a ... First Insulating film 16b ... Second insulating film 17, 17a ... Air gap 27 ... Punched hole

Claims (5)

Forming a wiring pattern having a first region and a second region having a wiring density lower than that of the first region on a semiconductor substrate;
Forming a temporary film so as to cover the wiring pattern;
Etch back the temporary film so that at least the surface of the wiring pattern is exposed,
Selectively removing the temporary film in the second region;
After selectively removing the temporary film, the wiring pattern is covered with a bridge film,
Removing the temporary film in the first region, and forming an air gap under the bridge film between the wirings of the wiring pattern in the first region. Method. Forming a temporary film on a semiconductor substrate;
Selectively removing the temporary film to form a temporary film pattern having a first region and a second region having a lower pattern density than the first region;
Forming a metal film on the semiconductor substrate so as to cover the temporary film pattern;
Etching back the metal film so that the surface of the temporary film pattern is exposed to form a wiring pattern,
After forming the wiring pattern, selectively removing the temporary film in the second region,
After selectively removing the temporary film, the wiring pattern is covered with a bridge film,
Removing the temporary film in the first region, and forming an air gap under the bridge film between the wirings of the wiring pattern in the first region. Method. The temporary film is a photoresist, and the step of selectively removing the temporary film in the second region includes:
A light-shielding portion of a photomask is disposed on the first region;
Exposing the temporary film through the photomask;
The method for manufacturing a semiconductor device according to claim 1, further comprising developing and removing the temporary film in the second region.   The method for manufacturing a semiconductor device according to claim 1, wherein the bridge film is a spin-on-glass film. The method of manufacturing a semiconductor device according to claim 1, wherein a wiring interval between the wirings in the first region is 5 μm or less.

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