JP3172998B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which unnecessary polysilicon is removed after forming a polysilicon pad bridging between gates, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Since the size in a DRAM cell affects the chip size of the DRAM, the miniaturization of the integrated circuit is rapidly progressing along with the miniaturization and high integration. As one of the factors that makes formation difficult in the miniaturization of DRAM cells,
There is intra-cell contact formation.

Conventionally, a method of forming a contact hole is disclosed in, for example, Japanese Patent Publication No. 2577864 (“Method of forming fine contact hole in semiconductor device”).

As shown in FIG. 6, in the method disclosed in this publication, a source electrode 66A and a drain electrode 66B are formed on a silicon substrate 101 provided with an element isolation region 102.
When forming a contact hole thereon, the polysilicon film 1
00 is formed. That is, in FIG. 6A, a polysilicon film 100 is formed on the entire surface of the oxide film 67 and the silicon nitride film 68. Next, in FIG. 6B, the polysilicon film 100 is anisotropically etched until the oxide film 67 and the silicon nitride film 68 are exposed. Membrane 67
A polysilicon pad 100A is formed on the side wall of. Since the polysilicon pad 100A acts as an etching barrier,
As shown in FIG. 6C, a contact hole having a width smaller than the pattern of the contact hole mask is formed.

Next, a detailed description will be given of a process of manufacturing a semiconductor device having a cell array portion and a peripheral circuit portion by utilizing the fact that the size of pad silicon is made larger than the critical dimension of photoresist. In this step, it is particularly difficult to form a contact in the cell. Here, the intra-cell contact includes a bit contact for electrically connecting the diffusion layer and the bit line between the word line and the bit line arranged at the minimum pitch, and a capacitance contact for electrically connecting the diffusion layer and the lower capacitor electrode. Is to form

First, a method of forming a pad larger than a critical dimension of etching by a photoresist will be described with reference to FIG.

In FIG. 7A, a device isolation region 102 is formed on a silicon substrate 101, and a gate oxide film 103, a gate lower electrode 104, and a gate upper electrode 10 are formed thereon.
5. A hard mask oxide film 106 is formed on the gate electrode.

Next, as shown in FIG. 7B, the hard mask oxide film 106 is formed by using a well-known photolithography technique.
Is patterned, and the gate electrode thereunder is also patterned to form a gate electrode.

Next, as shown in FIG. 7C, a side wall oxide film 108 is formed, and only the inside of the cell is etched back using a known photolithography technique.

Next, as shown in FIG. 7D, a polysilicon 109 serving as a pad is formed on the entire surface, and an oxide film 110 serving as a hard mask is formed thereon.

Next, as shown in FIG. 7E, a resist pattern 111 serving as a pad is formed by using a known photolithography technique.

Next, as shown in FIG. 7F, the oxide film hard mask 112 is patterned using the resist pattern as a mask. At this time, since the resist mask is etched, the time for over-etching is increased,
Etching is performed so that an oxide film does not remain on the gate step.

[0013]

However, as shown in FIG. 8 (G), in a subsequent step, an oxide film is formed on the entire surface and etched back to form an oxide film hard mask 112.
When the sidewall oxide film 113 is formed on the side wall, a sidewall oxide film residue 114 is generated at the end of the cell array and the gate step of the peripheral circuit portion.

Next, as shown in FIG. 8H, a photolithography step for protecting the oxide film pattern in the cell portion is performed in order to remove the residue 114 of the sidewall oxide film. However, at this time, the resist pattern edge 11
6 is more likely to be formed outside the cell array end due to misalignment of the underlying gate photoresist and the pad protection photoresist, and variations in the dimensions of the photoresist.

Therefore, as shown in FIG. 8 (I), even if the cell array portion is etched using the resist pattern 115 as a mask, the oxide film residue at the end of the cell array is protected by the photoresist. 114 remains as the oxide film remaining 117.

Finally, as shown in FIG. 8 (J), the pad polysilicon 109 is removed by etching using the mask oxide film as a mask, and the pad polysilicon 20 larger than the critical dimension of the photoresist by the thickness of the oxide film sidewall is obtained. Is formed, but the remaining oxide film 117 serves as a mask, and a pad polysilicon residue 118 is generated.

As described above, when the remaining oxide film 117 and the remaining pad polysilicon 118 occur around the cell array, the entire wafer may be defective.

Accordingly, an object of the present invention is to reliably remove a pad polysilicon residue 118 generated when a pad larger than a critical dimension of a photoresist is formed, and to stably form a DRAM cell.

[0019]

According to the present invention, there is provided a semiconductor device having an arrangement of gate electrodes formed on a substrate and a polysilicon pad bridging the adjacent gate electrodes. A semiconductor device having a cell array portion and a peripheral circuit portion in contact with the cell array portion, wherein a gate electrode width of a portion in contact with the peripheral circuit portion in a peripheral portion of the cell array portion is set to a value in contact with the peripheral circuit portion. The width of the gate electrode is set larger than the width of the gate electrode in the area where no change is made.

Further, a method of manufacturing a semiconductor device according to the present invention
After the polysilicon pad is formed, the polysilicon pad is protected with a photoresist, and the end of the photoresist is placed on the dummy gate to remove the polysilicon remaining outside the photoresist by etching.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view of a semiconductor device according to the present invention. As shown in FIG. 1, in the semiconductor device of the present invention, a gate electrode is formed on a silicon substrate on which an element isolation region is formed, a pad polysilicon is formed between the gate electrodes, and the entire surface is formed on the pad polysilicon. First, a first interlayer insulating film 21 is formed. Then, the first interlayer insulating film 2
A contact hole array is formed in 1 and a bit contact 2
The bit line 23 is laid on the first interlayer insulating film 21 through the gate line 2.

Further, a second insulating layer 24 is formed on the entire surface of the bit line 23. Then, another row of contact holes is formed, and the capacitor lower electrode 2 is connected via the capacitor contact 25.
6 are connected. On each of the capacitor lower electrodes 26, a capacitor insulating film 27 is formed. The capacitor upper electrode 28 is formed on the entire surface of the capacitor insulating film 27.

In the semiconductor device of the present invention, the width of the gate electrode in the periphery of the above-mentioned cell array portion is increased so that no pad polysilicon remains.

Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 2A, an element isolation region 2 is formed on a silicon substrate 1, and a gate oxide film 3, a gate lower electrode 4, a gate upper electrode 5, and a gate electrode An upper hard mask oxide film 6 is sequentially formed.

Next, as shown in FIG. 2B, the hard mask oxide film 6 is patterned using a known photolithography technique, and the gate electrode thereunder is also patterned to form a gate electrode. . At this time, the thickness of the dummy gate electrode 7 at the end of the cell array is made larger than in the cell. The thickness of the gate at this time is as follows: a, the amount of misalignment at the time of the gate photoresist; b, the amount of variation in the gate dimension following the gate photoresist; Assuming that the dimension variation amount of the resist is d, the gate thickness is 2 × (a + b + c + d) or more. Actually, the maximum value of the misregistration amount (mask positioning dimensional accuracy) is about half or less of the gate electrode width W inside the cell array. Therefore, the width of the dummy gate electrode 7 may be 2 W or more.

Next, as shown in FIG. 2C, a sidewall oxide film 8 is formed, and etch back is performed only in the cell.

Next, as shown in FIG. 3D, a polysilicon 9 serving as a pad is formed on the entire surface, and an oxide film 10 serving as a hard mask is formed thereon.

Next, as shown in FIG. 3E, a resist pattern 11 serving as a pad is formed by using a known photolithography technique.

Next, as shown in FIG. 3F, the oxide film hard mask 12 is patterned using the resist pattern 11 as a mask. At this time, since etching is performed on the resist mask, the time for over-etching is increased, and etching is performed so that an oxide film does not remain on the gate step.

Next, as shown in FIG. 4G, a sidewall oxide film 13 is formed on the sidewalls of the oxide hard mask 12 by forming an oxide film on the entire surface and performing etch back. At this time, a sidewall oxide film residue 14 is generated at the end of the cell array and the gate step of the peripheral circuit portion.

Next, as shown in FIG. 4H, in order to remove the sidewall oxidation residue 14, a photolithography step for protecting the oxide film pattern in the cell portion is performed. At this time, the layout is performed so that the end portion 16 of the resist pattern is located on the thick dummy gate 7. At this time, by setting the gate thickness to 2 × (a + b + c + d) or more, even if misalignment or dimensional deviation occurs, the resist end portion is separated from the gate portion, and the actual pattern can be formed without hiding the step portion. Can be formed in a shape as shown in FIG.

Next, as shown in FIG. 4I, using the resist pattern 15 as a mask,
Is removed.

Next, as shown in FIG. 4J, the pad polysilicon 9 is removed by etching using the oxide film hard mask 12 as a mask, and the pad polysilicon 9 is larger than the critical dimension of the photoresist by the thickness of the oxide film sidewall. Form silicon.

Thus, the pad polysilicon 20
After the formation of the first interlayer insulating film 2 as shown in FIG.
1 and the bit contact 22 and the bit line 23
To form Next, a second interlayer insulating film 24 is formed on the bit line, and a capacitor contact 25 is formed. And then,
A capacitor lower electrode is formed on the second interlayer insulating film, and a capacitor insulating film 27 and a capacitor upper electrode are stacked thereon. Thus, a cell portion of the DRAM is formed.

[Second Embodiment] A second embodiment will be described with reference to FIG.

First, the sidewall oxide film 8 is formed through the steps of FIGS. 2A, 2B, and 2C of the first embodiment.

Next, as shown in FIG. 5A, a polysilicon 9 serving as a pad is formed on the entire surface.

Next, as shown in FIG. 5B, a resist pattern 11 serving as a pad is formed by using a known photolithography technique. Next, as shown in FIG. 5C, the pad polysilicon 9 is patterned using the resist pattern 11 as a mask. At this time, by performing etching so as to form a taper, a pad interval is formed to be smaller than a photoresist dimension. However, in the etching with a taper, deposits frequently occur during the etching, and deposits are formed on the gate steps, which serve as a mask to generate polysilicon remaining 40.

Next, as shown in FIG. 5D, in order to remove the remaining polysilicon 40, a photoresist film 15 for protecting the pattern of the pad polysilicon 20 in the cell portion is formed. Perform a photolithography process. At this time, the layout is performed so that the resist pattern end portion 16 is located on the thick dummy gate.

Next, as shown in FIG. 5E, using the resist pattern 15 as a mask, the remaining polysilicon 40 is removed. By the steps so far, the pad polysilicon 20 is formed as in the first embodiment.

Thereafter, as in the first embodiment, D
The RAM cell is completed.

[0044]

According to the present invention described above, it is possible to reliably remove a residue of an oxide film and a residue of a pad polysilicon generated in a peripheral portion of a cell array when a pad larger than a critical dimension of a photoresist is formed. it can. Therefore,
DRAM cells can be formed stably.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a process diagram of a manufacturing method according to the first embodiment.

FIG. 3 is a process diagram of the manufacturing method according to the first embodiment (continued).

FIG. 4 is a process chart of the manufacturing method according to the first embodiment (continued).

FIG. 5 is a process chart of a manufacturing method according to a second embodiment.

FIG. 6 is a manufacturing process diagram of a conventional silicon pad.

FIG. 7 is a conventional manufacturing process diagram in which a silicon pad remains.

FIG. 8 is a conventional manufacturing process diagram in which a silicon pad remains.
(Continued)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 Element isolation region 3,103 Gate oxide film 4,104 Gate lower electrode 5,105 Gate upper electrode 6,106 Hard mask oxide film 7,107 Dummy gate electrode 8,108 Side wall oxide film 9 , 109 Polysilicon 10, 110 Oxide film 11, 111 Resist pattern 12, 112 Oxide hard mask 13, 113 Side wall oxide film 14, 114 Side wall oxide film residue 15, 115 Resist pattern 16, 116 Resist pattern end 117 Oxidation Film remaining 118 polysilicon remaining 20 pad polysilicon 21 first interlayer insulating film 22 bit contact 23 bit line 24 second interlayer insulating film 25 capacitor contact 26 capacitor lower electrode 27 capacitor insulating film 28 capacitor upper electrode 40 polysilicon Remaining

Claims (3)

(57) [Claims] An array of gate electrodes formed on a substrate;
A semiconductor device having a cell array portion having a polysilicon pad bridging the adjacent gate electrodes, and a peripheral circuit portion in contact with the cell array portion, wherein the peripheral circuit portion is a peripheral portion of the cell array portion; A width of the gate electrode in a portion that is in contact with the peripheral circuit portion is twice or more as large as a width of the gate electrode in a portion that is not in contact with the peripheral circuit portion. 2. An arrangement of gate electrodes formed on a substrate,
A cell array portion having a polysilicon pad bridging the adjacent gate electrodes, and a peripheral circuit portion in contact with the cell array portion, and a dummy gate electrode provided in a portion where the cell array portion contacts the peripheral circuit portion A method for manufacturing a semiconductor device, comprising: forming a sidewall oxide film on a side wall of the gate electrode and performing an etch back; and forming a polysilicon film to be a pad over the entire surface, and forming a hard mask thereon. Forming a mono-oxide film; forming a resist pattern to be the pad; patterning a hard mask of the first oxide film using the resist pattern as a mask; And etching back to form a second sidewall oxide film on the side wall of the hard mask of the first oxide film. Forming the end portion of the photoresist pattern on the dummy gate electrode while protecting the second oxide film with a photoresist resist pattern; Removing the second side wall oxide film. 3. An arrangement of gate electrodes formed on a substrate,
A cell array portion having a polysilicon pad bridging the adjacent gate electrodes, and a peripheral circuit portion in contact with the cell array portion, and a dummy gate electrode provided in a portion where the cell array portion contacts the peripheral circuit portion A method for manufacturing a semiconductor device, comprising: forming a sidewall oxide film on a side wall of the gate electrode and performing an etch back ; forming a polysilicon film serving as a pad over the entire surface; and forming a resist pattern serving as a pad. Forming, patterning pad polysilicon using the resist pattern as a mask, forming a photoresist film for protecting the pad polysilicon, and forming an end of the photoresist film on the dummy gate. And the photoresist using the resist pattern as a mask. The method of manufacturing a semiconductor device which comprises a step of removing the polysilicon present in.