KR0135837B1 - Fabrication method of semiconductor device to improve process margin of contact hole - Google Patents

Abstract

A novel method of manufacturing a semiconductor device is disclosed. A first conductive layer is formed on the semiconductor substrate having a limited active region, and a first insulating layer, a second insulating layer, and a second conductive layer are sequentially formed on the resultant. The second conductive layer is patterned to form a conductive layer pattern, and a spacer including a third insulating layer is formed on sidewalls of the conductive layer pattern. The second insulating layer is anisotropically etched using the spacer as an etching mask, and a fourth insulating layer is formed on the resultant. The fourth and first insulating layers may be selectively anisotropically etched to form contact holes exposing the active region and the conductive layer pattern, respectively. The process margin of the contact hole can be improved to prevent short circuits between the conductive layers.

Description

Manufacturing method of semiconductor device with improved process hole margin

1 is a plan view showing a contact hole forming a conventional boundary.

2 is a plan view of a semiconductor device by a conventional method.

3A is a cross-sectional view of the semiconductor device taken along line AA ′ of FIG. 2.

3B is a cross-sectional view of a semiconductor device for explaining the problem of the conventional method.

4A to 4C are cross-sectional views illustrating a conventional borderless contact hole forming method.

5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

6A to 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

30: active area 32: inactive area

34: first conductive layer pattern 36: first insulating layer

38,52: second insulating layer 40: second conductive layer pattern

42,54: third insulating layer 44: fourth insulating layer

42a, 52a: spacer 46, 56: photoresist pattern

48: contact hole with second conductive layer pattern 50: contact hole with active region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving a process margin of a contact hole.

As semiconductor devices become more integrated, not only the width of the wiring but also the space between the wiring and the wiring are significantly reduced. Furthermore, in a memory device using multiple conductive layers, the height between the conductive layer and the conductive layer is further increased by the interlayer insulating film, making the process of forming contact holes between the conductive layers very difficult.

In order to provide a depth of focus in the photolithography process for forming a contact hole, a border should be given to the two conductive layers to be connected by a predetermined distance from the contact hole.

1 is a plan view showing a conventional contact hole forming a boundary, and the portion indicated by a is a boundary. In designing the width and spacing of wiring, this boundary places a lot of constraints.

In general, in memory devices such as DRAM (Dynmaic Random Access Memory), an active diffusion layer (active), a gate electrode, a bit line electrode, a storage electrode, a plate electrode and the like are used as the conductive layers.

Most of these conductive layers are connected to the metal wiring through contact holes.

FIG. 2 is a plan view of a semiconductor device according to a conventional method, in which the metal wiring 5 has contact holes 26, 24, 28 for each of the active diffusion layer 12, the gate electrode 16, the bit line electrode 17, and the like. It is connected through).

3A is a cross-sectional view of the semiconductor device taken along the line AA ′ of FIG. 2.

Referring to FIG. 3A, an active diffusion layer 12 is formed in the active region of the semiconductor substrate 10 whose active region is defined by the field oxide film 14, and a gate electrode 16 is formed thereon. The first insulating layer 3 is formed on the entire surface of the substrate 10 on which the gate electrode 16 is formed, and the bit line electrode 17 is formed thereon. A second insulating layer 7 is formed on the entire surface of the substrate 10 on which the bit line electrode 17 is formed, and on the active diffusion layer 12 and the gate through the contact holes 24, 26, 28. Metal wires 5 connected to the electrodes 16 and the bit line electrodes 17 are formed.

Typically, an oxide film such as BPSG (BoroPhosphoSilicate Glass) or USG is used as an insulating layer to insulate the conductive layers, because the above films are advantageous for planarization. However, as shown in FIG. 3A, in order to ensure sufficient insulation and planarization, an insulating layer must be formed at a predetermined height or more, thereby increasing the vertical gap between the conductive layers. Therefore, the contact hole 24 of the active diffusion layer 12, the contact hole 26 of the gate electrode 16, and the contact hole 28 of the bit line electrode 17 during the connection process between the conductive layer and the metal wiring. Each contact hole formation position is greatly different. Accordingly, although the contact hole 28 with the bit line electrode 17 has already been formed, the etching process for forming the contact hole 24 with the active diffusion layer 12 must be continued, so that the bit line electrode 17 Contact hole 28 is over-etched and etched through the bit line electrode 17 to the first insulating layer 3 below it, causing short with other conductive layers. . In particular, when the margin of the boundary (a) as shown in FIG. 1 is insufficient, such a short circuit easily occurs, and thus the margin for alignment during the photolithography process is very insufficient.

The above problems are shown in FIG. 3B. That is, as shown in FIG. 3B, the contact hole 26 with the gate electrode 16 is formed through the gate electrode 16 to the field oxide film 14 below it, whereby the metal wiring 5 is formed on the substrate. A problem arises in contact with (10). In addition, the contact hole 28 with the bit line electrode 17 is formed through the bit line electrode 17 to the first insulating layer 3 at the lower portion thereof, whereby the metal wiring 5 is connected to the gate electrode 16. The problem of contact occurs.

In order to solve such problems, a method of forming a borderless contact hole has been steadily studied. A representative method thereof is an etching selection method of silicon nitride (SiN) and BPSG, which is disclosed in U.S. Patent No. 4,966,870. It is a method of forming a borderless contact hole using an etch selectivity.

4A to 4C are cross-sectional views illustrating the method of forming the borderless contact hole described above.

Referring to FIG. 4A, a field oxide film 14 is formed on a semiconductor substrate 10 by a conventional device isolation process to separate an active region 12 and an inactive region, and then a gate electrode made of polysilicon on the resultant. (16) is formed. Subsequently, SiN 18 is formed on the resultant, and the BPSG 20 is formed thereon to insulate and planarize the resultant. Next, by forming a photoresist pattern 22 for forming a contact hole on the resultant, a portion where the active diffusion layer contact hole 24 and the gate electrode contact hole 26 are to be formed is opened.

Referring to FIG. 4B, only the BPSG layer 20 is etched using the photoresist pattern 22 as an etching mask. At this time, the etching selectivity of BPSG and SiN is increased by using an etching gas such as BCl ₃ , so that the SiN layer 18 below the etching process of the BPSG layer 20 is not etched.

Referring to FIG. 4C, the active diffusion layer contact hole 24 and the gate electrode contact hole 26 are formed by etching the SiN layer 18 using the photoresist pattern 22 as an etching mask. At this time, by using an etching gas such as CH ₃ F to increase the etching selectivity of the SiN and the oxide, so that the field oxide film 14 of the lower portion during the etching process of the SiN layer 18 is not etched.

According to the above-described conventional method, by using two insulating layers having a large etching selectivity with respect to each other, it is possible to form a borderless contact hole which does not become a problem even if the gate electrode contact hole leaves the gate electrode. Have them.

① The etching process is complicated and lacks stability, such as the etching step of BPSG layer, the etching step of increasing the etching selectivity of BPSG and SiN, and the etching step of increasing the cutting selectivity of SiN and oxide.

(2) When the underlying layer is not a thermal oxide film but a conductive layer such as a BPSG for planarization, such as a bit line electrode or a plate electrode, the conventional method described above cannot be used. That is, even if the SiN layer is formed on each conductive layer, the upper SiN layer must be etched to form a contact hole with the lower conductive layer, so that the upper SiN layer does not play any role.

(3) According to the conventional method described above, the SiN layer remains in all the portions where the contact holes are not formed. This can be an obstacle for subsequent processes. That is, since the wet etch selectivity is different from the vertically adjacent insulating layers, when the two insulating layers are exposed together, a jaw is formed between the two insulating layers, thereby leaving a stringer.

④ The higher the integration of the memory device, the larger the vertical gap between the conductive layers. Generally, in order to overcome this problem, contact holes are formed by separating contact holes according to the high and low levels of the conductive layer and performing a plurality of photolithography processes. do. Therefore, the above-described conventional method cannot be applied to such contact hole separation forming process.

(5) When the SiN layer remains in contact with the semiconductor substrate in the active region, the portion where the SiN layer remains is a path of leakage current.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the problems of the conventional method described above and improve the process margin of the contact hole.

In order to achieve the above object, the present invention comprises the steps of: forming a first conductive layer on a semiconductor substrate having an active region defined; Sequentially forming a first insulating layer, a second insulating layer, and a second conductive layer on the resultant product on which the first conductive layer is formed; Patterning the second conductive layer to form a conductive layer pattern; Forming a spacer including a third insulating layer on sidewalls of the conductive layer pattern; Anisotropically etching the second insulating layer using the spacers as an etching mask; Forming a fourth insulating layer on the resultant product; And selectively anisotropically etching the fourth and first insulating layers to form contact holes exposing the active region and the conductive layer pattern, respectively.

As a material for forming the second insulating layer, a material having an etching rate different from that of the material for forming the first and fourth insulating layers may be used for any anisotropic etching process. Preferably, any one selected from SiN, SiON, and Al ₂ O ₃ groups is used as the material for forming the second insulating layer, and the material for forming the first and fourth insulating layers is selected from BPSG and USG. Use either.

A material constituting the third insulating layer, and having an etching rate similar to that of the material constituting the first and fourth insulating layers for any anisotropic etching process, and etching different from the material constituting the second insulating layer. Use a material with a rate. Preferably, a high temperature oxide is used as a material constituting the third insulating layer.

It is preferable that the width of the conductive layer pattern on which the contact hole is to be formed is wider than that of the bottom surface of the contact hole so that no boundary is provided.

In order to achieve the above another object, the present invention, forming a first conductive layer on a semiconductor substrate having an active region defined; Sequentially forming a first insulating layer and a second conductive layer on the resultant product on which the first conductive layer is formed; Patterning the second conductive layer to form a conductive layer pattern; Forming a spacer including a second insulating layer on sidewalls of the conductive layer pattern; Forming a third insulating layer on the resultant product on which the spacers are formed; And selectively anisotropically etching the third and first insulating layers to form contact holes for exposing the active region and the conductive layer pattern, respectively.

As a material constituting the second insulating layer, a material having an etching rate different from that of the material constituting the first and third insulating layers may be used for any anisotropic etching process. Preferably, any one selected from the group of SiN, SiON, and Al ₂ O ₃ is used as a material constituting the second insulating layer, and the material constituting the first and third insulating layers is any one selected from the group of BPSG and USG. Use one.

According to the present invention, the conductive layer is formed on the lower and upper portions of the conductive layer and the insulating layer having a different etching rate with respect to the insulating layer is left to be wider than the width of the conductive layer, thereby preventing the conductive layer. The contact hole to the layer is prevented from being etched away from the conductive layer and the etching end point is made at the conductive layer position.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

5A illustrates forming the first conductive layer pattern 34 and the first insulating layer 36. A field oxide film is formed on a semiconductor substrate by a conventional device isolation process to divide the substrate into an active region 30 and an inactive region 32. Subsequently, after the conductive material is deposited on the substrate to form the first conductive layer, the first conductive layer pattern 34 is formed by patterning the first conductive layer by a photolithography process. Here, the first conductive layer may be a conductive layer such as a gate electrode, and may be made of polycrystalline silicon doped with impurities of about 1000 to 3000 micrometers in thickness, or polycrystalline silicon doped using a POCl ₃ process. have. In addition, tungsten silicide (WSi), titanium silicide (TiSi), or the like may be used. Next, a low pressure chemical vapor deposition (LPCVD) method or an atmospheric pressure chemical vapor deposition (Atmospheric Pressure Chemical Vapor) method is performed on an insulating material, for example, BPSG or USG, on the resultant formed with the first conductive layer pattern 34. By depositing by the deposition (APCVD) method, the first insulating layer 36 is formed. In the first embodiment, a BPSG having a thickness of about 3000 to 6000 mW is used as the first insulating layer 36. The first insulating layer 36 serves to insulate the first conductive layer pattern 34 below and is planarized by a subsequent annealing process for about 30 minutes at a temperature of about 800 to 900 ° C. This planarization process facilitates the patterning of another conductive layer to be formed over the first insulating layer 36 from subsequent processing.

5B shows forming the second insulating layer 38 and the second conductive layer 40 '. An insulating material, for example, Si ₃ N ₄ , is deposited on the entire surface of the resultant layer on which the first insulating layer 36 is formed to form the second insulating layer 38. Subsequently, a conductive material is deposited on the second insulating layer 38 to form a second conductive layer 40 '. Here, the second conductive layer 40 ′ is a conductive layer such as a bit line electrode, and uses about 500 kW of doped polycrystalline silicon and about 1500 to 2000 kW of tungsten silicide together.

As a material constituting the second insulating layer 38, a material having a high etching selectivity, that is, having a different etching rate from that of the material constituting the first insulating layer 36 in any anisotropic etching process is used. It is desirable to.

5C illustrates forming the second conductive layer pattern 40 and the third insulating layer 42. The second conductive layer pattern 40 is formed by patterning the second conductive layer 40 'by a photolithography process, and then an insulating material such as a high temperature oxide (HTO) or a low temperature oxide (LTO) is LPCVD on the resultant. To form a third insulating layer 42. A material constituting the third insulating layer 42 and having an etching rate similar to that of the material constituting the first insulating layer 36 for any anisotropic etching process and forming the second insulating layer 38. It is preferable to use a material having an etching rate different from that of the material. For example, the second conductive layer pattern 40 may include a bit line electrode. In a portion not shown in FIG. 5C, the active region 30 and the first conductive layer pattern 34 through the contact hole may be formed. All contact parts may be present. However, since the present invention relates to a contact process between metal wiring and lower conductive layers such as the first and second conductive layer patterns 34 and 40, the second conductive layer pattern 40 may be formed in the active region 30. Illustration of the part in contact with the first conductive layer pattern 34 is omitted.

5D shows the step of forming the spacer 42a. The third insulating layer 42 is anisotropically etched to form spacers 42a on sidewalls of the second conductive layer pattern 40. Subsequently, the second insulating layer 38 is anisotropically etched using the second conductive layer pattern 40 and the spacer 42a as an etching mask. In the anisotropic etching process of the second insulating layer 38, when the O ₂ / CHF ₃ etching gas is used, the etching selectivity ratio of Si ₃ N ₄ and SiO ₂ is 15: 1 or more. Therefore, since the etching selectivity of BPSG and HTO is similar, while the etching selectivity of BPSG and HTO with respect to Si ₃ N ₄ is very large, the second insulating layer 38 made of Si ₃ N ₄ is formed of a spacer made of HTO. All parts except the area contained in 42a) are removed.

5E illustrates the step of forming the fourth insulating layer 44 and the photoresist pattern 46. On the resulting product of FIG. 5D, an insulating material such as BPSG composed of about 4 to 6 wt% of phosphorus (P) and about 7 to 10 wt% of boron (B) was prepared by APCVD or LPCVD. The fourth insulating layer 44 is formed by being deposited to a thickness of 7000 Å. Subsequently, an annealing process is performed at about 800 to 800 ° C. for 30 minutes in a nitrogen atmosphere to reflow the fourth insulating layer 44 to planarize the resultant product. Here, the fourth insulating layer 44 plays a role similar to that of the first insulating layer 36. That is, it has both a function of insulating the second conductive layer pattern 40 such as a bit line electrode and a planarization function. The material constituting the fourth insulating layer 44 may have an etching rate similar to that of the material constituting the first and third insulating layers 36 and 42 with respect to any anisotropic etching process. It is preferable to use a material having an etching rate different from that of the layer 38. Next, a photoresist is applied onto the resultant product in which the fourth insulating layer 44 is formed by a photolithography process. The photoresist may use both positive and negative, and may use a thickness of about 10000 ~ 17000Å depending on the type. Subsequently, the second conductive layer is subjected to an exposure process and a development process such as optical lithography, E-beam lithography, and X-ray lithography. A photoresist pattern 46 is formed to open a portion where the contact hole 48 with the pattern 40 and the contact hole 50 with the active region 30 are to be formed. In this case, the photoresist pattern 46 opens all of the portions in which the contact holes of the second conductive layer pattern 40, the first conductive layer pattern 34, and the active region 30 are to be formed. The contact hole forming portion with the conductive layer pattern 34 is not shown.

5F illustrates the step of forming contact holes 48 and 50. By anisotropically etching the fourth and first insulating layers 44 and 36 using the photoresist pattern 46 as an etching mask, the contact hole 48 and the active region of the second conductive layer pattern 40 may be A contact hole 50 with 30 is formed. At this time, a contact hole with the first conductive layer pattern 34 is also formed, but not shown in FIG. 5F. In the anisotropic etching process, the etching selectivity of BPSG to Si ₃ N ₄ may be realized to be equal to or greater than 11: 1 using BCl ₃ etching gas. When the etching selectivity is increased in this manner, even if the contact hole 48 with the second conductive layer pattern 40 is out of the second conductive layer pattern 40 as shown in FIG. with ₃ N ₄ to prevent the second insulating layer 38 is etched is made. Therefore, the contact hole 50 with the active region 30 can be formed stably.

6A to 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

6A illustrates the steps of forming the first conductive layer pattern 34, the first insulating layer 36, the second conductive layer pattern 40, and the second insulating layer 52. After forming the first conductive layer pattern 34 and the first insulating layer 36 by the method described with reference to FIG. 5A, polycrystalline silicon and tungsten silicide doped with conductive materials such as impurities are formed on the resultant. They are stacked in this order to form a second conductive layer. Subsequently, the second conductive layer is patterned by a photolithography process to form a second conductive layer pattern 40 such as a bit line electrode. Next, a material having a high etching selectivity with respect to a material forming the first insulating layer 36 for any anisotropic etching process on the entire surface of the resultant on which the second conductive layer pattern 40 is formed, for example, Si ₃ N _4. Is deposited to form a second insulating layer (52).

FIG. 6B illustrates anisotropic etching of the second insulating layer 52 to form spacers 52a on sidewalls of the second conductive layer pattern 40.

FIG. 6C shows forming the third insulating layer 54 and the contact holes 48 and 50. An insulating material, such as about BPSG or USG, is deposited on the resultant spacer 52a formed by the APCVD method or the LPCVD method to form a third insulating layer 54. Subsequently, the resultant is planarized by reflowing the third insulating layer 54 in an annealing process at about 800 to 900 ° C. for 30 minutes in a nitrogen atmosphere. Here, the third insulating layer 54 has both a function of insulating the second conductive layer pattern 40 such as a bit line electrode and a planarization function, and the first insulating layer 36 for any anisotropic etching process. A material having an etching rate similar to that of the material forming the second insulating layer 52 and having an etching rate different from the material forming the second insulating layer 52 is used. Next, a photoresist is applied on the resultant product in which the third insulating layer 54 is formed by a photolithography process, and the photoresist is exposed and developed to contact the contact hole 48 and the active region with the second conductive layer pattern 40. A photoresist pattern 56 is formed to open a portion where the contact hole 50 with 30 is to be formed. Subsequently, the third and first insulating layers 54 and 36 are anisotropically etched using the photoresist pattern 56 as an etching mask, thereby forming contact holes 48 and actives with the second conductive layer pattern 40. A contact hole 50 with the region 30 is formed. At this time, a contact hole with the first conductive layer pattern 34 is also formed, but not shown in FIG. 6C. Here, in the anisotropic etching process for forming the contact hole, an etching selectivity ratio of BPSG to Si ₃ N ₄ is realized to be equal to or greater than 11: 1 using BCl ₃ etching gas. Therefore, it is possible to prevent the contact hole 48 from the second conductive layer pattern 40 from the second conductive layer pattern 40 by the spacer 52a formed of Si ₃ N ₄ .

Therefore, according to the semiconductor device manufacturing method of the present invention as described above, the following effects can be obtained.

(1) the conductive layer formed on the lower and upper portions of the conductive layer in contact with the metal wiring and another insulating layer having a different etch rate with respect to the insulating layer to remain wider than the width of the conductive layer, thereby The contact hole to the layer is prevented from being etched away from the conductive layer and the etching end point is made at the conductive layer position. Therefore, unnecessary short circuit between the conductive layers can be prevented.

② Since the width of the insulating layer remaining under the conductive layer can be freely adjusted, a borderless contact hole can be formed.

(3) Unlike the conventional method, since all the insulating layers are removed except the predetermined distance under the conductive layer, the method of the present invention can be applied to the conductive layer at any part. It also completely eliminates stringer and leakage current problems.

④ When proceeding to the first embodiment, the contact area with the conductive layer to be in contact with the metal wiring can be realized in the same manner as before. On the other hand, when proceeding to the second embodiment, the contact area is reduced compared to the first embodiment, but the manufacturing process is very simple and can reduce the manufacturing cost.

It is apparent that the present invention is not limited to the embodiment, and many modifications, such as applying to all the conductive layers except the active region, are possible by those skilled in the art within the technical idea of the present invention.

Claims (10)

Forming a first conductive layer on a semiconductor substrate having an active region defined therein; Sequentially forming a first insulating layer, a second insulating layer, and a second conductive layer on the resultant product on which the first conductive layer is formed; Patterning the second conductive layer to form a conductive layer pattern; Forming a spacer including a third insulating layer on sidewalls of the conductive layer pattern; Anisotropically etching the second insulating layer using the spacers as an etching mask; Forming a fourth insulating layer on the resultant product; And selectively anisotropically etching the fourth and first insulating layers to form contact holes exposing the active region and the conductive layer pattern, respectively. The method of claim 1, wherein the material constituting the second insulating layer is characterized by using a material having a different etching rate for any anisotropic etching process than the material constituting the first and fourth insulating layer. Method of manufacturing a semiconductor device. The BPSU and USG group of claim 2, wherein any one selected from the group of SiN, SiON, and Al ₂ O ₃ is used as a material constituting the second insulating layer, and the material constituting the first and fourth insulating layers. Method for manufacturing a semiconductor device, characterized in that using any one selected from. 2. The second insulating layer of claim 1, wherein the third insulating layer is formed of a material having a similar etching rate to a material forming the first and fourth insulating layers for an anisotropic etching process. A method of manufacturing a semiconductor device, characterized by using a material having an etching rate different from that of the material. The method of manufacturing a semiconductor device according to claim 4, wherein a high temperature oxide is used as a material constituting the third insulating layer. The method of claim 1, wherein an area of the conductive layer pattern on which the contact hole is to be formed is wider than an area of the bottom surface of the contact hole so that no boundary is provided. Forming a first conductive layer on a semiconductor substrate having an active region defined therein; Sequentially forming a first insulating layer and a second conductive layer on the resultant product on which the first conductive layer is formed; Patterning the second conductive layer to form a conductive layer pattern; Forming a spacer including a second insulating layer on sidewalls of the conductive layer pattern; Forming a third insulating layer on the resultant product on which the spacers are formed; And selectively anisotropically etching the third and first insulating layers to form contact holes exposing the active region and the conductive layer pattern, respectively. The method of claim 7, wherein the material constituting the second insulating layer is characterized by using a material having a different etching rate for any anisotropic etching process than the material constituting the first and third insulating layer. Method of manufacturing a semiconductor device. The BPSG and USG group of claim 8, wherein any one selected from the group of SiN, SiON, and Al ₂ O ₃ is used as a material constituting the second insulating layer, and the material constituting the first and third insulating layers. Method for manufacturing a semiconductor device, characterized in that using any one selected from. The method of claim 7, wherein an area of the conductive layer pattern on which the contact hole is to be formed is larger than an area of the bottom surface of the contact hole so that no boundary is provided.