JP3172229B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a bit line contact and a storage node contact of a DRAM in a self-aligned manner, that is, a SAC (Self Aline Coctact).

[0002]

2. Description of the Related Art As the density and integration of semiconductor devices have been remarkably increasing, the size of contact holes has been decreasing along with the miniaturization of elements. However, as the miniaturization of elements progresses and the patterning of the wiring layer such as the gate wiring is performed near the resolution limit of the lithography technique, the patterning of the contact hole is performed using the same design rule (minimum size) as the pattern of the wiring layer. It's getting harder to do. In particular, D comprising a transistor and a capacitor
In a memory cell region in which memory cells such as a RAM are integrated at a high density, a contact margin with the wiring cannot be obtained, and patterning is performed in a self-aligned manner so that a contact hole is formed in the wiring. Such a contact is called an SAC and greatly contributes to miniaturization of an element occupation area, but has a problem that a short circuit between a contact and a wiring layer such as a gate wiring easily occurs.

In order to solve this problem, a method referred to as a stopper poly (SP) method has conventionally been used. in this way,
As shown in FIGS. 6A and 6B, after the formation of the gate electrode 32, an insulating film 35 is formed on the side wall, and then a silicon nitride film 36 is formed to prevent oxidation of the semiconductor substrate in a subsequent oxidation step.
Is deposited, and a polycrystalline silicon film 37 is deposited thereon.
A fusible insulating film 38 such as BPSG is deposited on the entire surface as an interlayer film. This makes it possible to use the fact that the selectivity of etching between the polycrystalline silicon film and the BPSG film (interlayer film) is large, and stops the etching of the BPSG film when the polycrystalline silicon film is exposed at the time of etching the contact hole. Next, the polycrystalline silicon film is once removed by a chemical dry etching (CDE) method or the like. By heating in an oxidizing atmosphere, the BPSG film is melted and planarized, and at the same time, the polycrystalline silicon film is also oxidized. Thereafter, the underlying silicon nitride film is etched, and the underlying silicon oxide film is also selected. In order to expose the surface of the silicon substrate.

However, in addition to the problem that the SP method itself has a large number of steps, the peripheral circuit portion having a sufficient contact margin does not require the SP method, and therefore does not require a polycrystalline silicon film as a stopper. Therefore, the polycrystalline silicon film must be selectively formed only in a necessary region, so that it is necessary to remove the polycrystalline silicon film by patterning. In addition, a region using the SP method and a peripheral circuit region not used are required. Therefore, since the film structure is different and the etching conditions are greatly different, it is necessary to perform the etching in a separate step, which causes a further increase in the number of steps, resulting in a serious problem of lowering the product yield.

Furthermore, the stopper film is oxidized once used, so that it cannot be used in a subsequent process.

[0006]

As the element is miniaturized as described above, the contact is formed in a self-aligned manner with the wiring layer in the memory cell portion where the element is densely formed by using the SP method. In the hole opening method, the process becomes complicated, and the patterning and etching of the contact of the peripheral circuit portion where the memory cell portion and the element are not densely packed need to be performed in a separate process, which also causes an increase in the number of processes. It has become.

Further, the stopper film is oxidized once used, and cannot be used in a subsequent process.

The present invention has been made in view of the above circumstances, and has as its object to provide a simple method for forming a contact in a self-aligned manner.

[0009]

Accordingly, in a first aspect of the present invention, a first conductive layer is deposited on a semiconductor substrate via a first insulating film, and a second insulating film is formed on the first conductive layer. On this upper layer, a stopper film, such as polycrystalline silicon, having a sufficiently large etching selectivity with an interlayer insulating film is deposited, a predetermined resist pattern is formed by photolithography, and the stopper film is formed by using anisotropic etching. After patterning the second insulating film and the first conductive layer into the same pattern, further forming an interlayer insulating film as a third insulating film and performing planarization, the first insulating film is formed using lithography technology.
A resist pattern having an opening larger than the pattern size of the conductive layer is formed, and using this as a mask, an interlayer insulating film (third layer) deposited in a contact region to be formed in a self-aligned manner with the first conductive layer pattern After removing the resist, the entire surface is etched back, and a contact hole is opened using the stopper film as a mask. Next, a fourth insulating film such as a nitride film that can be deposited with good step coverage is deposited to leave a side wall, and a side wall insulating film is formed on the side of the first conductive layer exposed to the contact, and at the same time, the surface of the semiconductor substrate is exposed. Then, a second conductive layer is formed so as to be in contact with the surface of the semiconductor substrate.

[0010] Preferably, after the opening of the contact hole, post-oxidation is performed before the formation of the sidewall insulating film in order to improve the insulating property on the side surface of the first conductive layer.

Further, as a more desirable means, a first insulating film serving as a gate insulating film, a first conductive layer serving as a gate electrode, a second insulating film, and selection of etching with an interlayer insulating film on a semiconductor substrate. A stopper film having a sufficiently large ratio is deposited, a predetermined resist pattern is formed by photolithography, and the stopper film, the second insulating film, the first conductive layer, and the first insulating film are formed in the same pattern by anisotropic etching. To form a gate electrode comprising a first conductive layer, form a diffusion layer serving as a source / drain by ion implantation or the like, further form an interlayer insulating film as a third insulating film, and form a After planarization is performed so that the thickness of the insulating film from the semiconductor substrate in the circuit portion becomes the same, the opening larger than the gap between the gate wirings is formed using lithography technology. Forming a resist pattern having, this as a mask, the interlayer insulating film deposited on the substrate surface of the contact region (third insulating film) is etched, after removal of the resist performs the entire surface is etched back,
A contact hole is simultaneously opened in the memory cell portion and the peripheral circuit portion so as to contact at least one of the source and drain using the stopper film as a mask. Then, post-oxidation is performed to insulate the side surface of the first conductive layer exposed in the contact hole, and a fourth insulating film such as a nitride film that can be deposited with good step coverage is deposited to leave sidewalls. At the same time, the surface of the semiconductor substrate is exposed, ion implantation is performed to form an LDD structure of the transistor, and then a second conductive layer such as a storage node electrode or a bit line is formed so as to contact the surface of the semiconductor substrate. I have.

Further, as a more desirable means, after forming a storage node electrode and forming a capacitor or after patterning a bit line, a second interlayer insulating film as a fifth insulating film is further formed to form a memory cell portion and After performing planarization so that the film thickness of the insulating film from the semiconductor substrate in the peripheral circuit portion is the same, a resist pattern having an opening larger than the gap between the underlying wirings is formed by using lithography technology. Second interlayer insulating film (fifth insulating film) deposited on the surface of the substrate in the contact region using the mask as a mask
After etching the resist and removing the resist, the entire surface is etched back, and a contact hole is opened using the stopper film as a mask so as to contact the other of the source and drain. Then, post-oxidation is performed to insulate the side surface of the first conductive layer, the bit line, and the capacitor exposed in the contact hole, and a sixth insulating film such as a nitride film that can be deposited with good step coverage is deposited. At the same time, the surface of the semiconductor substrate is exposed, and a third conductive layer such as a bit line or a storage node is formed so as to contact the surface of the semiconductor substrate.

[0013]

According to the first aspect of the present invention, since the stopper film can be patterned at the same time as the first conductive layer pattern, it is not necessary to separately pattern the stopper, and the first conductive layer pattern has Since this is completely covered with the stopper and remains as it is, this stopper film can be used any number of times in the subsequent process,
The self-alignment of the contacts can be formed with a very reliable and simple process. In addition, an extremely flat surface can be obtained, and an opening in the interlayer insulating film is formed by two etching steps, and the thickness of the interlayer insulating film between the first conductive layer and the second conductive layer is required. Since the thickness is minimized, an increase in the aspect ratio of the contact hole is suppressed, and a highly reliable semiconductor device can be easily obtained.

According to the second aspect of the present invention, in addition to the above effects, a contact between a memory cell portion and a peripheral circuit portion of a DRAM or the like can be simultaneously opened using a stopper (polycrystalline silicon) on a gate wiring as a mask. The number of steps is greatly reduced. This stopper can be used for forming any of bit line contacts, storage node contacts, and contacts of peripheral circuits.

In the conventional SP method, since polycrystalline silicon used once is oxidized, it cannot be used as a stopper in the next contact formation step. Therefore, the gate electrode can be protected until the final step.

Thus, the contact between the memory cell portion and the peripheral circuit portion can be simultaneously opened using the stopper film on the gate wiring as a mask, thereby greatly reducing the number of steps.

Further, when forming the second conductive layer,
After the second conductive layer is formed, an insulating film and a stopper film are sequentially laminated and then patterned into the same pattern, so that not only the gate electrode but also the bit line and the like can be protected, and the reliability is further improved. Can be measured.

Here, the relationship between the thickness of the stopper film, the selection ratio, and the wiring step is such that the etching selection ratio with the interlayer insulating film such as a polycrystalline silicon film is sufficiently large (for example, 20 or more).
The thickness of the stopper film made of the material is t _stop , and the sum of the thicknesses of the gate wiring and the second insulating film formed on the gate wiring is t
_Assuming that the selectivity of the _gate and the etching of the stopper film and the interlayer insulating film is R, the relationship of the formula (1) is established.

_Tstop × R ≧ _tgate (1) In this manner, the contact opening is etched in the SAC of the memory cell portion and the peripheral circuit portion with respect to the insulating film such as polycrystalline silicon deposited on the gate wiring. Simultaneous self-alignment can be performed simultaneously using a film having a large selectivity as a mask, and there is no need to go through a complicated process such as a stopper poly method, so that the number of processes can be reduced.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this method, a contact (SAC) in a memory cell portion and a contact in a peripheral circuit portion are simultaneously formed as shown in a manufacturing process diagram in FIG.

First, a well (not shown) is formed on a silicon substrate 11, and an element isolation region and an element region are formed by a usual method. Inject impurities. Subsequently, a gate oxide film having a thickness of about 10 nm is formed as a first insulating layer by thermal oxidation, and a polycide film 12 (here, polysilicon 100 nm and tungsten silicide 100 nm) serving as a gate electrode is deposited to a thickness of 200 nm. After a silicon oxide film 12s is formed by thermal oxidation to a degree, a silicon oxide film film 13 is formed as a second insulating film on the silicon oxide film 12s by CVD.
Is deposited to a thickness of about 200 nm, and a polycrystalline silicon film 14 is further deposited thereon to a thickness of about 50 nm. Then, a predetermined gate pattern is patterned using a resist by photolithography, and using this as a mask, the polycrystalline silicon film 14, the silicon oxide film 13, and the polycide film 12 are sequentially etched by reactive ion etching (RIE) to form a gate. An electrode 12 is formed. Next, using the gate electrode as a mask, an impurity is introduced into a predetermined position by an ion implantation method to form a diffusion layer D. At this time, the selectivity with respect to the polycrystalline silicon at the time of etching the silicon oxide film 13 is about 20 and the step of the gate wiring is about 400 nm.
× 20 = 1000 nm> 400 nm, which satisfies the relationship of the above equation (1).

Next, as the third insulating film 15, for example, CV
A silicon oxide film is deposited to a thickness of about 800 nm by a method D, and is planarized by a planarization method such as polishing, so that the film thickness from the semiconductor substrate is about 6 in the memory cell portion and the peripheral circuit portion.
Planarization is performed to about 00 nm (see FIG. 1A and
(b)). In the following figures, (a) shows a memory cell area, and (b) shows a peripheral circuit area.

Then, a resist pattern 16 is formed by using a lithography technique, and the resist pattern 16 is used as a mask to simultaneously pattern contact holes in a memory cell portion and a peripheral circuit portion, thereby forming a third insulating film 15 deposited between gate wirings. In the memory cell portion, about 450 nm is etched by the RIE method in the peripheral circuit portion in the same manner as in the prior art, in a self-alignment manner with the polysilicon of the stopper film. At this time, the film thickness t1 of the third insulating film 15 remaining between the gate wirings is the film thickness t on the polycrystalline silicon.
2 is desirable (Fig. 2 (a) and (b)
).

Next, as shown in FIGS. 3A and 3B,
After removing the resist pattern 16, the insulating film on the entire surface of the semiconductor substrate is etched by about 150 nm using an anisotropic etching method. Thereby, the contact hole H is formed in a desired shape. Next, a thermal oxide film is
A silicon nitride film 17 is formed to a thickness of about 0 nm, and a silicon nitride film 17 is deposited to a thickness of about 50 nm using a low pressure (LP) CVD method, and the remaining sidewalls are etched to secure electrical insulation between the gate electrode and the contact. Further, ion implantation may be performed at a predetermined position after the side wall of the silicon nitride film is left. Thus, an LDD structure of the transistor is formed.

Next, as shown in FIGS. 4A and 4B, a third conductive layer 18 made of tungsten or the like serving as a bit line is
0 nm, an insulating film 19 which can be deposited at a low temperature on the third conductive layer is deposited at a thickness of about 200 nm, and polycrystalline silicon 20 as a stopper is deposited on the insulating film 19 at a thickness of about 50 nm. And process.

The polycrystalline silicon remaining between the gate and the bit line is etched in a self-aligned manner simultaneously with the etching of the bit line. That is, first, the polysilicon is etched using the resist pattern of the bit line, and then the insulating film 19, the third conductive layer 18, and the polysilicon are sequentially processed. Thereafter, a storage node contact of the capacitor is formed again through the same process as that for processing the bit line.

The storage node electrode 21 is processed to such an extent that a predetermined capacitance is obtained, a plate electrode 23 and a capacitor insulating film 22 are formed, an interlayer insulating film 24 is formed, and the process proceeds to a bit line forming step. 5 (a) and 5 (b)
Is formed as shown in FIG. Where 2
5 is a wiring layer of the plate electrode.

Thus, a highly reliable semiconductor memory device can be easily obtained.

The gate wiring material and the insulating film material may be changed without departing from the gist of the present invention.

Although the capacitor is formed on the bit line in the above embodiment, the bit line may be formed after processing the capacitor.

In the above embodiment, when forming a bit line, a conductive layer made of tungsten or the like to be a bit line is formed on the conductive layer.
Since the insulating film 19 and the polycrystalline silicon 20 are deposited and the bit line is patterned, the polycrystalline silicon film 20 acts as a stopper when the storage node contact is formed, so that the bit line is protected and the reliability is improved. However, even if an interlayer film is formed by a normal method without forming the insulating film 19 and the polycrystalline silicon 20, a short circuit with the gate electrode is protected when forming the storage node contact, and a favorable A self-aligned pattern can be formed.

It is needless to say that the present invention can be applied to the manufacture of a semiconductor memory device using a trench cell without departing from the gist of the present invention.

Needless to say, the present invention can be applied to the manufacture of a semiconductor device having a multilayer wiring.

[0035]

As described above, according to the present invention, the self-aligned contact can be easily formed, and the semiconductor memory device can be easily miniaturized and the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 5 is a sectional view showing the manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 6 is a cross-sectional view when a contact for a bit line is opened in a manufacturing process of a conventional semiconductor memory device.

[Explanation of symbols]

 11, 31 Semiconductor substrate 12, 32 Gate wiring (first conductive layer) 13 Insulating film between gate and bit line (second insulating film) 14 Polycrystalline silicon film 15 Interlayer insulating film (third insulating film) 16 Resist 17, 35 SiN for insulation between gate contacts 18 Bit line 19 Bit line, interlayer insulation film between capacitors 20 Polycrystalline silicon film 21 Storage node electrode 22 Capacitor insulation film 23 Plate electrode 24 Plate, insulation film between aluminum wiring 25 Aluminum wiring 33 Gate Upper insulating film (SiO2) 34 Insulating film on gate (SiN) 36 SiN for preventing substrate oxidation 37 Stopper poly 38 Insulating film between gate and bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (1)

(57) [Claims] A first insulating film depositing step of depositing a first insulating film on a semiconductor substrate; a first conductive layer depositing step of depositing a first conductive layer on the first insulating film; A second insulating film depositing step of depositing a second insulating film on the upper layer; a stopper film depositing step of depositing a stopper film having a lower etching rate on the interlayer insulating film on the upper layer; A first etching step of sequentially patterning the second insulating film and the first conductive layer into the same pattern, and an interlayer insulating film forming step of forming an interlayer insulating film as a third insulating film over the entire surface of the semiconductor substrate thereon Forming a mask pattern having an opening larger than the inter-pattern distance of the first conductive layer, and using this as a mask,
A second etching step of etching an interlayer insulating film deposited in a contact region to be formed in a self-aligned manner with respect to the first conductive layer pattern; and, after removing the mask pattern, the stopper film forms the second insulating film. A third etching step of opening the contact hole by etching back the entire surface of the semiconductor substrate in the stopper film and the contact region while exposing the stopper film while masking the insulating film; and further depositing a fourth insulating film. Forming a sidewall insulating film at the same time as forming a sidewall insulating film and exposing the surface of the semiconductor substrate at the same time as forming a sidewall insulating film; and forming a second side so as to contact the semiconductor substrate surface exposed in the contact hole. A second conductive layer forming step of forming the first conductive layer.