JP3374837B2 - Manufacturing method of stacked capacitor type DRAM - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked capacitor type DRAM, and more particularly to a method of manufacturing a stacked capacitor type DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor.

[0002]

2. Description of the Related Art Generally, a stacked capacitor type DRAM is manufactured by a method of forming a stacked capacitor after forming a MOS transistor to be a switching transistor and then forming a bit line.
Therefore, the layers are arranged in the order of the word line, the storage node (lower electrode) of the stacked capacitor, the plate electrode (upper electrode of the stacked capacitor), and the bit line.

However, in recent years, a stacked capacitor type DRAM in which bit lines are formed before the stacked capacitors has been developed. FIGS. 8A and 8B show such a stacked capacitor type DRAM,
The same figure (A) is a plan view and the same figure (B) is BB of the same figure (A).
It is sectional drawing which follows the line.

In the figure, a is a p-type semiconductor substrate, b,
c and c are n ⁺ -type diffusion layers selectively formed on the surface of the semiconductor substrate a, which are sources of the switching transistor.
It forms the drain region. The diffusion layer b is a source / drain region connected to the bit line, and the diffusion layers c and c are source / drain regions connected to a storage node (lower electrode of the stacked capacitor).

D is a gate insulating film, e is a word line made of polycrystalline silicon, f is an interlayer insulating film, g is a bit line made of polycrystalline silicon, h is a bit contact hole, i is an interlayer insulating film, and j is a polycrystalline silicon film. Storage node made of crystalline silicon (lower electrode of stacked capacitor), k
Is a node contact hole, 1 is a dielectric film forming a dielectric of a stacked capacitor, and m is a plate electrode (upper electrode of the stacked capacitor), which is entirely formed on the memory cell array.

Such a stacked capacitor type DRA
M is referred to as a bit line shielded stacked capacitor type DRAM because it can electrostatically shield between bit lines by the storage node j and the plate electrode m, and is also abbreviated as DASH (IEEE TRA).
NSACTIONS ON ELECTRON DEV
ICES. VOL. 37. NO. 3. MARCH 19
90).

[0007]

The stacked capacitor type DRAM shown in FIG. 8 described above has the advantage that it can electrostatically shield bit lines between storage nodes and plate electrodes, and is therefore the mainstream of DRAMs. Have the potential to become. But 16Mbit, 6
It is difficult to meet the demand for increased storage capacity of 4 Mbits or even 128 Mbits. This is because the cell size must be reduced considerably to meet the demand, which is not possible with conventional technology.

Therefore, it can be said that it is preferable to form the bit contact portion and the node contact portion by making full use of the self-aligned contact technique. The self-aligned contact technique will be described. After forming the word lines e, e, ..., A dummy film having an appropriate thickness is formed on the word lines e, e ,. Sidewalls are formed, and the gaps between the sidewalls are used as contact holes to form a contact between the bit line g and the diffusion layer b, that is, a bit contact. After the bit lines g, g, ... Are formed, an insulating film j having an appropriate thickness is formed as an interlayer insulating film on the bit lines g, g ,. A side wall made of an insulating film is formed on the side surfaces of g, ... And then a storage node j is formed.

However, according to such a technique,
There is a problem that the workability is poor and the interlayer breakdown voltage failure is likely to occur. This is because the sidewalls on the side surfaces of the bit line i are formed with the interlayer insulating film f made of the same material as the base, and there is no one that serves as an etching stopper during anisotropic etching for forming the sidewall. This is because the interlayer insulating film f may be eroded by the anisotropic etching.

However, instead of this, a normal align contact technique, that is, a technique of forming a contact hole of a size that allows patterning at a certain distance from the underlying wiring, has poor workability and may cause breakdown voltage drop. Although the problem that there is such a problem can be solved, it is impossible to form a fine contact hole beyond the limit of the fine processing technology using a photoresist, and the self-size is significantly increased.

The present invention has been made to solve such a problem, and is a stacked capacitor type DR capable of reducing the size of a memory cell while securing an interlayer breakdown voltage.
It is an object of the present invention to provide a method for manufacturing AM.

[0012]

In order to solve the above-mentioned problems, a method of manufacturing a stacked capacitor type DRAM according to the present invention forms a bit contact and a dummy film on an interlayer insulating film (and thereafter, the dummy film is formed). An etching stopper and a polycrystalline silicon layer for detecting the end point may be formed on it),
An opening is formed in the dummy film (and the etching stopper and the polycrystalline silicon layer for detecting the end point) by etching using a photoresist film as a mask, a sidewall is formed on the inner peripheral surface of the opening, and the sidewall is masked. A contact is formed by a method of forming an opening having a smaller diameter than the opening by selective etching of the interlayer insulating film, removing the dummy film and the sidewall, and then forming a wiring film forming a bit line. After the wiring film forming the storage node is formed, the side wall is formed in the opening formed in the node contact forming portion of the wiring film to form the node contact hole having the smaller inner diameter, and then the lower electrode is formed. It is done by the method of doing.

According to the method of manufacturing the stacked capacitor type DRAM of the present invention, the bit contact is formed with a dummy film on the interlayer insulating film, and an opening is formed in the dummy film by etching using the photoresist film as a mask. A sidewall is formed on the inner peripheral surface of the opening, an opening having a smaller diameter than the opening is formed by selective etching of the interlayer insulating film using the sidewall as a mask, and the dummy film and the sidewall are removed. After that, since it is taken by the method of forming the wiring film forming the bit line, the bit contact hole whose inner diameter is made as small as necessary by forming the side wall having the width corresponding to the thickness of the dummy film on the inner side surface of the opening. Can be formed, and the limit of the microfabrication technology using a photoresist is exceeded by an arbitrary amount, resulting in a miniaturized bit. It is possible to form the contact hole.

After forming the dummy film, if the etching stopper and the polycrystalline silicon layer for detecting the end point are formed on the dummy film, the sidewall is formed on the inner side surface of the opening of the dummy film. At the time of anisotropic etching, the polycrystalline silicon layer can be used as an etching stopper and an end point detection, and the sidewall can be formed with high reliability.

As for the node contact, after forming the wiring film forming the storage node, a sidewall is formed in the opening formed in the node contact forming portion of the wiring film to form a node contact hole having a smaller inner diameter. After that, since the contact is made by forming the lower electrode, the inner diameter of the node contact is reduced as much as necessary by forming a sidewall having a width corresponding to the thickness of the wiring film forming the node contact on the inner side surface. Holes can be formed. Therefore,
It is possible to form a miniaturized node contact hole by exceeding the limit of the fine processing technique using a photoresist by an arbitrary amount.

[0016]

EXAMPLES Hereinafter, the stacked capacitor type DRA of the present invention
A method of manufacturing M will be described in detail with reference to the illustrated embodiment. 1 and 2 show an example of a stacked capacitor type DRAM manufactured by an embodiment of a method of manufacturing a stacked capacitor type DRAM of the present invention. FIG. 1 is a plan view and FIG. It is a sectional view taken along line -2.

In the drawings, 1 is a p-type semiconductor substrate, 2 is a field insulating film formed by selective oxidation of the surface of the semiconductor substrate 1, 3 is a gate insulating film, 4 is a word line (gate electrode) made of polycide, 5 is word line 4
Side wall made of SiO ₂ formed on the side surface of the
Reference numerals 6a and 6b denote diffusion layers forming source / drain regions.
a is a diffusion layer connected to a bit line, 6b is a diffusion layer connected to a storage node, 7 is an interlayer insulating film having a two-layer structure made of SiO ₂ and PSG, and 8 is formed on the interlayer insulating film 7. It is a bit contact hole and is formed by the technique of reducing the inner diameter by forming a sidewall in the opening, and is not formed by photoetching the interlayer insulating film 7.
The formation of the bit contact hole 8 will be clarified later in the description according to FIGS.

Reference numeral 9 is a polycide bit line,
It is composed of a polycrystalline silicon film 9a and a silicide film 9b. The bit line 9, especially the polycrystalline silicon film 9a thereof, is connected to the diffusion layer 6a through the bit contact hole 8. An interlayer insulating film 10 is composed of SiO ₂ and PSG. Reference numeral 11 denotes a node contact hole formed in the interlayer insulating film 10 and the interlayer insulating film 7, which is also formed by a technique of forming a sidewall in the opening to reduce the inner diameter.

[0019] 12 is a storage node of polycrystalline silicon, 13 in the side wall formed on the side surface of the storage node 12, sidewalls contribute to the formation of the small-diameter node contact hole 11 is this, SiO ₂ And PSG. Reference numeral 14 is a polycrystalline silicon layer that connects the storage node 12 and the diffusion layer 6b, and the diffusion layer 6 is formed through the node contact hole 11.
connected to b. Reference numeral 15 is a dielectric film, and 16 is a plate electrode entirely formed on the memory cell array.

Such a stacked capacitor type DRA
According to M, the bit contact hole 8 and the node contact 11 are both formed by a technique of forming a contact hole having a small inner diameter by forming a sidewall in the opening, and a fine processing technique using a photoresist. It is possible to form a fine contact hole beyond the limit of. Therefore, the interval between word lines can be made smaller and the memory cell size can be made smaller.

FIGS. 3A to 3E, 4F to 4J, 5K to 5N, and 6O to 6R are shown in FIGS. 1 and 2. 5A to 5C are cross-sectional views sequentially showing steps (A) to (R) of the method of manufacturing the stacked capacitor type DRAM shown in FIG. (A) A switching transistor is formed by a method similar to the conventional method for manufacturing a stacked capacitor type DRAM. FIG. 3A shows the diffusion layer 6 of the switching transistor.
The state after formation of a and 6b is shown.

(B) Next, an interlayer insulating film 7 is formed on the surface, a polycrystalline silicon film 17 for detecting an etching stop and an etching end point is further formed on the interlayer insulating film 7, and the polycrystalline silicon film 17 is formed. Then, a dummy SiO ₂ film 18 is formed. FIG. 3B shows a state after the dummy SiO ₂ film 18 is formed. (C) Next, by using the photoresist film 19 as a mask, an opening 20 is formed in the dummy SiO ₂ film 18 at a position where a bit contact is to be made, as shown in FIG. d is the diameter of this opening 20.

(D) Next, as shown in FIG. 3D, a sidewall 21 made of SiO ₂ is formed on the inner peripheral surface of the opening 20. This sidewall 21 is made of, for example, Si
It consists of O ₂ and silicon nitride. (E) Next, as shown in FIG. 6E, the polycrystalline silicon film 1 for detecting the etching stop and the etching end point is formed.
7 is the dummy SiO ₂ film 18 and the sidewall 2
Etching is performed using 1 as a mask.

(F) Next, as shown in FIG.
The dummy SiO ₂ film 18 and the sidewall 21 are removed by etching back iO ₂ , and the bit contact hole 8 is formed. The diameter of the bit contact hole 8 is considerably smaller than the diameter d of the opening 20. (G) Next, a polycrystalline silicon film 9a is formed as shown in FIG. The polycrystalline silicon film 9a contacts the diffusion layer 6a at the bit contact hole 8, and
The polycrystalline silicon film 17 for forming the bit line 9 made of polycide is integrated with the polycrystalline silicon film 17 for detecting the etching stop and the etching end point.

(H) Next, as shown in FIG. 3H, a silicide film 9b forming the bit line 9 is formed. (I) Next, as shown in FIG. 2I, the polycrystalline silicon film 9a and the silicide film 9 are formed using the resist film 22 as a mask.
bit line 9 by selectively etching b
To form. (J) Next, as shown in FIG. (J), SiO ₂ and P
The interlayer insulating film 10 made of SG is formed.

(K) Next, as shown in FIG. 5K, a polycrystalline silicon film 12 to be a storage node is formed. (L) Next, as shown in FIG. 6L, the portion of the polycrystalline silicon film 12 where the node contact is to be formed is removed by selective etching using the resist film 23 as a mask.
Reference numeral 24 is an opening formed in the portion of the polycrystalline silicon film 12 where a node contact should be made by this etching.

(M) Next, as shown in FIG. 3M, a sidewall 13 made of SiO ₂ and silicon nitride is formed on the inner surface of the opening 24 of the polycrystalline silicon film 12. (N) Next, as shown in FIG. 9N, the inter-layer insulating films 7 and 10 are etched using the polycrystalline silicon film 12 and the sidewalls 13 as masks to form node contact holes 11.

(O) Next, as shown in FIG. 6 (O), a polycrystalline silicon film 14 is formed. The polycrystalline silicon film 1
Reference numeral 4 denotes a node contact hole 11, which is in contact with the diffusion layer 6b and is also in contact with the storage node 12. That is, the polycrystalline silicon film 14 serves to electrically connect the diffusion layer 6b and the storage node 12. (P) Next, as shown in FIG. 7 (P), the storage nodes 12 are formed by patterning the polycrystalline silicon films 14 and 12 by etching using the resist film 25 as a mask.

(Q) Next, a dielectric film 15 is formed as shown in FIG. (R) After that, as shown in FIG. 8R, the plate electrode 16 made of polycrystalline silicon is formed over the entire surface.

In the manufacturing method shown in FIGS. 3 to 6, a thin polycrystalline silicon film may be formed after the step (B) shown in FIG. 3B is completed. FIG. 7 shows a state in which the resist film 25 is formed after forming the polycrystalline silicon film 26. This polycrystalline silicon film 26 can be used as an etching stopper and an end point detecting means in anisotropic etching for forming the sidewall 21.

[0031]

The stacked capacitor type DRAM of the present invention
Is a method of manufacturing a stacked capacitor type DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor,
A bit contact, which is a contact between the bit line and the diffusion layer on the surface of the semiconductor substrate, is formed as a dummy film on the interlayer insulating film, and an opening is masked with a photoresist film at a position where the bit contact of the dummy film should be made. To form a side wall on the inner peripheral surface of the opening, and the side wall is used as a mask to etch the interlayer insulating film to form an opening having a smaller diameter than the opening. The film and the side wall are removed, and thereafter, a wiring layer which forms a bit line and is connected to the diffusion layer through the opening having the small diameter is formed, and the lower electrode of the stacked capacitor and the surface of the semiconductor substrate are formed. After forming a wiring film forming a storage node, a node contact which is a contact with another diffusion layer of A side wall is formed in the opening formed in the node contact forming portion of the wire film to form a node contact hole having a smaller inner diameter, and then a lower electrode connected to the other diffusion layer through the node contact hole is formed. The method is characterized in that a wiring film is formed, and after the dummy film is formed, an etching stopper and an end point detecting polycrystalline silicon layer may be formed on the dummy film.

Therefore, the stacked capacitor type D of the present invention
According to the method of manufacturing a RAM, a bit contact is formed as a dummy film on an interlayer insulating film, and an opening is formed in the dummy film by etching using a photoresist film as a mask.
A sidewall is formed on the inner peripheral surface of the opening, an opening having a smaller diameter than the opening is formed by selective etching of the interlayer insulating film using the sidewall as a mask, and the dummy film and the sidewall are removed. After that, since it is taken by the method of forming the wiring film forming the bit line, the bit contact hole whose inner diameter is made as small as necessary by forming the side wall having the width corresponding to the thickness of the dummy film on the inner side surface of the opening. It is possible to form a bit contact hole which is miniaturized by an arbitrary amount exceeding the limit of the microfabrication technique using a photoresist.

After the dummy film is formed, if the etching stopper and the end-point detecting polycrystalline silicon layer are formed on the dummy film, the sidewall is formed on the inner side surface of the opening of the dummy film. At the time of anisotropic etching, the polycrystalline silicon layer can be used as an etching stopper and an end point detection, and the sidewall can be formed with high reliability.

As for the node contact, after forming the wiring film forming the storage node, the side wall is formed in the opening formed in the node contact forming portion of the wiring film to form the node contact hole having the smaller inner diameter. After that, since the contact is made by forming the lower electrode, the inner diameter of the node is reduced as much as necessary by forming a sidewall having a width corresponding to the thickness of the wiring film forming the node contact on the inner peripheral surface. A contact hole can be formed. Therefore,
It is possible to form a miniaturized node contact hole by exceeding the limit of the fine processing technique using a photoresist by an arbitrary amount.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a stacked capacitor type DRAM manufactured by an embodiment of a method of manufacturing a stacked capacitor type DRAM of the present invention.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

3A-3E are steps (A)-of one embodiment of a method of manufacturing a stacked capacitor type DRAM of the present invention.
It is sectional drawing which shows (E).

4 (F) to (J) are steps (F) to (J) in the above embodiment.
It is sectional drawing which shows (J).

5 (K) to (N) are steps (K) to
It is sectional drawing which shows (N).

6 (O)-(R) are the steps (O)-
It is sectional drawing which shows (R).

FIG. 7 is a cross-sectional view for explaining another embodiment different from the above embodiment.

8A and 8B show a conventional stacked capacitor type DPAM, in which FIG. 8A is a plan view and FIG. 8B is a sectional view taken along line BB in FIG. 8A.

[Explanation of symbols]

1 ... Semiconductor substrate, 4 ... Word line, 6a,
6b ... diffusion layer, 8 ... bit contact hole,
9 (9a, 9b) ... Bit line, 11 ... Node contact hole, 12 ... Storage node (lower electrode of stacked capacitor), 20 ... Opening, 2
4 ... Opening, 26 ... Etching stopper and polycrystalline silicon layer for end point detection.

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Claims (2)

(57) [Claims] 1. A method of manufacturing a stacked capacitor type DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor, wherein a contact between the bit line and a diffusion layer on a surface of a semiconductor substrate is provided. A dummy film is formed on the interlayer insulating film, and an opening is formed in the dummy film at a position where the bit contact is to be formed by etching using a photoresist film as a mask, and an inner peripheral surface of the opening is formed. A side wall is formed, and the interlayer insulating film is etched using the side wall as a mask to form an opening having a diameter smaller than that of the opening. Thereafter, the dummy film and the side wall are removed, and then the bit line is formed. And forming a wiring layer connected to the diffusion layer through the small diameter opening. A contact formed between the lower electrode of the stacked capacitor and another diffusion layer on the surface of the semiconductor substrate is formed in the node contact forming portion of the wiring film after forming the wiring film forming the storage node. A side wall is formed inside to form a node contact hole having a smaller inner diameter, and then a wiring film forming a lower electrode connected to the other diffusion layer through the node contact hole is formed. A method of manufacturing a stacked capacitor type DRAM, comprising: 2. A method of manufacturing a stacked capacitor type DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor, wherein the contact between the bit line and a diffusion layer on a surface portion of a semiconductor substrate. A dummy film is formed on the interlayer insulating film, an etching stopper and an end point detecting polycrystalline silicon layer are formed on the dummy film, and the dummy film, the etching stopper and the end point detecting polycrystal are formed. An opening is formed in the silicon layer at a position where a bit contact should be made by etching using a photoresist film as a mask, a sidewall is formed on the inner peripheral surface of the opening, and the interlayer insulating film is etched using the sidewall as a mask. To form an opening having a diameter smaller than that of the above, and then the dummy film and The sidewall is removed, and thereafter, a wiring layer is formed which forms a bit line and is connected to the diffusion layer through the opening having a small diameter. The wiring layer is connected to the lower electrode of the stacked capacitor and the surface portion of the semiconductor substrate. A node contact, which is a contact with another diffusion layer, has a smaller inner diameter by forming a side wall in an opening formed in a node contact forming portion of the wiring film after forming a wiring film forming a storage node. A method of manufacturing a stacked capacitor type DRAM, comprising: forming a hole, and then forming a wiring film forming a lower electrode connected to the other diffusion layer through the node contact hole.