JP3165693B2 - Stacked capacitor type DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial application fields B. Summary of the invention C. Prior art [Fig. 5] D. Problems to be solved by the invention E. Means to solve the problems F. Function G. Example [No. FIGS. 1 to 4] H. Effects of the Invention (A. Industrial Application Field) The present invention relates to a stacked capacitor type DRAM, in particular, in which a bit line is above a word line and below a lower electrode of the stacked capacitor. The present invention also relates to a method of manufacturing a stacked capacitor type DRAM in which a bit line is electrostatically shielded by the lower electrode and the upper electrode.

(B. Summary of the Invention) The present invention relates to a method for manufacturing a stacked capacitor DRAM as described above, wherein a bit contact is formed and a dummy film is formed on an interlayer insulating film in order to reduce the size of a memory cell while ensuring an interlayer withstand voltage. An opening is formed in the dummy film by etching using a photoresist film as a mask, a sidewall is formed on an inner peripheral surface of the opening, and the interlayer insulating film is selectively etched using the sidewall as a mask. A method of forming an opening smaller in diameter than the opening, removing the dummy film and the side wall, and thereafter forming a wiring film forming a bit line, and forming a node contact after forming the wiring film forming a storage node. A node contour whose inner diameter is reduced by forming a sidewall in an opening formed in a node contact forming portion of the wiring film. Forming a Tohoru, then, are those taken by the method of forming a lower electrode.

(C. Prior Art) [FIG. 5] A stacked capacitor type DRAM is generally manufactured by forming a MOS transistor serving as a switching transistor, forming a stacked capacitor, and then forming a bit line. . Therefore, the layers are arranged in the order of the word line, the storage node (lower electrode) of the stacked capacitor, the plate electrode (upper electrode of the stacked capacitor), and the bit line.

However, in recent years, a stacked capacitor type DRAM in which a bit line is formed before a stacked capacitor has been developed. FIGS. 5A and 5B show such a stacked capacitor type DRAM, wherein FIG. 5A is a plan view and FIG. 5B is a BB line of FIG. 5A. FIG.

In the figure, a is a p-type semiconductor substrate, and b, c, and c are n ⁺ -type diffusion layers selectively formed on the surface of the semiconductor substrate a, and form source / drain regions of a switching transistor. The diffusion layer b is a source connected to the bit line.
The drain region and the diffusion layers c are source / drain regions connected to the storage node (the lower electrode of the stacked capacitor).

d is a gate insulating film, e is a word line made of polycrystalline silicon, f is an interlayer insulating film, g is a bit line made of polycrystalline silicon, h is a bit contact hole, i is an interlayer insulating film, and j is a polycrystalline silicon. Storage node (lower electrode of the stacked capacitor), k is a node contact hole, l is a dielectric film forming a dielectric of the stacked capacitor, m is a plate electrode (upper electrode of the stacked capacitor), and is located on the memory cell array. It is formed entirely.

Such a stacked capacitor DRAM can be electrostatically shielded between bit lines by a storage node j and a plate electrode m, and is therefore called a bit line shielded stacked capacitor DRAM, and further abbreviated as DASH. (IEEE TRANSACTIONS ON ELECTRON DEVICES.VO
L.37.NO.3.MARCH 1990).

(D. Problems to be solved by the invention) The stacked capacitor type DRAM shown in FIG. 5 described above.
Has the advantage that the bit lines can be electrostatically shielded by the storage node and the plate electrode, and thus has a possibility of becoming the mainstream of DRAM. However, it is difficult to meet the demand for a storage capacity increase of 16 Mbits, 64 Mbits, and even 126 Mbits. This is because the cell size has to be reduced considerably to meet that demand, which is not possible with conventional technology.

Therefore, it can be said that it is preferable to form the bit contact portion and the node contact portion using the self-aligned contact technology. The self-aligned contact technology will be described. After forming word lines e, e,..., A dummy film having an appropriate thickness is formed on the word lines e, e,. A side wall is formed, and a contact between the bit line g and the diffusion layer b, that is, a bit contact is formed using a gap generated between the side walls as a contact. After forming the bit lines g, g,..., An insulating film j having an appropriate thickness is formed as an interlayer insulating film on the bit lines g, g,. are formed on the side surfaces of g,..., and then the storage node j is formed.

However, according to such a technique, there is a problem that workability is poor and an interlayer withstand voltage failure is likely to occur. That is, the side wall on the side surface of the bit line i is formed with the interlayer insulating film f made of the same material as the base,
This is because there is no material serving as an etching stopper in the anisotropic etching for forming the sidewall, and the anisotropic etching may corrode the interlayer insulating film f.

However, according to the conventional align contact technique, that is, the technique of forming a contact hole having a size that can be patterned at a fixed distance from the underlying wiring, the processing control is poor and the withstand voltage may be reduced. Although the above problem can be solved, the fine contact hole cannot be formed beyond the limit of the fine processing technology using the photoresist, and the self-size is greatly increased.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a method of manufacturing a stacked capacitor type DRAM capable of reducing the size of a memory cell while ensuring an interlayer breakdown voltage. I do.

(E. Means for Solving the Problems) According to the method of manufacturing a stacked capacitor type DRAM of the present invention, the bit line is formed above the word line and below the lower electrode of the stacked capacitor, and at least the lower electrode In a method for manufacturing a stacked capacitor DRAM in which a bit line is electrostatically shielded, a contact between the bit line and a diffusion layer forming a part of the switching transistor on a surface of a semiconductor substrate on which the switching transistor is formed is provided. A certain bit contact is formed by forming a dummy film from an insulating film on the interlayer insulating film covering the switching transistor, and forming an opening at a position where the bit contact of the dummy film is to be made by etching using a photoresist film as a mask, Forming a sidewall made of an insulating film on the inner peripheral surface of the opening; Removing the sidewalls and the dummy film by etching back the insulating film, and removing a portion of the interlayer insulating film surrounded by the sidewalls to form an opening smaller in diameter than the opening, Forming a wiring layer connected to the diffusion layer through the small-diameter opening, forming the bit line, and forming the lower electrode of the stacked capacitor and the switching transistor on the surface of the semiconductor substrate. A node contact, which is a contact with a diffusion layer forming another part,
Forming an interlayer insulating film covering the interlayer insulating film and the bit line, forming a wiring film serving as a storage node on the interlayer insulating film, forming an opening at a position where a node contact of the wiring film is to be made; By forming a sidewall on the inner peripheral surface of the opening, and etching the interlayer insulating film covering the bit line and the interlayer insulating film covering the switching transistor using the sidewall as a mask, the diffusion forming the another portion of the switching transistor is diffused. Forming a node contact hole consisting of an opening exposing the layer, and then forming a wiring film forming a lower electrode connected to the diffusion layer forming the another portion through the node contact hole. And

(F. Function) According to the method of manufacturing a stacked capacitor DRAM of the present invention, an opening is formed in a bit contact by forming a dummy film on an interlayer insulating film and etching the dummy film using a photoresist film as a mask. Then, a sidewall is formed on the inner peripheral surface of the opening, an opening smaller in diameter than the opening is formed by selective etching of the interlayer insulating film using the sidewall as a mask, and the dummy film and the sidewall are formed. It is removed by a method of forming a wiring film forming a bit line, and then a bit having an inner diameter as small as necessary by forming a sidewall having a width corresponding to the thickness of the dummy film on the inner side surface of the opening. Since the contact hole is formed, the bit contact size has been reduced beyond the limit of the fine processing technology using photoresist by an arbitrary amount. A tohole can be formed.

Also, as for the node contact, after the formation of the wiring film forming the storage node, a side wall is formed in the opening formed in the node contact forming portion of the wiring film to form a node contact hole having a reduced inner diameter, and thereafter, Since the contact is made by forming the lower electrode, a node contact hole having an inner diameter as small as necessary is formed by forming a sidewall having a width corresponding to the thickness of the wiring film forming the node contact on the inner surface. Can be formed. Therefore, it is possible to form a miniaturized node contact hole by exceeding the limit of the fine processing technology using a photoresist by an arbitrary amount.

(G. Embodiment) [FIGS. 1 to 4] Hereinafter, a stacked capacitor type DRAM of the present invention will be described in detail with reference to illustrated embodiments. 1 and 2 show an example of a stacked capacitor DRAM manufactured by one embodiment of the method of manufacturing a stacked capacitor DRAM of the present invention. FIG. 1 is a plan view, and FIG. 2-2 in FIG.
It is sectional drawing which follows a line.

In the drawings, 1 is a p-type semiconductor substrate, 2 is a field insulating film formed by selective oxidation of the surface of the semiconductor substrate 1, 3 is a gate insulating film, 4 is a word line (gate electrode) made of polycide, and 5 is a word. Side walls made of SiO ₂ formed on the side surfaces of the line 4, 6a and 6b are diffusion layers forming source / drain regions, 6a is a diffusion layer connected to a bit line, and 6b is a diffusion layer connected to a storage node. Reference numeral 7 denotes an interlayer insulating film having a two-layer structure composed of SiO ₂ and PSG, and reference numeral 8 denotes a bit contact hole formed in the interlayer insulating film 7, which has a smaller inner diameter by forming a sidewall in the opening. It is formed by technology, and is not formed by photoetching the interlayer insulating film 7. The formation of the bit contact hole 8 will be clarified later in the description with reference to FIG.

Reference numeral 9 denotes a bit line made of polycide, which comprises a polycrystalline silicon film 9a and a silicide film 9b. The bit line 9, especially the polycrystalline silicon film 9a, is connected to the diffusion layer 6a through the bit contact hole 8. Reference numeral 10 denotes an interlayer insulating film 7, which is made of SiO ₂ and PSG. 11 is interlayer insulating film 1
0 and a node contact hole formed in the interlayer insulating film 7, which is also formed by a technique of reducing the inner diameter by forming a sidewall in the opening.

12 storage nodes of polycrystalline silicon, 13 in the side wall formed on the side surface of the storage node 12, sidewalls contribute to the formation of the small-diameter node contact hole 11 is this, of SiO ₂ and PSG Become. Reference numeral 14 denotes a polycrystalline silicon layer connecting between the storage node 12 and the diffusion layer 6b, and a node contact hole 11
Through to the diffusion layer 6b.

Reference numeral 15 denotes a dielectric film, and reference numeral 16 denotes a plate electrode formed entirely on the memory cell array.

According to such a stacked capacitor type DRAM, the bit contact hole 8 and the node contact 11 are both formed by a technique of forming a contact hole with a reduced inner diameter by forming a sidewall in an opening, and a photoresist is used. It is possible to form a fine contact hole beyond the limit of the fine processing technology using GaN. Therefore, the interval between word lines can be made smaller, and the memory cell size can be made smaller.

FIGS. 3 (A) to 3 (R) show a method of manufacturing the stacked capacitor type DRAM shown in FIGS. 1 and 2, and more specifically, one embodiment of the method of manufacturing the stacked capacitor type DRAM of the present invention. It is sectional drawing shown in order.

(A) A switching transistor is formed by a method similar to a conventional method of manufacturing a stacked capacitor type DRAM. FIG. 3A shows the diffusion layers 6a and 6b of the switching transistor.
2 shows the state after formation.

(B) Next, an interlayer insulating film 7 is formed on the surface, and a polysilicon film 17 for etching stop and etching end point detection is formed on the interlayer insulating film 7.
A dummy SiO ₂ film 18 is formed on 17. FIG. 3B shows a state after the formation of the dummy SiO ₂ film 18.

(C) Next, an opening 20 is formed by etching using the photoresist film 19 as a mask at a position where a bit contact is to be made in the dummy SiO ₂ film 18 as shown in FIG. d
Is the diameter of the opening 20.

(D) Next, as shown in FIG. 3D, a sidewall 21 made of SiO ₂ is formed on the inner peripheral surface of the opening 20. The sidewall 21 is made of, for example, SiO ₂ and silicon nitride.

(E) Next, as shown in FIG. 3E, the etching stop and the etching end point detecting polycrystalline silicon film 17 are formed.
Is etched using the dummy SiO ₂ film 18 and the side walls 21 as a mask.

(F) Next, as shown by (F), the dummy SiO ₂ film 18 and the side wall by etching back the SiO ₂
21 is removed and the bit contact hole 8 is formed. The diameter of the bit contact hole 8 is considerably smaller than the diameter d of the opening 20.

(G) Next, as shown in FIG.
Form 9a. The polycrystalline silicon film 9a is in contact with the diffusion layer 6a at the bit contact hole 8, and is integrated with the polycrystalline silicon film 17 for etching stop and etching end point detection to form the polycrystalline bit line 9 composed of polycide. It becomes a silicon film.

(H) Next, a silicide film 9b constituting the bit line 9 is formed as shown in FIG.

(I) Next, as shown in FIG. 1I, the bit line 9 is formed by selectively etching the polycrystalline silicon film 9a and the silicide film 9b using the resist film 22 as a mask.

(J) Next, as shown in FIG. 1J, an interlayer insulating film 10 made of SiO ₂ and PSG is formed.

(K) Next, as shown in FIG. 1K, a polycrystalline silicon film 12 serving as a storage node is formed.

(L) Next, as shown in FIG. 2L, a portion of the polycrystalline silicon film 12 where a node contact is to be made is formed by a resist film 23.
Is removed by selective etching using as a mask. Reference numeral 24 denotes an opening formed in a portion of the polycrystalline silicon film 12 where a node contact is to be made by this etching.

(M) Next, as shown in FIG. 1M, a sidewall 13 made of SiO ₂ and silicon nitride is formed on the inner side surface of the opening 24 of the polycrystalline silicon film 12.

(N) Next, as shown in FIG. 3N, the interlayer insulating film 7 is formed using the polycrystalline silicon film 12 and the side walls 13 as a mask.
And 10 are etched to form a node contact hole 11.

(O) Next, a polycrystalline silicon film 14 is formed as shown in FIG. The polycrystalline silicon film 14 contacts the diffusion layer 6b at the node contact hole 11, and also contacts the storage node 12. That is, the polycrystalline silicon film 14 serves to electrically connect the diffusion layer 6b and the storage node 12.

(P) Next, as shown in FIG. 3 (P), the polycrystalline silicon films 14 and 12 are patterned by etching using the resist film 25 as a mask, thereby forming the storage node 12.
To form

(Q) Next, a dielectric film 15 is formed as shown in FIG.

(R) Thereafter, as shown in FIG. 3 (R), a plate electrode 16 made of polycrystalline silicon is formed over the entire surface.

In the manufacturing method shown in FIG. 3, a thin polycrystalline silicon film may be formed after step (B). FIG. 4 shows a resist film after the polycrystalline silicon film 26 is formed.
25 shows a state where 25 is formed. This polycrystalline silicon film
Reference numeral 26 can be used as an etching stopper and an end detecting means at the time of anisotropic etching for forming the sidewall 21.

(H. Effects of the Invention) As described above, the stacked capacitor type of the present invention
A method of manufacturing a DRAM includes a method of manufacturing a stacked capacitor DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor, and the bit line is electrostatically shielded by at least the lower electrode. A bit contact, which is a contact between the bit line and a diffusion layer forming a part of the switching transistor on the surface of the semiconductor substrate on which the switching transistor is formed, is formed from an insulating film on an interlayer insulating film covering the switching transistor. Then, a dummy film is formed, an opening is formed at a position where a bit contact of the dummy film is to be made by etching using a photoresist film as a mask, a sidewall made of an insulating film is formed on the inner peripheral surface of the opening, By etching back the film, the side wall and the The Mie film is removed, and the portion of the interlayer insulating film surrounded by the sidewalls is removed to form an opening having a smaller diameter than the opening. Thereafter, the bit line is formed and the opening having a smaller diameter is formed. Forming a wiring layer connected to the diffusion layer through the lower electrode of the stacked capacitor and a diffusion layer forming a part different from the part of the switching transistor on the surface of the semiconductor substrate. A node contact which is a contact should be formed by forming an interlayer insulating film covering the interlayer insulating film and the bit line, forming a wiring film serving as a storage node on the interlayer insulating film, and taking a node contact of the wiring film. An opening is formed at the position, a sidewall is formed on the inner peripheral surface of the opening, and an interlayer insulation covering the bit line is formed using the sidewall as a mask. By etching the edge film and the interlayer insulating film covering the switching transistor, a node contact hole including an opening exposing the diffusion layer forming the another portion of the switching transistor is formed, and then the node contact hole is formed through the node contact hole. And forming a wiring film forming a lower electrode connected to the diffusion layer forming the portion.

Therefore, according to the method of manufacturing a stacked capacitor DRAM of the present invention, a bit contact is formed by forming a dummy film on an interlayer insulating film, and forming an opening in the dummy film by etching using a photoresist film as a mask. Forming a sidewall on the inner peripheral surface of the opening, forming an opening smaller in diameter than the opening by selective etching of the interlayer insulating film using the sidewall as a mask, removing the dummy film and the sidewall, After that, since a wiring film forming a bit line is formed, a side wall having a width corresponding to the thickness of the dummy film is formed on the inner surface of the opening to form a bit contact hole having an inner diameter as small as necessary. Can be formed. Therefore, it is possible to form a fine contact hole beyond the limit of the fine processing technology using a photoresist by an arbitrary amount.

Also, as for the node contact, after the formation of the wiring film forming the storage node, a side wall is formed in the opening formed in the node contact forming portion of the wiring film to form a node contact hole having a reduced inner diameter, and thereafter, Since the contact is made by forming the lower electrode, a node contact hole having an inner diameter as small as necessary is formed by forming a sidewall having a width corresponding to the thickness of the wiring film forming the node contact on the inner surface. Can be formed.

Therefore, it is possible to form a miniaturized node contact hole beyond the limit of the fine processing technology using a photoresist by an arbitrary amount.

[Brief description of the drawings]

1 to 3 show a stacked capacitor type DRAM according to the present invention.
To explain an example of a stacked capacitor type DRAM manufactured by one embodiment of the manufacturing method of the first embodiment.
FIG. 2 is a plan view, FIG. 2 is a sectional view taken along line 2-2 of FIG.
FIGS. 3A to 3R are cross-sectional views showing a method of manufacturing the stacked capacitor DRAM shown in FIGS. 1 and 2, that is, one embodiment of the method of manufacturing the stacked capacitor DRAM of the present invention in the order of steps. FIG. 4 is a sectional view showing another manufacturing method.
5 (A) and 5 (B) show a conventional example, wherein FIG. 5 (A) is a plan view and FIG. 5 (B) is a sectional view taken along line BB of FIG. 5 (A). DESCRIPTION OF SYMBOLS 1 ... semiconductor substrate, 4 ... word line, 6a, 6b ... diffusion layer, 8 ... bit contact hole, 9 (9a, 9b) ... bit line, 11 ... node contact hole, 12 ... ... storage node (lower electrode of stacked capacitor), 20 ... opening, 24 ... opening.

Claims (1)

(57) [Claims] 1. A method of manufacturing a stacked capacitor DRAM in which a bit line is formed above a word line and below a lower electrode of a stacked capacitor, and the bit line is electrostatically shielded by at least the lower electrode. A bit contact, which is a contact between the bit line and a diffusion layer forming a part of the switching transistor on the surface of the semiconductor substrate on which the switching transistor is formed, comprising an insulating film on an interlayer insulating film covering the switching transistor; Forming a dummy film, forming an opening at a position where a bit contact of the dummy film is to be made by etching using a photoresist film as a mask, forming a sidewall made of an insulating film on the inner peripheral surface of the opening, The sidewalls and the above-mentioned dummy Along with removing the film, a portion of the interlayer insulating film surrounded by the sidewalls is removed to form an opening having a smaller diameter than the opening, and thereafter, forming the bit line and passing through the opening having a smaller diameter. Forming a wiring layer connected to the diffusion layer, the lower electrode of the stacked capacitor and a diffusion layer forming a part different from the part of the switching transistor on the surface of the semiconductor substrate. A node contact which is a contact is formed by forming an interlayer insulating film covering the interlayer insulating film and the bit line, forming a wiring film serving as a storage node on the interlayer insulating film, and forming a node contact of the wiring film. An opening is formed in the opening, a sidewall is formed on the inner peripheral surface of the opening, and an interlayer insulation covering the bit line is formed using the sidewall as a mask. By etching a film and an interlayer insulating film covering the switching transistor, a node contact hole consisting of an opening exposing a diffusion layer forming the another portion of the switching transistor is formed, and then the another node contact hole is formed through the node contact hole. Forming a wiring film forming a lower electrode connected to a diffusion layer forming a portion of the stacked capacitor type DRAM.