JP3120633B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a grooved capacity type memory cell of a dynamic random access memory (DRAM) suitable for high integration and a method of manufacturing the same.

[0002]

2. Description of the Related Art MOS dynamic memories are available in 1970.
Starting with the launch of the 1-kbit DRAM annually, high integration has been made four times in three years, and megabit-class memories have already been mass-produced.

This high integration has been achieved by miniaturizing the device dimensions. However, due to the phenomenon of storage capacitance accompanying the miniaturization, the signal-to-noise (SN) ratio decreases and α
The inversion of a signal due to the incidence of a line, the so-called harmful effect of a so-called soft error, etc., has become evident, and is a problem in terms of reliability.

[0004] As a memory cell that solves these problems, IEDM Technical Digest 1984 (IEDM Technical Digest) has been proposed.
St. 1984) There is a groove stacked capacitance type memory cell published on pages 240 to 243. This is because the storage capacity
It has a structure embedded in a groove formed around the switching transistor via an insulating film. It is expected that a large storage capacity is secured by using the trench capacity, and that the storage capacity is covered with an insulating film in the trench to provide soft error resistance.

[0005] FIG.
0 is shown. FIG. 20A is a plan layout view of the cell, and FIG. 20B is a cross-sectional view taken along line AA of FIG.

A conventional memory cell will be described with reference to FIG. A drain region 2 and a source region 3 made of an n-type impurity are formed on a surface portion of a p-type silicon substrate 1, and a word line 4 made of polycrystalline silicon and provided via a gate oxide film 8 is used as a gate electrode. Is formed. Drain region 2
Is connected to a bit line 13 through a bit line contact 12. On the other hand, in the capacitor portion, a groove 5 is dug in the p-type silicon substrate 1 and an insulating film 6 is formed on the inner surface thereof.
The storage electrode 7 made of polycrystalline silicon is formed thereon. Further, a capacitor insulating film 9 and a cell plate 10 are successively formed thereon. As shown in FIG. 20A, since the storage electrode 7 surrounds the switching transistor via the insulating film 6 via the insulating film 6, an effective area acting as a capacitor can be increased, and a large storage area can be obtained with a small cell occupation area. Capacity can be secured. In addition, the presence of the insulating film 6 can reduce the influence of a soft error due to α-ray incidence.

[0007]

However, in the conventional example shown in FIG. 20, the storage electrode 7 exists on the side surface of the switching transistor via the insulating film 6 as described above. Therefore, as shown in FIG. 21, a MOS transistor T2 having the insulating film 6 as a gate oxide film and the storage electrode 7 as a gate electrode is necessarily formed on the side surface of the channel. When a high-side voltage is written as information to the storage electrode 7 (information “H”), the side wall parasitic MOS transistor T
2 turns ON, and a leakage current occurs. The written information is lost due to this leakage current, which is a serious problem for maintaining high stability and high reliability of the memory operation.

An object of the present invention is to solve the above-mentioned problems and to provide a groove stacked capacitance type memory cell suitable for an ultra-highly integrated DRAM and a method of manufacturing the same.

[0009]

According to the present invention, there is provided a semiconductor memory device comprising a gate electrode provided on a surface of an island region defined by a groove formed in a semiconductor substrate of a first conductivity type via a gate insulating film; A switching transistor having a pair of second conductivity type diffusion layers respectively formed on a surface portion of the island region, an insulating film covering side surfaces and a bottom surface of the groove, and a side surface of the groove on the side of the island region Having a lower electrode connected to one of the second conductivity type diffusion layers and covering the lower electrode, a capacitor insulating film covering the lower electrode, and a capacitor comprising an upper electrode covering the capacitor insulating film. In a semiconductor memory device having a cell, the lower electrode is connected to the switching transistor.
Below the gate electrode of the
A portion of the transistor interposed between the pair of second conductivity type diffusion layers
A lower electrode removing portion in which a portion facing the minute is removed,
The lower electrode is located in a region other than the lower electrode removing portion.
It covers the side surface of the groove .

Further, according to the method of manufacturing a semiconductor memory device of the present invention, there is provided a step of forming a groove from one main surface to the inside of the first conductivity type semiconductor substrate to partition an island region, and forming a side surface and a bottom surface of the groove. A step of forming an insulating film to cover, a step of locally removing a portion of the insulating film near the surface of the island-shaped region to form a connection portion, and depositing a conductive film on the entire surface to form a connection portion. Forming a second conductivity type connection region by diffusing an impurity into the semiconductor substrate region in the vicinity thereof; and at least locally arranging a portion of the island region close to the surface of the semiconductor substrate when patterning the conductive film. To 2
Remove the lower electrode and switch the switching transistor
Below the region where the gate electrode is to be formed,
Region for forming a pair of second conductive type diffusion layers of the transistor
Remove the lower electrode where the part opposite the part sandwiched by
Having a left part, and in an area other than the lower electrode removal part.
Forming a lower electrode so as to cover the side surface of the groove, forming a capacitor by sequentially covering the lower electrode with a capacitor insulating film and an upper electrode, and forming a gate insulating film on the surface of the island region. Forming a gate electrode at a position passing above the portion where the conductive film is removed, forming a pair of second conductive type diffusion layers , one of which is connected to the second conductive type connection region; Forming a switching transistor in which the semiconductor substrate region sandwiched by the second conductivity type diffusion layers does not face the lower electrode.

Hereinafter, embodiments of the present invention will be described.
Before that, however, related technologies related to the present invention were described.
Keep it.

FIG. 1A shows a first related art D of the present invention.
FIG. 1B is a plan view of the RAM cell, and FIG.
It is a line sectional view.

A drain region 2 and a source region 3 made of an n-type diffusion layer are formed on the surface of a p-type silicon substrate 1, and a word line made of polycrystalline silicon provided via a gate oxide film 8 is formed. A switching transistor having the gate electrode 4 is formed. A bit line 13 is connected to the drain region 2 via a bit line contact 12. On the other hand, as a component of the capacitor, p
A groove 5 is dug in the mold silicon substrate 1, an insulating film 6A made of, for example, a silicon oxide film is formed on the inner surface thereof, and a storage electrode 7A (lower electrode) made of polycrystalline silicon is formed thereon. The upper end of the storage electrode 7A is formed below the lower end of the impurity-doped region (n-type diffusion layer) constituting the drain region 2 and the source region 3, and is located between the drain region 2 and the source region 3. Are not arranged in the portion facing the channel portion. Therefore, there is no parasitic MOS transistor in which the side surface of the channel portion is a parasitic channel and the storage electrode 7A is a parasitic gate electrode. Therefore, even if a high voltage is written as information to the storage electrode 7A, no leakage current is generated due to the presence of the parasitic MOS transistor. Further, a capacitor is formed by the capacitor insulating film 9A on the storage electrode 7A and the cell plate 10A (lower electrode) subsequently formed thereon.

A method of manufacturing the DRAM cell shown in FIG. 1 will be described. First, as shown in FIG. 2, the p-type silicon substrate 1 is thermally oxidized to form a sacrificial silicon oxide film 15,
Subsequently, after a silicon nitride film 16 is formed by a CVD method, etching is performed through the silicon nitride film 16 and the sacrificial silicon oxide film 15 to form a groove 5 (0.4 μm in width and 1 μm in depth) in the p-type silicon substrate 1. To divide the island-shaped region 14. Next, thermal oxidation is performed to form an insulating film 6 having a thickness of 70 nm on the side and bottom surfaces of the groove, as shown in FIG. Thereafter, a resist film 17 having an opening 18 on the upper surface of the silicon nitride film 16 from the side surface of the groove 5 is formed. Next, the insulating film 6 exposed at the opening 18 is removed by etching using a wet etching method, thereby forming an insulating film 6A having a connection portion 19, as shown in FIG. After stripping the resist film 17, the thickness is 150 n by the CVD method.
After the polycrystalline silicon film 21 having a thickness of m is deposited on the entire surface including the groove 5, impurities are introduced into the polycrystalline silicon film 21 by using, for example, a method of thermally diffusing phosphorus to give conductivity. By this method, a capacitance contact (n-type connection region 20) is formed.

Subsequently, the polycrystalline silicon film 21 is etched by using selective anisotropic etching to form the storage electrode 7A shown in FIG. At this time, the etching time is selected such that the upper end of the storage electrode 7A is lower than the lower ends of the drain region 2 and the source region 3 (FIG. 8) of the switching transistor described later. The position of the upper end of the storage electrode 7A may be a position approximately 200 nm lower than the sacrificial silicon oxide film 15 at present. At this time, no storage electrode 7A is formed on the insulating film 6A on the bottom surface of the groove 5, and the storage electrodes 7A between adjacent cells are completely separated. Next, the storage electrode 7A is thermally oxidized as shown in FIG.
A capacitor insulating film 9A is formed, and then a polycrystalline silicon film 21 is deposited by a CVD method. Thereafter, impurities are introduced into the polycrystalline silicon film 21 by, for example, thermally diffusing phosphorus. By performing selective anisotropic dry etching of the polycrystalline silicon film 21 from this state, a cell plate 10A is formed as shown in FIG.

Here, the case where the height of the cell plate 10A is lower than the upper end of the storage electrode 7A is shown. Further C
A silicon oxide film (not shown) is deposited thickly by the VD method, and the entire surface is etched back using a dry etching method, and is buried in the upper part of the groove 5 so as to be embedded in the isolation insulating film 11A.
(Shown by oblique lines in FIG. 7A). The figure shows that the sacrificial silicon oxide film 15
Is shown, but it may be higher than this position. Such as by using the phosphoric acid in this state, only the nitrided silicon film 16 is etched away, followed by a sacrificial silicon oxide film 15 is removed by etching with such as an aqueous solution of hydrofluoric acid.

Thereafter, as shown in FIG. 8, the exposed portion of the p-type silicon substrate 1 is thermally oxidized to form a gate oxide film 8.
Next, a word line 4 made of a polycrystalline silicon film or the like in which an impurity is diffused is formed, and in this state, arsenic is implanted at an acceleration energy of 100 keV and a dose of 5 × 10 ¹⁵ cm ⁻² to form a drain region 2 and a source region 3. I do. According to this condition, the depth of the drain region 2 and the source region 3 is 150 nm.
As shown in the figure, the drain electrode 2, the source electrode 3, and the channel portion between them are not arranged to face the storage electrode 7. Next, as shown in FIG. 1, after depositing an interlayer insulating film 22 made of a silicon oxide film by a CVD method,
By opening the bit line contact 12 and forming the bit line 13 using, for example, polycide in which a tungsten silicide film and a polycrystalline silicon film are laminated,
A groove stacked capacitance type memory cell is obtained.

Next, an embodiment of the present invention will be described along its manufacturing steps.

The first related art In the storage electrode 7A entire drain region 2 as shown in FIG. 5, deeper than the source region 3 (below) is a polycrystalline silicon film 21 to come into position was etched, the In the embodiment of the present invention , as shown in FIG. 9, the polycrystalline silicon film 21A can be separated between adjacent cells.
It should be lower than the sacrificial silicon oxide film 15. Next, as shown in FIG. 10, a resist film 23 is applied so as to have an opening 24 and is patterned. In this state, the upper end of the polycrystalline silicon film 21A is moved to the position (FIG. 5) shown in the first embodiment. When the etching is performed, only the portion exposed from the opening 24 is etched as illustrated.

After removing the resist film 23, the polycrystalline silicon film 21A is thermally oxidized to obtain the storage electrode 7B covered with the capacitor insulating film 9B shown in FIG. In the storage electrode 7B, lower electrode removing portions 25 are provided on both sides of the island region. From this state, in the same manner as in the first embodiment, as shown in FIG. 12, a cell plate 10B and an isolation insulating film 11B are formed, and the word line 4 is connected to a portion where the upper end of the storage electrode 7B is deeper (lower electrode). It is formed at a position that passes above the removal section 25). Thereafter, if arsenic is implanted under the conditions described in the first embodiment, the storage electrode 7B contacts the drain region 2 and the source region 3 via the insulating film 6A, but the channel portion does not face the storage electrode 7B. Parasitic M
The first is to reduce the leakage current by the OS transistor.
The same effect as the related art can be obtained.

[0021] The difference between the first related art, the first of Seki
In the continuous technology , the height of the entire storage electrode is reduced, but the lowered storage electrode is manifested as a decrease in the storage capacity. However, in the embodiment of the present invention, it does not exist areas of storage electrode, since the portion between the drain region and the source region small, reduction in the storage capacity due to it, the first related technique
It has the advantage of being smaller than the art . Similarly, a change in the etching amount at the time of forming the storage electrode leads to a change in the storage capacitance. However, in the embodiment of the present invention , since the lower electrode removal portion by etching is small with respect to the entire storage capacitance, the change in the etching amount results. The variation of the storage capacity is also reduced.
That is, from the viewpoint of manufacturing the memory cell, there is an advantage that there is a margin for controlling the storage capacity and the etching stop.

Next, a second related art of the present invention will be described.

After the step corresponding to FIG. 6 in the first related art , as shown in FIG.
Is applied. Next, by selectively etching the resist film 26, as shown in FIG. 14, the resist film 26A is left only in the groove portion (indicated by oblique lines in FIG. 14A). Next, the polycrystalline silicon film 21 is etched, and FIG.
As shown in FIG. 5, the polycrystalline silicon film 21A is left only around the island region. Next, the resist film 26A is removed, and thermal oxidation is performed using the silicon nitride film 16 as a mask to form an isolation insulating film 11C as shown in FIG. At this time, the polycrystalline silicon film 2 remaining without being oxidized
1A becomes the cell plate 10C. Subsequently, a gate oxide film 8, a gate electrode (4), a drain region 2, and a source region 3
Etc. are formed.

The second related technology is a first related technology,
Instead of forming and etching a silicon oxide film by a CVD method for embedding an isolation insulating film in the trench 5 as in the embodiment of the present invention , element isolation and cell plate formation by deposition and oxidation of a polycrystalline silicon film. Has the advantage that the process can be simplified.

Next, a third related technique of the present invention will be described. In the third related art , FIG.
Relatively thin polycrystalline silicon film 2 in a process corresponding to
Instead of depositing No. 1, a thickness of 600 nm as shown in FIG.
Is deposited, and impurities are introduced by, for example, a method of thermally diffusing phosphorus. Thereafter, the polycrystalline silicon film 27 is etched by a selective anisotropic dry etching method, and the sacrificial silicon oxide film 15 is removed. Etching is stopped when the polycrystalline silicon film 27 is reduced to the height.
Subsequently, as shown in the first related art , the silicon nitride film 16 and the sacrificial silicon oxide film 15 are sequentially etched and removed, thereby forming the cell plate 10C as shown in FIG.
Get. From this state, similarly to the first related art , as shown in FIG. 19, the gate oxide film 8 (at this time, the silicon oxide film 28 is formed on the surface of the cell plate 10C), the word line 4, and the drain region. 2, to form a source region 3. In this structure, the cell plate 10C is
Through the drain region 2, the source region 3, and the channel portion. During operation of the memory cell, the cell plate 10C has 0 potential or 1 / (1) of the high potential stored as information.
Since the potential is fixed at two potentials, a small leakage current can be suppressed as compared with the case where the storage electrode 7A is in contact. this
In the third related technology , the first and second related technologies and the book
Although the effect of reducing the leakage current is smaller than that of the embodiment of the invention, the leakage current is smaller than that of the conventional cell structure, and the number of steps required for manufacturing is smaller than that of other related technologies and the embodiment of the present invention . It has advantages.

In the conventional memory cell structure, 64 Mbits D
In the case of RAM, when the substrate voltage is -1 V, the leakage current is 10 ^-6
A is about 10 A, whereas in the first, second and third embodiments of the present invention, it is 10 ⁻¹² A or less. As in the embodiment, it becomes 10 ^-12 A or less, which is ^{1/1 of} the power supply voltage.
Even when a potential of 2, for example 1.5 V is used, 10 ^-8
The leakage current can be reduced to about A.

[0027]

According to the present invention, in a trench stacked capacitance type memory cell having a structure in which a capacitor is buried in a trench formed around a switching transistor via an insulating film, the trench is sandwiched between a source region and a drain region. By providing the lower electrode (storage electrode) avoiding the portion facing the semiconductor substrate region and its vicinity, it is possible to suppress the occurrence of the sidewall parasitic MOS transistor which is a problem in the conventional example. Therefore, leakage current caused by the parasitic MOS transistor can be suppressed.

As a result, the holding characteristics, the stability of the memory operation, and the reliability are more advantageous than the conventional structure. In addition, since it basically adopts the structure of a groove stacked capacitance type memory cell, it secures a desired large storage capacity within a small cell occupation area, maintains a feature having high α-ray resistance, and is used in a highly integrated DRAM. This is a suitable memory cell.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1) showing a first related art of the present invention;
(A)) and sectional drawing (FIG.1 (b)).

2A and 2B are a plan view (FIG. 2A) and a cross-sectional view (FIG. 2B) for describing a manufacturing method according to a first related technique .

3A and 3B are a plan view (FIG. 3A) and a cross-sectional view (FIG. 3B) for describing a step subsequent to the step corresponding to FIG.

4A and 4B are a plan view (FIG. 4A) and a cross-sectional view (FIG. 4B) for explaining a step subsequent to the step corresponding to FIG.

5A and 5B are a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) for describing a step subsequent to the step corresponding to FIG.

6A and 6B are a plan view (FIG. 6A) and a cross-sectional view (FIG. 6B) for explaining a step following the step corresponding to FIG.

7A and 7B are a plan view (FIG. 7A) and a cross-sectional view (FIG. 7B) for explaining a step subsequent to the step corresponding to FIG.

8A and 8B are a plan view (FIG. 8A) and a cross-sectional view (FIG. 8B) for explaining a step following the step corresponding to FIG.

9A and 9B are a plan view (FIG. 9A) and a cross-sectional view (FIG. 9B) for describing an example of the present invention along the manufacturing process.

10 is a plan view (FIG. 10 (a)) and a cross-sectional view (FIG. 10 (b)) for explaining a step following the step corresponding to FIG.
It is.

FIG. 11 is a plan view (FIG. 11A) and a cross-sectional view (FIG. 11) for explaining a step following the step corresponding to FIG.
(B)).

FIG. 12 is a plan view (FIG. 12A) and a cross-sectional view (FIG. 12) for describing a step subsequent to the step corresponding to FIG.
(B)).

FIG. 13 is a plan view (FIG. 13) for explaining a second related art example of the present invention along its manufacturing process.
(A)) and sectional drawing (FIG. 13 (b)).

FIG. 14 is a plan view (FIG. 14A) and a cross-sectional view (FIG. 14) for describing a step subsequent to the step corresponding to FIG.
(B)).

15 is a plan view (FIG. 15A) and a cross-sectional view (FIG. 15) for describing a step subsequent to the step corresponding to FIG.
(B)).

FIG. 16 is a plan view (FIG. 16A) and a cross-sectional view (FIG. 16) for describing a step subsequent to the step corresponding to FIG.
(B)).

17A and 17B are a plan view (FIG. 17A) and a cross-sectional view (FIG. 17B) for describing a third related technique of the present invention along its manufacturing steps.

18 is a plan view (FIG. 18A) and a cross-sectional view (FIG. 18) for describing a step subsequent to the step corresponding to FIG.
(B)).

FIG. 19 is a plan view (FIG. 19A) and a cross-sectional view (FIG. 19) for describing a step following the step corresponding to FIG.
(B)).

FIG. 20 is a plan view showing a conventional DRAM cell (FIG. 20).
(A)) and sectional drawing (FIG.20 (b)).

21 is a simplified perspective view (FIG. 21 (a)) and an equivalent circuit diagram (FIG. 21 (b)) for explaining the problems of the conventional example shown in FIG. 20.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 2 drain region 3 source region 4 word line 5 groove 6, 6A insulating film 7, 7A, 7B storage electrode 8 gate oxide film 9, 9A, 9B capacitor insulating film 10, 10A, 10B, 10C cell plate 1 , 11A, 11B, 11C Isolation insulating film 12 Bit line contact 13 Bit line 14 Island region 15 Sacrificial silicon oxide film 16 Silicon nitride film 17 Resist film 18 Opening 19 Connection 20 N-type connection region 21, 21A Polycrystalline silicon film 22 Interlayer insulating film 23 resist film 24 opening 25 lower electrode removing portion 26, 26A resist film 27 polycrystalline silicon film 28 silicon oxide film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-248158 (JP, A) JP-A-1-296658 (JP, A) JP-A-2-54575 (JP, A) JP-A-2- 275666 (JP, A) JP-A-63-207171 (JP, A) JP-A-63-241961 (JP, A) JP-A-2-28367 (JP, A) JP-A-61-144058 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/76 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57) [Claims] 1. A gate electrode provided on a surface of an island region defined by a groove formed in a first conductivity type semiconductor substrate via a gate insulating film, and a gate electrode formed on a surface portion of the island region, respectively. A switching transistor having a pair of second conductivity type diffusion layers, an insulating film covering side surfaces and a bottom surface of the groove, and an insulating film covering a side surface of the groove between the island-like regions via the insulating film; In a semiconductor memory device having a memory cell having a lower electrode connected to one of the conductive type diffusion layers, a capacitor insulating film covering the lower electrode, and a capacitor including an upper electrode covering the capacitor insulating film, the lower electrode is The switching
The switch is located below the gate electrode of the transistor.
Between the pair of second conductivity type diffusion layers of the switching transistor.
Lower electrode removal part where the part opposite to the enclosed part is removed
And the lower electrode is a region other than the lower electrode removal portion.
3. The semiconductor memory device according to claim 1 , wherein a side surface of said groove is covered . 2. A step of forming a groove from one main surface to the inside of the first conductivity type semiconductor substrate to partition an island region, a step of forming an insulating film covering side surfaces and a bottom surface of the groove, Forming a connection portion by locally removing a portion of the insulating film near the surface of the island region; and depositing a conductive film on the entire surface and diffusing impurities from the connection portion to the semiconductor substrate region near the connection portion. Forming a second conductivity type connection region, and removing at least two portions of the island-like region close to the surface of the semiconductor substrate in patterning the conductive film, thereby forming a lower electrode. , Switching
Below the region where the gate electrode of the transistor is to be formed,
A pair of second conductive type diffusion layers of a switching transistor
The part opposite to the part sandwiched between the planned areas has been removed
Having a lower electrode removing portion, and other than the lower electrode removing portion
Forming a lower electrode so as to cover the side surface of the groove in the region, and forming a capacitor by sequentially covering the lower electrode with a capacitor insulating film and an upper electrode,
A gate insulating film is formed on the surface of the island region, and a gate electrode is formed at a position passing above the portion where the conductive film is removed.
And forming a pair of second conductivity type diffusion layers , one of which is connected to the second conductivity type connection region, and the semiconductor substrate region sandwiched between the second conductivity type diffusion layers does not face the lower electrode Forming a switching transistor.