JPH1174475A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of the refreshing characteristic of a refined DRAM. SOLUTION: When contact holes 15 which connect one n-type semiconductor areas (sources or drains) 10a of MISFETs for selecting memory cell to capacitance elements for storing information, by dry-etching a silicon oxide film 12 covering the MISFETs for selecting memory cell, side wall spacers 18 are formed on the side walls of cavities formed at the end sections of element separating grooves 2 by the misalignment between the contact holes 15 and active areas. In addition, n-type semiconductor layers 12 for relieving electric field are formed in p-type wells 5 in areas deeper than the n-type semiconductor areas 10a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly, to a DRAM (Dynamic Integrated Circuit).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a random access memory (Random Access Memory).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor manufacturing process, a field insulating film using a local oxidation of silicon (LOCOS) method has been widely used. However, with the miniaturization of semiconductor devices, development of new alternative device isolation technologies has been promoted.

An element isolation groove formed by embedding an insulating film such as a silicon oxide film in a groove formed in a semiconductor substrate has a (a) element isolation interval which is smaller than that of a field oxide film formed by a LOCOS method. (B) easy control of the element isolation film thickness and easy setting of the field inversion voltage; and (c) prevention of inversion by separately implanting impurities between the side wall and the bottom in the trench. Since the layer can be separated from the element diffusion layer and the channel region, there is an advantage that it is advantageous for securing sub-threshold characteristics, reducing junction leakage, and reducing the back gate effect.

The outline of a process for forming an element isolation groove in a semiconductor substrate is as follows.

First, a semiconductor substrate is heat-treated to form a thin silicon oxide film (pad oxide film) on its main surface. This pad oxide film is formed for the purpose of reducing stress applied to the substrate when sintering (burning) the silicon oxide film buried in the groove later.

Next, a CVD (Chemica) is formed on the pad oxide film.
(l) A silicon nitride film is deposited by a vapor deposition method, and the silicon nitride film in the element isolation region is removed by etching using a photoresist film as a mask. Since the silicon nitride film has a property of being hardly oxidized, it is used as a mask for preventing oxidation of the substrate surface under the silicon nitride film. The silicon nitride film is also used as a mask when a groove is formed by etching the substrate.

Next, after forming a groove in the semiconductor substrate by etching using the silicon nitride film as a mask, the substrate is oxidized to form a thin silicon oxide film on the inner wall of the groove. This silicon oxide film is formed for the purpose of removing etching damage generated on the inner wall of the groove and alleviating the stress of the silicon oxide film embedded in the groove in a later step.

Next, after a silicon oxide film is deposited on the semiconductor substrate by the CVD method and the silicon oxide film is embedded in the groove, the semiconductor substrate is subjected to a heat treatment, so that the silicon oxide film embedded in the groove is removed. Perform baking (sintering).

Next, chemical mechanical polishing (Chemical Mechanic)
Al Polishing) is used to remove the silicon oxide film above the silicon nitride film and leave it only inside the groove, thereby forming an element isolation groove in which the silicon oxide film is embedded. After that, the silicon nitride film used as the oxidation mask is removed by etching, and then a high-concentration semiconductor layer for suppressing the parasitic MOSFET operation is formed at the bottom of the isolation trench by ion-implanting impurities into the semiconductor substrate. A semiconductor device such as a MISFET is formed in the active region.

The above-described technology for forming the element isolation groove is described in, for example, JP-A-2-260660, JP-A-4-303942, and JP-A-8-97277.

[0011]

In recent DRAMs, the size of an active region in which memory cells are formed and the distance between gate electrodes (word lines) of MISFETs for selecting memory cells are determined by photolithography in order to promote large capacity. By reducing the size to near the resolution limit of lithography, miniaturization of a memory cell is achieved.

Therefore, the memory cell selecting MISFET
Forming a contact hole for electrically connecting one of the semiconductor regions (source, drain) and the information storage capacitor by etching the insulating film deposited on the
When misalignment of the photoresist film serving as an etching mask occurs, a part of the contact hole deviates from the active region and overlaps with the element isolation groove.

At this time, if sufficient over-etching is performed to compensate for variations in the thickness of the insulating film and the etching rate and ensure conduction of the contact holes, the silicon oxide film embedded in the element isolation trench is also etched. A high impurity concentration semiconductor region (source, drain) formed by phosphorus diffusion from a phosphorus-doped polycrystalline silicon film embedded in a contact hole in a subsequent step suppresses a parasitic MOS operation formed at the bottom of the element isolation trench. Approaching the vicinity of the end of the element isolation trench with the high-concentration impurity layer. As a result, the expansion of the depletion layer extending from the semiconductor region when the storage electrode of the information storage capacitor is at a positive potential is suppressed, and the junction electric field in the semiconductor region increases, thereby deteriorating the refresh characteristics of the DRAM. Occurs.

An object of the present invention is to provide a technique capable of effectively suppressing the deterioration of the refresh characteristic which becomes a problem when a DRAM is miniaturized.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a semiconductor integrated circuit device according to the present invention, a memory cell selecting MIS is formed in an active region of a semiconductor substrate whose periphery is defined by an element isolation groove in which a first insulating film is embedded.
An FET is formed and the memory cell selecting MI is
An information storage capacitor is formed on a second insulating film covering the SFET, and one of a source and a drain of the memory cell selection MISFET and the information storage capacitor are formed through a contact hole formed in the second insulating film. And a device having a DRAM electrically connected to the active region, the device being caused by misalignment between the active region and the contact hole when at least the second insulating film is etched to form the contact hole. Sidewall spacers made of a third insulating film are formed on the side walls of the depressions of the separation grooves.

(2) The semiconductor integrated circuit device according to the present invention includes at least a source of the memory cell selecting MISFET;
An electric field relaxation semiconductor region of the same conductivity type as the source and the drain is formed at one bottom of the drain.

(3) In the semiconductor integrated circuit device of the present invention, a plug made of a phosphorus-doped polycrystalline silicon film, a metal film or a metal nitride film is embedded in the contact hole and the depression.

(4) In the semiconductor integrated circuit device of the present invention, a semiconductor layer for suppressing a parasitic MOSFET operation is formed at least at the bottom of the element isolation groove.

(5) In the semiconductor integrated circuit device according to the present invention, the diameter of the contact hole along the direction in which the word line extends is larger than the length of the active region along the direction.

(6) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) forming an element isolation groove in which a first insulating film is buried in a main surface of a semiconductor substrate; and (b) selecting a memory cell in an active region of the semiconductor substrate whose periphery is defined by the element isolation groove. Forming a MISFET, (c)
After forming a second insulating film on the memory cell selecting MISFET, a contact hole is formed on at least one of a source and a drain of the memory cell selecting MISFET by etching the second insulating film. (D) forming a third insulating film on the second insulating film including the inside of the contact hole;
By etching the insulating film, at least a sidewall of a dent of the element isolation groove caused by misalignment between the active region and the contact hole when the contact hole is formed is formed from the third insulating film. (E) forming an information storage capacitor electrically connected to one of the source and the drain of the memory cell selecting MISFET through the contact hole on the second insulating film. Forming step.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after forming the memory cell selecting MISFET, an impurity of the same conductivity type as the source and drain is ion-implanted into the semiconductor substrate. An electric field relaxation semiconductor region is formed at least on one of the bottoms of the source and the drain of the memory cell selection MISFET.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after the sidewall spacer is formed on the side wall of the dent, the phosphorus-doped polycrystalline silicon film and the metal film are formed inside the contact hole and the dent. Alternatively, a plug made of a metal nitride film is embedded.

(9) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the device isolation trench is formed in the main surface of the semiconductor substrate, and then the semiconductor substrate is ion-implanted with an impurity to at least isolate the device. A semiconductor layer for suppressing a parasitic MOSFET operation is formed at the bottom of the groove.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is an equivalent circuit diagram of a DRAM according to an embodiment of the present invention. As shown, the memory array (MARY) of the DRAM includes a plurality of word lines WL (WLn−1, WLn−1,
WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell that stores one bit of information is one memory cell selecting MISFET Qs
And one information storage capacitor C connected in series to the
It is composed of MISFETQ for memory cell selection
One of the source and drain of s is an information storage capacitor C
And the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is connected to a sense amplifier SA.

Next, a method of manufacturing the memory cell of the DRAM will be described in the order of steps with reference to FIGS.

First, FIG. 2 (a plan view showing a part of the memory array) and FIG. 3 (the left part of the figure is a sectional view taken along the line AA 'in FIG. 2, and the right part is the same line BB' in FIG. 2). (A cross-sectional view taken along the line), for example, on a main surface of a semiconductor substrate 1 made of single-crystal silicon having a p-type resistivity of about 10 Ωcm,
The island-shaped active regions L separated from each other by the element isolation grooves 2 are formed. The element isolation groove 2 is formed by etching an element isolation region of the semiconductor substrate 1 to form a groove.
A silicon oxide film 3 is deposited thereon by a CVD (Chemical Vapor Deposition) method, and then the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 3 and then the surface thereof is subjected to chemical mechanical polishing (CMP). It is formed by polishing by a method and leaving a part thereof inside the groove.

Next, as shown in FIG. 4, a p-type impurity (for example, boron) is ion-implanted into the semiconductor substrate 1 so that a p-type semiconductor layer for suppressing a parasitic MOSFET operation is formed at the bottom of the element isolation groove 2. 4, a p-type well 5 is formed in the active region L, and a p-type channel layer 6 for controlling the threshold voltage (Vth) of the MISFET is formed on the surface thereof. Due to these ion implantations, the p-type impurity concentration of the semiconductor substrate 1 after the process has a profile as shown in FIG. 5, for example.

Next, as shown in FIGS. 6 and 7, the surface of the p-type well 5 is wet-oxidized to
After forming the gate oxide film 7 of the ISFET, a gate electrode 8 (word line WL) is formed thereon. For the gate electrode 8 (word line WL), for example, a polycrystalline silicon film doped with P (phosphorus) is deposited on the semiconductor substrate 1 by a CVD method, and then a TiN film and a W film are deposited thereon by a sputtering method. Further, after a silicon nitride film 9 is deposited thereon by a CVD method, these films are patterned and formed by etching using a photoresist film as a mask.

Next, as shown in FIG. 8, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 2 to form an n-type semiconductor region 10 (source, drain), thereby selecting a memory cell. The MISFET Qs is formed.

Next, as shown in FIG.
(Word line WL) sidewall spacer 11 on the side wall
Is formed, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 2 so that n
The mold semiconductor layer 12 is formed. Sidewall spacer 1
1 is formed by, for example, anisotropically etching a silicon nitride film deposited on a semiconductor substrate 1 by a CVD method. Also, n
The type semiconductor layer 12 has a high impurity concentration formed at the bottom of the n-type semiconductor region 10 by phosphorus diffusion from a polycrystalline silicon film embedded in a contact hole above the n-type semiconductor region 10 (source, drain) in a later step. It is formed in a region deeper than the n-type semiconductor region.

Next, as shown in FIG.
After a silicon oxide film 13 is deposited thereon by a CVD method and its surface is flattened by a chemical mechanical polishing method, as shown in FIGS. 11 and 12, the n-type semiconductor region 10 (source,
The silicon oxide film 13 is dry-etched using the photoresist film 16 in which the upper portion of the drain) is opened as a mask, thereby forming the n-type semiconductor region 10 (source, drain).
A contact hole 14 is formed on one of the upper portions, and a contact hole 15 is formed on the other upper portion. N
One of the type semiconductor regions 10 (source and drain) is connected to a bit line through a contact hole 14, and the other is connected to a lower electrode of an information storage capacitor through a contact hole 15. Bit line and n-type semiconductor region 1
As shown in FIG. 12, the contact hole 14 that connects to the zero is formed in a substantially rectangular planar pattern partly extending above the element isolation groove 2.

When the silicon oxide film 13 is dry-etched to form the contact holes 14 and 15, if a misalignment occurs between the opening pattern of the photoresist film 16 and the pattern of the active region L, as shown in FIG. When sufficient overetching is performed to ensure the conduction of the contact holes 14 and 15 by compensating for variations in the insulating film thickness and the etching rate, a part of the silicon oxide film 3 buried in the element isolation trench 2 is simultaneously formed. Etched hollow 1
7, which causes deterioration of the refresh characteristic of the DRAM.

Therefore, in the present embodiment, after the photoresist film 16 is removed, as shown in FIGS. 13 and 14 (an enlarged view of a main part of FIG. 13), an insulating film deposited on the silicon oxide film 13 is formed. By anisotropically etching (for example, a silicon oxide film deposited by the CVD method), sidewall spacers 18 are formed on the side walls of the contact holes 14 and 15 and the side wall of the depression 17.

Next, as shown in FIGS. 15 and 16 (enlarged view of a main part of FIG. 15), a polycrystalline silicon film doped with phosphorus is deposited on the silicon oxide film 13 by a CVD method.
Next, the surface is polished by a chemical mechanical polishing method, and a part thereof is left inside the contact holes 14 and 15, thereby forming a polycrystalline silicon plug 19 inside the contact holes 14 and 15. At this time, the polycrystalline silicon plugs 19 are also buried in the depressions 17 formed at the bottoms of the contact holes 14 and 15.

Next, as shown in FIGS. 17 and 18 (enlarged view of the main part of FIG. 17), the semiconductor substrate 1 is subjected to a heat treatment, and a part of the phosphorus in the polycrystalline silicon film forming the plug 19 is reduced to a contact hole. N-type semiconductor regions 8 from the bottoms of 14 and 15
By diffusion into the (source, drain), the n-type semiconductor region 8 (source, drain) becomes the n-type semiconductor region 10a having a higher impurity concentration. Thus, the n-type impurity concentration of the semiconductor substrate 1 after the process is completed is, for example, as shown in FIG.
The profile is as shown in FIG.

Next, as shown in FIGS. 20 and 21,
A silicon oxide film 20 is deposited on the silicon oxide film 13 by a CVD method, and a through hole 21 is formed in the silicon oxide film 20 above the contact hole 14 by dry etching using a photoresist film as a mask. A bit line BL is formed on the film 20. FIG.
As shown in FIG. 0, the through-hole 21 is formed in a substantially rectangular plane pattern such that a part thereof extends from the active region L to the upper portion of the element isolation groove 2. Bit line BL
Is connected to the memory cell selecting MISFET Qs through the through hole 21 and the contact hole 14 thereunder.
Electrically connected to one of the n-type semiconductor regions 8 (source, drain). To form the bit line BL, for example, TiN is formed on the silicon oxide film 20 by sputtering.
After depositing the film and the W film, these films are patterned by dry etching using the photoresist film as a mask.

Thereafter, as shown in FIG.
A silicon oxide film 22 and a silicon nitride film 23 are deposited on the upper part of the contact hole 15 by a CVD method, and the silicon nitride film 23 and the silicon oxide films 22 and 20 on the contact hole 15 are removed by dry etching using a photoresist film as a mask. After removal to form a through hole 24, the silicon nitride film 23 is removed.
A memory cell selecting MIS is formed by forming an information storage capacitive element C having a laminated structure of a lower electrode (storage electrode) 25, a capacitor insulating film 26, and an upper electrode 27 on the top of the MIS.
D composed of FET Qs and connected in series
The memory cell of the RAM is substantially completed. The lower electrode 25 of the information storage capacitor C is made of, for example, a polycrystalline silicon film.
The upper electrode 27 is made of, for example, a TiN film. The capacitance insulating film 26 is made of, for example, a tantalum oxide film.

FIG. 23A shows the junction electric field of the semiconductor substrate 1 near the end of the contact hole when the substrate voltage is -1 V, the word line voltage is 0 V, and the storage electrode voltage is 2.4 V in the memory cell. It is a graph which shows distribution.

Here, assuming that the diameter of the contact hole 15 is the same as the length of the active region L in the short side direction, the active region L
When the misalignment of the contact hole 15 along the short side direction was the largest, the junction electric field was 0.32 MV / cm. Further, as shown in FIG.
Is minimum (= 0), the junction electric field is 0.25
MV / cm. On the other hand, as shown in FIG.
When the sidewall spacer 18 was not formed on the side wall of the depression 17, the junction electric field was 0.5 MV / cm when the misalignment of the contact hole 15 was maximum. That is, according to the present embodiment, even when the misalignment between the active region L and the contact hole 15 is the largest, the junction electric field can be reduced as compared with a case where the sidewall spacer 18 is not formed on the side wall of the recess 17. Was completed. Specifically, the information retention time when the side wall spacer 18 was not formed on the side wall of the recess 17 was about 10 msec, whereas in the present embodiment it was about 100 msec.

This is because, as shown in FIG. 24, when the storage electrode where the refresh characteristic becomes a problem has a positive potential,
The active region portion in contact with the sidewall spacer 18 formed on the side wall of the pn junction is depleted (or inverted), whereby the depletion layer 30 at the pn junction expands. It is thought that it is. That is, in the present embodiment, when the storage electrode where the refresh characteristic becomes a problem has a positive potential, the depletion layer 30 expands greatly, so that the junction electric field is relaxed in a self-aligned manner. An n-type semiconductor layer 1 for electric field relaxation is provided in a region deeper than the n-type semiconductor region 10a having a high impurity concentration.
By forming 2, even when the misalignment of the contact hole 15 is minimum (= 0), the junction electric field is reduced to some extent.

(Embodiment 2) As shown in FIGS. 25 and 26, in the DRAM of the present embodiment, the diameter of the contact hole 15 along the direction parallel to the word line WL is adjusted in the short side direction of the active region L. When the misalignment between the active region L and the contact hole 15 is the largest, a depression 17 is formed in the element isolation groove 2 on both sides of the active region L. Further, the sidewall spacers 18 are formed on the side walls of the contact holes 15 and the recesses 17 by the above-described method. In this case, the p-type impurity concentration of the semiconductor substrate 1 after the process has a profile as shown in FIG. 27, for example.

According to the present embodiment, the active region portions in contact with the sidewall spacers 18 formed on the side walls of the recess 17 on both sides of the active region L are depleted (or inverted), thereby depleting the pn junction. Because the layers spread,
The expansion of the depletion layer is larger than in the first embodiment, in which the depletion layer expands only on one side of the active region L. As a result, the junction electric field is 0.21 MV / cm on both sides of the active region L, the information retention time is about 250 to 350 msec, and the refresh characteristics can be further improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above embodiment, the plug material to be buried in the contact hole above the n-type semiconductor region (source, drain) is made of a polycrystalline silicon film. However, a metal film such as W or a metal nitride film such as TiN is used. A plug may be configured.

FIG. 28 shows the expansion of the depletion layer 30 when the W / TiN film 28 is buried in the contact hole 15 as a plug material. As shown in FIG.
A depletion layer 30 is formed in the W / TiN film 28 embedded in the recess 17.
However, when the side wall spacers 18 are provided on the side walls of the depressions 17 as shown in FIG. 3B, the contact between the W / TiN film 28 and the depletion layer 30 is increased. Can be reliably prevented.

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, by forming the side wall spacer on the side wall of the recess of the element isolation groove, the expansion of the depletion layer of the n-type semiconductor region (source and drain) is increased to reduce the junction electric field. DRA
Deterioration of refresh characteristics when M is miniaturized can be suppressed.

According to the present invention, misalignment between the active region and the contact hole can be tolerated.
The process design margin when the DRAM is miniaturized can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a plan view of a principal part of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 5 is a graph showing a p-type impurity concentration profile of the semiconductor substrate on which the DRAM according to the first embodiment of the present invention is formed;

FIG. 6 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 11 is a plan view of a principal part of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is an enlarged fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is an enlarged cross-sectional view of a main part of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is an enlarged cross-sectional view of a principal part of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a graph showing an n-type impurity concentration profile of a semiconductor substrate on which a DRAM according to the first embodiment of the present invention is formed.

FIG. 20 is an essential part plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

23A and 23B are graphs showing a junction electric field distribution of a semiconductor substrate on which a DRAM according to the first embodiment of the present invention is formed, and FIG. 23C is a graph showing a junction electric field distribution of a comparative example. It is.

FIG. 24 is an explanatory diagram showing a spread of a depletion layer at a pn junction of a semiconductor substrate on which a DRAM according to the first embodiment of the present invention is formed;

FIG. 25 is a main-portion plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 26 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a DRAM according to a second embodiment of the present invention;

FIG. 27 is a graph showing a p-type impurity concentration profile of a semiconductor substrate on which a DRAM according to the second embodiment of the present invention is formed;

FIGS. 28A and 28B are explanatory diagrams showing the expansion of a depletion layer when a W / TiN film is buried inside a contact hole.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation groove 3 silicon oxide film 4 p-type semiconductor layer 5 p-type well 6 p-type channel layer 7 gate oxide film 8 gate electrode 9 silicon nitride film 10 n-type semiconductor region (source, drain) 10 an n-type semiconductor Region (source, drain) 11 Sidewall spacer 12 N-type semiconductor layer 13 Silicon oxide film 14, 15 Contact hole 16 Photoresist film 17 Depression 18 Sidewall spacer 19 Plug 20 Silicon oxide film 21 Through hole 22 Silicon oxide film 23 Silicon nitride Film 24 Through hole 25 Lower electrode (storage electrode) 26 Capacitive insulating film 27 Upper electrode 28 W / TiN film 30 Depletion layer BL Bit line C Information storage capacitor L Active area Qs Memory cell selection MISFET WL Word line

Continued on the front page (72) Inventor Yutaka Ito 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Kozo Watanabe 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Manufacturing Division

Claims (9)

[Claims] An MISFET for selecting a memory cell is formed in an active region of a semiconductor substrate whose periphery is defined by an element isolation groove in which a first insulating film is buried, and a second insulating layer covering the MISFET for selecting a memory cell. An information storage capacitive element is formed on the film, and the memory cell selecting M is formed through a contact hole formed in the second insulating film.
A semiconductor integrated circuit device having a DRAM in which one of a source and a drain of an ISFET is electrically connected to the information storage capacitor, wherein at least the second insulating film is etched to form the contact hole. A side wall spacer made of a third insulating film is formed on a side wall of a recess of the element isolation groove caused by misalignment between the active region and the contact hole. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein at least a bottom of one of a source and a drain of the memory cell selecting MISFET has the same conductivity type as the source and the drain. Wherein the semiconductor integrated circuit device is formed. 3. The semiconductor integrated circuit device according to claim 1, wherein a plug made of a phosphorus-doped polycrystalline silicon film, a metal film, or a metal nitride film is embedded in said contact hole and said recess. A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein a semiconductor layer for suppressing a parasitic MOSFET operation is formed at least at a bottom of said isolation trench. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein a diameter of said contact hole along a direction in which a word line extends is smaller than a diameter of said active region along said direction. A semiconductor integrated circuit device having a length greater than a length. 6. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming an element isolation groove in which a first insulating film is embedded in a main surface of a semiconductor substrate; (b) Forming a MISFET for selecting a memory cell in an active region of a semiconductor substrate whose periphery is defined by the isolation trench; (c) forming a second insulating film on the MISFET for selecting a memory cell; Forming a contact hole on at least one of the source and the drain of the memory cell selecting MISFET by etching the insulating film; and (d) forming a third hole on the second insulating film including the inside of the contact hole. After forming the insulating film, the third insulating film is etched, so that at least the contact region is formed at the time of forming the contact hole. Forming a sidewall spacer made of the third insulating film on a side wall of the recess of the element isolation groove caused by misalignment with the through hole; and (e) forming the contact on the upper side of the second insulating film. Forming an information storage capacitor electrically connected to one of a source and a drain of the memory cell selection MISFET through the hole; 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein after forming said memory cell selecting MISFET, impurities of the same conductivity type as said source and drain are ion-implanted into said semiconductor substrate. By doing
A method for manufacturing a semiconductor integrated circuit device, comprising: forming an electric field relaxation semiconductor region at least at a bottom of one of a source and a drain of the memory cell selection MISFET. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein after forming the side wall spacer on a side wall of the depression, the phosphorus-doped polycrystal is formed inside the contact hole and the depression. A method for manufacturing a semiconductor integrated circuit device, wherein a plug made of a silicon film, a metal film, or a metal nitride film is embedded. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the element isolation trench is formed in a main surface of the semiconductor substrate, and then an impurity is ion-implanted into the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, wherein a semiconductor layer for suppressing a parasitic MOSFET operation is formed at least at a bottom of the element isolation groove.